xref: /llvm-project/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp (revision 7da22dfcd06a2df056f10913dccae8f6b28f79ef) 
1 //===-- SystemZAsmParser.cpp - Parse SystemZ assembly instructions --------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "MCTargetDesc/SystemZInstPrinter.h"
10 #include "MCTargetDesc/SystemZMCAsmInfo.h"
11 #include "MCTargetDesc/SystemZMCTargetDesc.h"
12 #include "TargetInfo/SystemZTargetInfo.h"
13 #include "llvm/ADT/STLExtras.h"
14 #include "llvm/ADT/SmallVector.h"
15 #include "llvm/ADT/StringRef.h"
16 #include "llvm/MC/MCAsmInfo.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstBuilder.h"
21 #include "llvm/MC/MCParser/MCAsmLexer.h"
22 #include "llvm/MC/MCParser/MCAsmParser.h"
23 #include "llvm/MC/MCParser/MCAsmParserExtension.h"
24 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
25 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
26 #include "llvm/MC/MCStreamer.h"
27 #include "llvm/MC/MCSubtargetInfo.h"
28 #include "llvm/Support/Casting.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/SMLoc.h"
31 #include "llvm/Support/TargetRegistry.h"
32 #include <algorithm>
33 #include <cassert>
34 #include <cstddef>
35 #include <cstdint>
36 #include <iterator>
37 #include <memory>
38 #include <string>
39 
40 using namespace llvm;
41 
42 // Return true if Expr is in the range [MinValue, MaxValue].
43 static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue) {
44   if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
45     int64_t Value = CE->getValue();
46     return Value >= MinValue && Value <= MaxValue;
47   }
48   return false;
49 }
50 
51 namespace {
52 
53 enum RegisterKind {
54   GR32Reg,
55   GRH32Reg,
56   GR64Reg,
57   GR128Reg,
58   FP32Reg,
59   FP64Reg,
60   FP128Reg,
61   VR32Reg,
62   VR64Reg,
63   VR128Reg,
64   AR32Reg,
65   CR64Reg,
66 };
67 
68 enum MemoryKind {
69   BDMem,
70   BDXMem,
71   BDLMem,
72   BDRMem,
73   BDVMem
74 };
75 
76 class SystemZOperand : public MCParsedAsmOperand {
77 private:
78   enum OperandKind {
79     KindInvalid,
80     KindToken,
81     KindReg,
82     KindImm,
83     KindImmTLS,
84     KindMem
85   };
86 
87   OperandKind Kind;
88   SMLoc StartLoc, EndLoc;
89 
90   // A string of length Length, starting at Data.
91   struct TokenOp {
92     const char *Data;
93     unsigned Length;
94   };
95 
96   // LLVM register Num, which has kind Kind.  In some ways it might be
97   // easier for this class to have a register bank (general, floating-point
98   // or access) and a raw register number (0-15).  This would postpone the
99   // interpretation of the operand to the add*() methods and avoid the need
100   // for context-dependent parsing.  However, we do things the current way
101   // because of the virtual getReg() method, which needs to distinguish
102   // between (say) %r0 used as a single register and %r0 used as a pair.
103   // Context-dependent parsing can also give us slightly better error
104   // messages when invalid pairs like %r1 are used.
105   struct RegOp {
106     RegisterKind Kind;
107     unsigned Num;
108   };
109 
110   // Base + Disp + Index, where Base and Index are LLVM registers or 0.
111   // MemKind says what type of memory this is and RegKind says what type
112   // the base register has (GR32Reg or GR64Reg).  Length is the operand
113   // length for D(L,B)-style operands, otherwise it is null.
114   struct MemOp {
115     unsigned Base : 12;
116     unsigned Index : 12;
117     unsigned MemKind : 4;
118     unsigned RegKind : 4;
119     const MCExpr *Disp;
120     union {
121       const MCExpr *Imm;
122       unsigned Reg;
123     } Length;
124   };
125 
126   // Imm is an immediate operand, and Sym is an optional TLS symbol
127   // for use with a __tls_get_offset marker relocation.
128   struct ImmTLSOp {
129     const MCExpr *Imm;
130     const MCExpr *Sym;
131   };
132 
133   union {
134     TokenOp Token;
135     RegOp Reg;
136     const MCExpr *Imm;
137     ImmTLSOp ImmTLS;
138     MemOp Mem;
139   };
140 
141   void addExpr(MCInst &Inst, const MCExpr *Expr) const {
142     // Add as immediates when possible.  Null MCExpr = 0.
143     if (!Expr)
144       Inst.addOperand(MCOperand::createImm(0));
145     else if (auto *CE = dyn_cast<MCConstantExpr>(Expr))
146       Inst.addOperand(MCOperand::createImm(CE->getValue()));
147     else
148       Inst.addOperand(MCOperand::createExpr(Expr));
149   }
150 
151 public:
152   SystemZOperand(OperandKind kind, SMLoc startLoc, SMLoc endLoc)
153       : Kind(kind), StartLoc(startLoc), EndLoc(endLoc) {}
154 
155   // Create particular kinds of operand.
156   static std::unique_ptr<SystemZOperand> createInvalid(SMLoc StartLoc,
157                                                        SMLoc EndLoc) {
158     return std::make_unique<SystemZOperand>(KindInvalid, StartLoc, EndLoc);
159   }
160 
161   static std::unique_ptr<SystemZOperand> createToken(StringRef Str, SMLoc Loc) {
162     auto Op = std::make_unique<SystemZOperand>(KindToken, Loc, Loc);
163     Op->Token.Data = Str.data();
164     Op->Token.Length = Str.size();
165     return Op;
166   }
167 
168   static std::unique_ptr<SystemZOperand>
169   createReg(RegisterKind Kind, unsigned Num, SMLoc StartLoc, SMLoc EndLoc) {
170     auto Op = std::make_unique<SystemZOperand>(KindReg, StartLoc, EndLoc);
171     Op->Reg.Kind = Kind;
172     Op->Reg.Num = Num;
173     return Op;
174   }
175 
176   static std::unique_ptr<SystemZOperand>
177   createImm(const MCExpr *Expr, SMLoc StartLoc, SMLoc EndLoc) {
178     auto Op = std::make_unique<SystemZOperand>(KindImm, StartLoc, EndLoc);
179     Op->Imm = Expr;
180     return Op;
181   }
182 
183   static std::unique_ptr<SystemZOperand>
184   createMem(MemoryKind MemKind, RegisterKind RegKind, unsigned Base,
185             const MCExpr *Disp, unsigned Index, const MCExpr *LengthImm,
186             unsigned LengthReg, SMLoc StartLoc, SMLoc EndLoc) {
187     auto Op = std::make_unique<SystemZOperand>(KindMem, StartLoc, EndLoc);
188     Op->Mem.MemKind = MemKind;
189     Op->Mem.RegKind = RegKind;
190     Op->Mem.Base = Base;
191     Op->Mem.Index = Index;
192     Op->Mem.Disp = Disp;
193     if (MemKind == BDLMem)
194       Op->Mem.Length.Imm = LengthImm;
195     if (MemKind == BDRMem)
196       Op->Mem.Length.Reg = LengthReg;
197     return Op;
198   }
199 
200   static std::unique_ptr<SystemZOperand>
201   createImmTLS(const MCExpr *Imm, const MCExpr *Sym,
202                SMLoc StartLoc, SMLoc EndLoc) {
203     auto Op = std::make_unique<SystemZOperand>(KindImmTLS, StartLoc, EndLoc);
204     Op->ImmTLS.Imm = Imm;
205     Op->ImmTLS.Sym = Sym;
206     return Op;
207   }
208 
209   // Token operands
210   bool isToken() const override {
211     return Kind == KindToken;
212   }
213   StringRef getToken() const {
214     assert(Kind == KindToken && "Not a token");
215     return StringRef(Token.Data, Token.Length);
216   }
217 
218   // Register operands.
219   bool isReg() const override {
220     return Kind == KindReg;
221   }
222   bool isReg(RegisterKind RegKind) const {
223     return Kind == KindReg && Reg.Kind == RegKind;
224   }
225   unsigned getReg() const override {
226     assert(Kind == KindReg && "Not a register");
227     return Reg.Num;
228   }
229 
230   // Immediate operands.
231   bool isImm() const override {
232     return Kind == KindImm;
233   }
234   bool isImm(int64_t MinValue, int64_t MaxValue) const {
235     return Kind == KindImm && inRange(Imm, MinValue, MaxValue);
236   }
237   const MCExpr *getImm() const {
238     assert(Kind == KindImm && "Not an immediate");
239     return Imm;
240   }
241 
242   // Immediate operands with optional TLS symbol.
243   bool isImmTLS() const {
244     return Kind == KindImmTLS;
245   }
246 
247   const ImmTLSOp getImmTLS() const {
248     assert(Kind == KindImmTLS && "Not a TLS immediate");
249     return ImmTLS;
250   }
251 
252   // Memory operands.
253   bool isMem() const override {
254     return Kind == KindMem;
255   }
256   bool isMem(MemoryKind MemKind) const {
257     return (Kind == KindMem &&
258             (Mem.MemKind == MemKind ||
259              // A BDMem can be treated as a BDXMem in which the index
260              // register field is 0.
261              (Mem.MemKind == BDMem && MemKind == BDXMem)));
262   }
263   bool isMem(MemoryKind MemKind, RegisterKind RegKind) const {
264     return isMem(MemKind) && Mem.RegKind == RegKind;
265   }
266   bool isMemDisp12(MemoryKind MemKind, RegisterKind RegKind) const {
267     return isMem(MemKind, RegKind) && inRange(Mem.Disp, 0, 0xfff);
268   }
269   bool isMemDisp20(MemoryKind MemKind, RegisterKind RegKind) const {
270     return isMem(MemKind, RegKind) && inRange(Mem.Disp, -524288, 524287);
271   }
272   bool isMemDisp12Len4(RegisterKind RegKind) const {
273     return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length.Imm, 1, 0x10);
274   }
275   bool isMemDisp12Len8(RegisterKind RegKind) const {
276     return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length.Imm, 1, 0x100);
277   }
278 
279   const MemOp& getMem() const {
280     assert(Kind == KindMem && "Not a Mem operand");
281     return Mem;
282   }
283 
284   // Override MCParsedAsmOperand.
285   SMLoc getStartLoc() const override { return StartLoc; }
286   SMLoc getEndLoc() const override { return EndLoc; }
287   void print(raw_ostream &OS) const override;
288 
289   /// getLocRange - Get the range between the first and last token of this
290   /// operand.
291   SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
292 
293   // Used by the TableGen code to add particular types of operand
294   // to an instruction.
295   void addRegOperands(MCInst &Inst, unsigned N) const {
296     assert(N == 1 && "Invalid number of operands");
297     Inst.addOperand(MCOperand::createReg(getReg()));
298   }
299   void addImmOperands(MCInst &Inst, unsigned N) const {
300     assert(N == 1 && "Invalid number of operands");
301     addExpr(Inst, getImm());
302   }
303   void addBDAddrOperands(MCInst &Inst, unsigned N) const {
304     assert(N == 2 && "Invalid number of operands");
305     assert(isMem(BDMem) && "Invalid operand type");
306     Inst.addOperand(MCOperand::createReg(Mem.Base));
307     addExpr(Inst, Mem.Disp);
308   }
309   void addBDXAddrOperands(MCInst &Inst, unsigned N) const {
310     assert(N == 3 && "Invalid number of operands");
311     assert(isMem(BDXMem) && "Invalid operand type");
312     Inst.addOperand(MCOperand::createReg(Mem.Base));
313     addExpr(Inst, Mem.Disp);
314     Inst.addOperand(MCOperand::createReg(Mem.Index));
315   }
316   void addBDLAddrOperands(MCInst &Inst, unsigned N) const {
317     assert(N == 3 && "Invalid number of operands");
318     assert(isMem(BDLMem) && "Invalid operand type");
319     Inst.addOperand(MCOperand::createReg(Mem.Base));
320     addExpr(Inst, Mem.Disp);
321     addExpr(Inst, Mem.Length.Imm);
322   }
323   void addBDRAddrOperands(MCInst &Inst, unsigned N) const {
324     assert(N == 3 && "Invalid number of operands");
325     assert(isMem(BDRMem) && "Invalid operand type");
326     Inst.addOperand(MCOperand::createReg(Mem.Base));
327     addExpr(Inst, Mem.Disp);
328     Inst.addOperand(MCOperand::createReg(Mem.Length.Reg));
329   }
330   void addBDVAddrOperands(MCInst &Inst, unsigned N) const {
331     assert(N == 3 && "Invalid number of operands");
332     assert(isMem(BDVMem) && "Invalid operand type");
333     Inst.addOperand(MCOperand::createReg(Mem.Base));
334     addExpr(Inst, Mem.Disp);
335     Inst.addOperand(MCOperand::createReg(Mem.Index));
336   }
337   void addImmTLSOperands(MCInst &Inst, unsigned N) const {
338     assert(N == 2 && "Invalid number of operands");
339     assert(Kind == KindImmTLS && "Invalid operand type");
340     addExpr(Inst, ImmTLS.Imm);
341     if (ImmTLS.Sym)
342       addExpr(Inst, ImmTLS.Sym);
343   }
344 
345   // Used by the TableGen code to check for particular operand types.
346   bool isGR32() const { return isReg(GR32Reg); }
347   bool isGRH32() const { return isReg(GRH32Reg); }
348   bool isGRX32() const { return false; }
349   bool isGR64() const { return isReg(GR64Reg); }
350   bool isGR128() const { return isReg(GR128Reg); }
351   bool isADDR32() const { return isReg(GR32Reg); }
352   bool isADDR64() const { return isReg(GR64Reg); }
353   bool isADDR128() const { return false; }
354   bool isFP32() const { return isReg(FP32Reg); }
355   bool isFP64() const { return isReg(FP64Reg); }
356   bool isFP128() const { return isReg(FP128Reg); }
357   bool isVR32() const { return isReg(VR32Reg); }
358   bool isVR64() const { return isReg(VR64Reg); }
359   bool isVF128() const { return false; }
360   bool isVR128() const { return isReg(VR128Reg); }
361   bool isAR32() const { return isReg(AR32Reg); }
362   bool isCR64() const { return isReg(CR64Reg); }
363   bool isAnyReg() const { return (isReg() || isImm(0, 15)); }
364   bool isBDAddr32Disp12() const { return isMemDisp12(BDMem, GR32Reg); }
365   bool isBDAddr32Disp20() const { return isMemDisp20(BDMem, GR32Reg); }
366   bool isBDAddr64Disp12() const { return isMemDisp12(BDMem, GR64Reg); }
367   bool isBDAddr64Disp20() const { return isMemDisp20(BDMem, GR64Reg); }
368   bool isBDXAddr64Disp12() const { return isMemDisp12(BDXMem, GR64Reg); }
369   bool isBDXAddr64Disp20() const { return isMemDisp20(BDXMem, GR64Reg); }
370   bool isBDLAddr64Disp12Len4() const { return isMemDisp12Len4(GR64Reg); }
371   bool isBDLAddr64Disp12Len8() const { return isMemDisp12Len8(GR64Reg); }
372   bool isBDRAddr64Disp12() const { return isMemDisp12(BDRMem, GR64Reg); }
373   bool isBDVAddr64Disp12() const { return isMemDisp12(BDVMem, GR64Reg); }
374   bool isU1Imm() const { return isImm(0, 1); }
375   bool isU2Imm() const { return isImm(0, 3); }
376   bool isU3Imm() const { return isImm(0, 7); }
377   bool isU4Imm() const { return isImm(0, 15); }
378   bool isU6Imm() const { return isImm(0, 63); }
379   bool isU8Imm() const { return isImm(0, 255); }
380   bool isS8Imm() const { return isImm(-128, 127); }
381   bool isU12Imm() const { return isImm(0, 4095); }
382   bool isU16Imm() const { return isImm(0, 65535); }
383   bool isS16Imm() const { return isImm(-32768, 32767); }
384   bool isU32Imm() const { return isImm(0, (1LL << 32) - 1); }
385   bool isS32Imm() const { return isImm(-(1LL << 31), (1LL << 31) - 1); }
386   bool isU48Imm() const { return isImm(0, (1LL << 48) - 1); }
387 };
388 
389 class SystemZAsmParser : public MCTargetAsmParser {
390 #define GET_ASSEMBLER_HEADER
391 #include "SystemZGenAsmMatcher.inc"
392 
393 private:
394   MCAsmParser &Parser;
395   enum RegisterGroup {
396     RegGR,
397     RegFP,
398     RegV,
399     RegAR,
400     RegCR
401   };
402   struct Register {
403     RegisterGroup Group;
404     unsigned Num;
405     SMLoc StartLoc, EndLoc;
406   };
407 
408   bool parseRegister(Register &Reg, bool RestoreOnFailure = false);
409 
410   bool parseIntegerRegister(Register &Reg, RegisterGroup Group);
411 
412   OperandMatchResultTy parseRegister(OperandVector &Operands,
413                                      RegisterKind Kind);
414 
415   OperandMatchResultTy parseAnyRegister(OperandVector &Operands);
416 
417   bool parseAddress(bool &HaveReg1, Register &Reg1, bool &HaveReg2,
418                     Register &Reg2, const MCExpr *&Disp, const MCExpr *&Length,
419                     bool HasLength = false, bool HasVectorIndex = false);
420   bool parseAddressRegister(Register &Reg);
421 
422   bool ParseDirectiveInsn(SMLoc L);
423 
424   OperandMatchResultTy parseAddress(OperandVector &Operands,
425                                     MemoryKind MemKind,
426                                     RegisterKind RegKind);
427 
428   OperandMatchResultTy parsePCRel(OperandVector &Operands, int64_t MinVal,
429                                   int64_t MaxVal, bool AllowTLS);
430 
431   bool parseOperand(OperandVector &Operands, StringRef Mnemonic);
432 
433   // Both the hlasm and att variants still rely on the basic gnu asm
434   // format with respect to inputs, clobbers, outputs etc.
435   //
436   // However, calling the overriden getAssemblerDialect() method in
437   // AsmParser is problematic. It either returns the AssemblerDialect field
438   // in the MCAsmInfo instance if the AssemblerDialect field in AsmParser is
439   // unset, otherwise it returns the private AssemblerDialect field in
440   // AsmParser.
441   //
442   // The problematic part is because, we forcibly set the inline asm dialect
443   // in the AsmParser instance in AsmPrinterInlineAsm.cpp. Soo any query
444   // to the overriden getAssemblerDialect function in AsmParser.cpp, will
445   // not return the assembler dialect set in the respective MCAsmInfo instance.
446   //
447   // For this purpose, we explicitly query the SystemZMCAsmInfo instance
448   // here, to get the "correct" assembler dialect, and use it in various
449   // functions.
450   unsigned getMAIAssemblerDialect() {
451     return Parser.getContext().getAsmInfo()->getAssemblerDialect();
452   }
453 
454   // An alphabetic character in HLASM is a letter from 'A' through 'Z',
455   // or from 'a' through 'z', or '$', '_','#', or '@'.
456   inline bool isHLASMAlpha(char C) {
457     return isAlpha(C) || llvm::is_contained("_@#$", C);
458   }
459 
460   // A digit in HLASM is a number from 0 to 9.
461   inline bool isHLASMAlnum(char C) { return isHLASMAlpha(C) || isDigit(C); }
462 
463   // Are we parsing using the AD_HLASM dialect?
464   inline bool isParsingHLASM() { return getMAIAssemblerDialect() == AD_HLASM; }
465 
466   // Are we parsing using the AD_ATT dialect?
467   inline bool isParsingATT() { return getMAIAssemblerDialect() == AD_ATT; }
468 
469 public:
470   SystemZAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
471                    const MCInstrInfo &MII,
472                    const MCTargetOptions &Options)
473     : MCTargetAsmParser(Options, sti, MII), Parser(parser) {
474     MCAsmParserExtension::Initialize(Parser);
475 
476     // Alias the .word directive to .short.
477     parser.addAliasForDirective(".word", ".short");
478 
479     // Initialize the set of available features.
480     setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
481   }
482 
483   // Override MCTargetAsmParser.
484   bool ParseDirective(AsmToken DirectiveID) override;
485   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
486   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc,
487                      bool RestoreOnFailure);
488   OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc,
489                                         SMLoc &EndLoc) override;
490   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
491                         SMLoc NameLoc, OperandVector &Operands) override;
492   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
493                                OperandVector &Operands, MCStreamer &Out,
494                                uint64_t &ErrorInfo,
495                                bool MatchingInlineAsm) override;
496   bool isLabel(AsmToken &Token) override;
497 
498   // Used by the TableGen code to parse particular operand types.
499   OperandMatchResultTy parseGR32(OperandVector &Operands) {
500     return parseRegister(Operands, GR32Reg);
501   }
502   OperandMatchResultTy parseGRH32(OperandVector &Operands) {
503     return parseRegister(Operands, GRH32Reg);
504   }
505   OperandMatchResultTy parseGRX32(OperandVector &Operands) {
506     llvm_unreachable("GRX32 should only be used for pseudo instructions");
507   }
508   OperandMatchResultTy parseGR64(OperandVector &Operands) {
509     return parseRegister(Operands, GR64Reg);
510   }
511   OperandMatchResultTy parseGR128(OperandVector &Operands) {
512     return parseRegister(Operands, GR128Reg);
513   }
514   OperandMatchResultTy parseADDR32(OperandVector &Operands) {
515     // For the AsmParser, we will accept %r0 for ADDR32 as well.
516     return parseRegister(Operands, GR32Reg);
517   }
518   OperandMatchResultTy parseADDR64(OperandVector &Operands) {
519     // For the AsmParser, we will accept %r0 for ADDR64 as well.
520     return parseRegister(Operands, GR64Reg);
521   }
522   OperandMatchResultTy parseADDR128(OperandVector &Operands) {
523     llvm_unreachable("Shouldn't be used as an operand");
524   }
525   OperandMatchResultTy parseFP32(OperandVector &Operands) {
526     return parseRegister(Operands, FP32Reg);
527   }
528   OperandMatchResultTy parseFP64(OperandVector &Operands) {
529     return parseRegister(Operands, FP64Reg);
530   }
531   OperandMatchResultTy parseFP128(OperandVector &Operands) {
532     return parseRegister(Operands, FP128Reg);
533   }
534   OperandMatchResultTy parseVR32(OperandVector &Operands) {
535     return parseRegister(Operands, VR32Reg);
536   }
537   OperandMatchResultTy parseVR64(OperandVector &Operands) {
538     return parseRegister(Operands, VR64Reg);
539   }
540   OperandMatchResultTy parseVF128(OperandVector &Operands) {
541     llvm_unreachable("Shouldn't be used as an operand");
542   }
543   OperandMatchResultTy parseVR128(OperandVector &Operands) {
544     return parseRegister(Operands, VR128Reg);
545   }
546   OperandMatchResultTy parseAR32(OperandVector &Operands) {
547     return parseRegister(Operands, AR32Reg);
548   }
549   OperandMatchResultTy parseCR64(OperandVector &Operands) {
550     return parseRegister(Operands, CR64Reg);
551   }
552   OperandMatchResultTy parseAnyReg(OperandVector &Operands) {
553     return parseAnyRegister(Operands);
554   }
555   OperandMatchResultTy parseBDAddr32(OperandVector &Operands) {
556     return parseAddress(Operands, BDMem, GR32Reg);
557   }
558   OperandMatchResultTy parseBDAddr64(OperandVector &Operands) {
559     return parseAddress(Operands, BDMem, GR64Reg);
560   }
561   OperandMatchResultTy parseBDXAddr64(OperandVector &Operands) {
562     return parseAddress(Operands, BDXMem, GR64Reg);
563   }
564   OperandMatchResultTy parseBDLAddr64(OperandVector &Operands) {
565     return parseAddress(Operands, BDLMem, GR64Reg);
566   }
567   OperandMatchResultTy parseBDRAddr64(OperandVector &Operands) {
568     return parseAddress(Operands, BDRMem, GR64Reg);
569   }
570   OperandMatchResultTy parseBDVAddr64(OperandVector &Operands) {
571     return parseAddress(Operands, BDVMem, GR64Reg);
572   }
573   OperandMatchResultTy parsePCRel12(OperandVector &Operands) {
574     return parsePCRel(Operands, -(1LL << 12), (1LL << 12) - 1, false);
575   }
576   OperandMatchResultTy parsePCRel16(OperandVector &Operands) {
577     return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, false);
578   }
579   OperandMatchResultTy parsePCRel24(OperandVector &Operands) {
580     return parsePCRel(Operands, -(1LL << 24), (1LL << 24) - 1, false);
581   }
582   OperandMatchResultTy parsePCRel32(OperandVector &Operands) {
583     return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, false);
584   }
585   OperandMatchResultTy parsePCRelTLS16(OperandVector &Operands) {
586     return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, true);
587   }
588   OperandMatchResultTy parsePCRelTLS32(OperandVector &Operands) {
589     return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, true);
590   }
591 };
592 
593 } // end anonymous namespace
594 
595 #define GET_REGISTER_MATCHER
596 #define GET_SUBTARGET_FEATURE_NAME
597 #define GET_MATCHER_IMPLEMENTATION
598 #define GET_MNEMONIC_SPELL_CHECKER
599 #include "SystemZGenAsmMatcher.inc"
600 
601 // Used for the .insn directives; contains information needed to parse the
602 // operands in the directive.
603 struct InsnMatchEntry {
604   StringRef Format;
605   uint64_t Opcode;
606   int32_t NumOperands;
607   MatchClassKind OperandKinds[7];
608 };
609 
610 // For equal_range comparison.
611 struct CompareInsn {
612   bool operator() (const InsnMatchEntry &LHS, StringRef RHS) {
613     return LHS.Format < RHS;
614   }
615   bool operator() (StringRef LHS, const InsnMatchEntry &RHS) {
616     return LHS < RHS.Format;
617   }
618   bool operator() (const InsnMatchEntry &LHS, const InsnMatchEntry &RHS) {
619     return LHS.Format < RHS.Format;
620   }
621 };
622 
623 // Table initializing information for parsing the .insn directive.
624 static struct InsnMatchEntry InsnMatchTable[] = {
625   /* Format, Opcode, NumOperands, OperandKinds */
626   { "e", SystemZ::InsnE, 1,
627     { MCK_U16Imm } },
628   { "ri", SystemZ::InsnRI, 3,
629     { MCK_U32Imm, MCK_AnyReg, MCK_S16Imm } },
630   { "rie", SystemZ::InsnRIE, 4,
631     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
632   { "ril", SystemZ::InsnRIL, 3,
633     { MCK_U48Imm, MCK_AnyReg, MCK_PCRel32 } },
634   { "rilu", SystemZ::InsnRILU, 3,
635     { MCK_U48Imm, MCK_AnyReg, MCK_U32Imm } },
636   { "ris", SystemZ::InsnRIS, 5,
637     { MCK_U48Imm, MCK_AnyReg, MCK_S8Imm, MCK_U4Imm, MCK_BDAddr64Disp12 } },
638   { "rr", SystemZ::InsnRR, 3,
639     { MCK_U16Imm, MCK_AnyReg, MCK_AnyReg } },
640   { "rre", SystemZ::InsnRRE, 3,
641     { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg } },
642   { "rrf", SystemZ::InsnRRF, 5,
643     { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm } },
644   { "rrs", SystemZ::InsnRRS, 5,
645     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm, MCK_BDAddr64Disp12 } },
646   { "rs", SystemZ::InsnRS, 4,
647     { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
648   { "rse", SystemZ::InsnRSE, 4,
649     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
650   { "rsi", SystemZ::InsnRSI, 4,
651     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
652   { "rsy", SystemZ::InsnRSY, 4,
653     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp20 } },
654   { "rx", SystemZ::InsnRX, 3,
655     { MCK_U32Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
656   { "rxe", SystemZ::InsnRXE, 3,
657     { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
658   { "rxf", SystemZ::InsnRXF, 4,
659     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
660   { "rxy", SystemZ::InsnRXY, 3,
661     { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp20 } },
662   { "s", SystemZ::InsnS, 2,
663     { MCK_U32Imm, MCK_BDAddr64Disp12 } },
664   { "si", SystemZ::InsnSI, 3,
665     { MCK_U32Imm, MCK_BDAddr64Disp12, MCK_S8Imm } },
666   { "sil", SystemZ::InsnSIL, 3,
667     { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_U16Imm } },
668   { "siy", SystemZ::InsnSIY, 3,
669     { MCK_U48Imm, MCK_BDAddr64Disp20, MCK_U8Imm } },
670   { "ss", SystemZ::InsnSS, 4,
671     { MCK_U48Imm, MCK_BDXAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } },
672   { "sse", SystemZ::InsnSSE, 3,
673     { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12 } },
674   { "ssf", SystemZ::InsnSSF, 4,
675     { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } },
676   { "vri", SystemZ::InsnVRI, 6,
677     { MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_U12Imm, MCK_U4Imm, MCK_U4Imm } },
678   { "vrr", SystemZ::InsnVRR, 7,
679     { MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_VR128, MCK_U4Imm, MCK_U4Imm,
680       MCK_U4Imm } },
681   { "vrs", SystemZ::InsnVRS, 5,
682     { MCK_U48Imm, MCK_AnyReg, MCK_VR128, MCK_BDAddr64Disp12, MCK_U4Imm } },
683   { "vrv", SystemZ::InsnVRV, 4,
684     { MCK_U48Imm, MCK_VR128, MCK_BDVAddr64Disp12, MCK_U4Imm } },
685   { "vrx", SystemZ::InsnVRX, 4,
686     { MCK_U48Imm, MCK_VR128, MCK_BDXAddr64Disp12, MCK_U4Imm } },
687   { "vsi", SystemZ::InsnVSI, 4,
688     { MCK_U48Imm, MCK_VR128, MCK_BDAddr64Disp12, MCK_U8Imm } }
689 };
690 
691 static void printMCExpr(const MCExpr *E, raw_ostream &OS) {
692   if (!E)
693     return;
694   if (auto *CE = dyn_cast<MCConstantExpr>(E))
695     OS << *CE;
696   else if (auto *UE = dyn_cast<MCUnaryExpr>(E))
697     OS << *UE;
698   else if (auto *BE = dyn_cast<MCBinaryExpr>(E))
699     OS << *BE;
700   else if (auto *SRE = dyn_cast<MCSymbolRefExpr>(E))
701     OS << *SRE;
702   else
703     OS << *E;
704 }
705 
706 void SystemZOperand::print(raw_ostream &OS) const {
707   switch (Kind) {
708   case KindToken:
709     OS << "Token:" << getToken();
710     break;
711   case KindReg:
712     OS << "Reg:" << SystemZInstPrinter::getRegisterName(getReg());
713     break;
714   case KindImm:
715     OS << "Imm:";
716     printMCExpr(getImm(), OS);
717     break;
718   case KindImmTLS:
719     OS << "ImmTLS:";
720     printMCExpr(getImmTLS().Imm, OS);
721     if (getImmTLS().Sym) {
722       OS << ", ";
723       printMCExpr(getImmTLS().Sym, OS);
724     }
725     break;
726   case KindMem: {
727     const MemOp &Op = getMem();
728     OS << "Mem:" << *cast<MCConstantExpr>(Op.Disp);
729     if (Op.Base) {
730       OS << "(";
731       if (Op.MemKind == BDLMem)
732         OS << *cast<MCConstantExpr>(Op.Length.Imm) << ",";
733       else if (Op.MemKind == BDRMem)
734         OS << SystemZInstPrinter::getRegisterName(Op.Length.Reg) << ",";
735       if (Op.Index)
736         OS << SystemZInstPrinter::getRegisterName(Op.Index) << ",";
737       OS << SystemZInstPrinter::getRegisterName(Op.Base);
738       OS << ")";
739     }
740     break;
741   }
742   case KindInvalid:
743     break;
744   }
745 }
746 
747 // Parse one register of the form %<prefix><number>.
748 bool SystemZAsmParser::parseRegister(Register &Reg, bool RestoreOnFailure) {
749   Reg.StartLoc = Parser.getTok().getLoc();
750 
751   // Eat the % prefix.
752   if (Parser.getTok().isNot(AsmToken::Percent))
753     return Error(Parser.getTok().getLoc(), "register expected");
754   const AsmToken &PercentTok = Parser.getTok();
755   Parser.Lex();
756 
757   // Expect a register name.
758   if (Parser.getTok().isNot(AsmToken::Identifier)) {
759     if (RestoreOnFailure)
760       getLexer().UnLex(PercentTok);
761     return Error(Reg.StartLoc, "invalid register");
762   }
763 
764   // Check that there's a prefix.
765   StringRef Name = Parser.getTok().getString();
766   if (Name.size() < 2) {
767     if (RestoreOnFailure)
768       getLexer().UnLex(PercentTok);
769     return Error(Reg.StartLoc, "invalid register");
770   }
771   char Prefix = Name[0];
772 
773   // Treat the rest of the register name as a register number.
774   if (Name.substr(1).getAsInteger(10, Reg.Num)) {
775     if (RestoreOnFailure)
776       getLexer().UnLex(PercentTok);
777     return Error(Reg.StartLoc, "invalid register");
778   }
779 
780   // Look for valid combinations of prefix and number.
781   if (Prefix == 'r' && Reg.Num < 16)
782     Reg.Group = RegGR;
783   else if (Prefix == 'f' && Reg.Num < 16)
784     Reg.Group = RegFP;
785   else if (Prefix == 'v' && Reg.Num < 32)
786     Reg.Group = RegV;
787   else if (Prefix == 'a' && Reg.Num < 16)
788     Reg.Group = RegAR;
789   else if (Prefix == 'c' && Reg.Num < 16)
790     Reg.Group = RegCR;
791   else {
792     if (RestoreOnFailure)
793       getLexer().UnLex(PercentTok);
794     return Error(Reg.StartLoc, "invalid register");
795   }
796 
797   Reg.EndLoc = Parser.getTok().getLoc();
798   Parser.Lex();
799   return false;
800 }
801 
802 // Parse a register of kind Kind and add it to Operands.
803 OperandMatchResultTy
804 SystemZAsmParser::parseRegister(OperandVector &Operands, RegisterKind Kind) {
805   Register Reg;
806   RegisterGroup Group;
807   switch (Kind) {
808   case GR32Reg:
809   case GRH32Reg:
810   case GR64Reg:
811   case GR128Reg:
812     Group = RegGR;
813     break;
814   case FP32Reg:
815   case FP64Reg:
816   case FP128Reg:
817     Group = RegFP;
818     break;
819   case VR32Reg:
820   case VR64Reg:
821   case VR128Reg:
822     Group = RegV;
823     break;
824   case AR32Reg:
825     Group = RegAR;
826     break;
827   case CR64Reg:
828     Group = RegCR;
829     break;
830   }
831 
832   // Handle register names of the form %<prefix><number>
833   if (Parser.getTok().is(AsmToken::Percent)) {
834     if (parseRegister(Reg))
835       return MatchOperand_ParseFail;
836 
837     // Check the parsed register group "Reg.Group" with the expected "Group"
838     // Have to error out if user specified wrong prefix.
839     switch (Group) {
840     case RegGR:
841     case RegFP:
842     case RegAR:
843     case RegCR:
844       if (Group != Reg.Group) {
845         Error(Reg.StartLoc, "invalid operand for instruction");
846         return MatchOperand_ParseFail;
847       }
848       break;
849     case RegV:
850       if (Reg.Group != RegV && Reg.Group != RegFP) {
851         Error(Reg.StartLoc, "invalid operand for instruction");
852         return MatchOperand_ParseFail;
853       }
854       break;
855     }
856   } else if (Parser.getTok().is(AsmToken::Integer)) {
857     if (parseIntegerRegister(Reg, Group))
858       return MatchOperand_ParseFail;
859   }
860   // Otherwise we didn't match a register operand.
861   else
862     return MatchOperand_NoMatch;
863 
864   // Determine the LLVM register number according to Kind.
865   const unsigned *Regs;
866   switch (Kind) {
867   case GR32Reg:  Regs = SystemZMC::GR32Regs;  break;
868   case GRH32Reg: Regs = SystemZMC::GRH32Regs; break;
869   case GR64Reg:  Regs = SystemZMC::GR64Regs;  break;
870   case GR128Reg: Regs = SystemZMC::GR128Regs; break;
871   case FP32Reg:  Regs = SystemZMC::FP32Regs;  break;
872   case FP64Reg:  Regs = SystemZMC::FP64Regs;  break;
873   case FP128Reg: Regs = SystemZMC::FP128Regs; break;
874   case VR32Reg:  Regs = SystemZMC::VR32Regs;  break;
875   case VR64Reg:  Regs = SystemZMC::VR64Regs;  break;
876   case VR128Reg: Regs = SystemZMC::VR128Regs; break;
877   case AR32Reg:  Regs = SystemZMC::AR32Regs;  break;
878   case CR64Reg:  Regs = SystemZMC::CR64Regs;  break;
879   }
880   if (Regs[Reg.Num] == 0) {
881     Error(Reg.StartLoc, "invalid register pair");
882     return MatchOperand_ParseFail;
883   }
884 
885   Operands.push_back(
886       SystemZOperand::createReg(Kind, Regs[Reg.Num], Reg.StartLoc, Reg.EndLoc));
887   return MatchOperand_Success;
888 }
889 
890 // Parse any type of register (including integers) and add it to Operands.
891 OperandMatchResultTy
892 SystemZAsmParser::parseAnyRegister(OperandVector &Operands) {
893   SMLoc StartLoc = Parser.getTok().getLoc();
894 
895   // Handle integer values.
896   if (Parser.getTok().is(AsmToken::Integer)) {
897     const MCExpr *Register;
898     if (Parser.parseExpression(Register))
899       return MatchOperand_ParseFail;
900 
901     if (auto *CE = dyn_cast<MCConstantExpr>(Register)) {
902       int64_t Value = CE->getValue();
903       if (Value < 0 || Value > 15) {
904         Error(StartLoc, "invalid register");
905         return MatchOperand_ParseFail;
906       }
907     }
908 
909     SMLoc EndLoc =
910       SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
911 
912     Operands.push_back(SystemZOperand::createImm(Register, StartLoc, EndLoc));
913   }
914   else {
915     Register Reg;
916     if (parseRegister(Reg))
917       return MatchOperand_ParseFail;
918 
919     if (Reg.Num > 15) {
920       Error(StartLoc, "invalid register");
921       return MatchOperand_ParseFail;
922     }
923 
924     // Map to the correct register kind.
925     RegisterKind Kind;
926     unsigned RegNo;
927     if (Reg.Group == RegGR) {
928       Kind = GR64Reg;
929       RegNo = SystemZMC::GR64Regs[Reg.Num];
930     }
931     else if (Reg.Group == RegFP) {
932       Kind = FP64Reg;
933       RegNo = SystemZMC::FP64Regs[Reg.Num];
934     }
935     else if (Reg.Group == RegV) {
936       Kind = VR128Reg;
937       RegNo = SystemZMC::VR128Regs[Reg.Num];
938     }
939     else if (Reg.Group == RegAR) {
940       Kind = AR32Reg;
941       RegNo = SystemZMC::AR32Regs[Reg.Num];
942     }
943     else if (Reg.Group == RegCR) {
944       Kind = CR64Reg;
945       RegNo = SystemZMC::CR64Regs[Reg.Num];
946     }
947     else {
948       return MatchOperand_ParseFail;
949     }
950 
951     Operands.push_back(SystemZOperand::createReg(Kind, RegNo,
952                                                  Reg.StartLoc, Reg.EndLoc));
953   }
954   return MatchOperand_Success;
955 }
956 
957 bool SystemZAsmParser::parseIntegerRegister(Register &Reg,
958                                             RegisterGroup Group) {
959   Reg.StartLoc = Parser.getTok().getLoc();
960   // We have an integer token
961   const MCExpr *Register;
962   if (Parser.parseExpression(Register))
963     return true;
964 
965   const auto *CE = dyn_cast<MCConstantExpr>(Register);
966   if (!CE)
967     return true;
968 
969   int64_t MaxRegNum = (Group == RegV) ? 31 : 15;
970   int64_t Value = CE->getValue();
971   if (Value < 0 || Value > MaxRegNum) {
972     Error(Parser.getTok().getLoc(), "invalid register");
973     return true;
974   }
975 
976   // Assign the Register Number
977   Reg.Num = (unsigned)Value;
978   Reg.Group = Group;
979   Reg.EndLoc = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
980 
981   // At this point, successfully parsed an integer register.
982   return false;
983 }
984 
985 // Parse a memory operand into Reg1, Reg2, Disp, and Length.
986 bool SystemZAsmParser::parseAddress(bool &HaveReg1, Register &Reg1,
987                                     bool &HaveReg2, Register &Reg2,
988                                     const MCExpr *&Disp, const MCExpr *&Length,
989                                     bool HasLength, bool HasVectorIndex) {
990   // Parse the displacement, which must always be present.
991   if (getParser().parseExpression(Disp))
992     return true;
993 
994   // Parse the optional base and index.
995   HaveReg1 = false;
996   HaveReg2 = false;
997   Length = nullptr;
998 
999   // If we have a scenario as below:
1000   //   vgef %v0, 0(0), 0
1001   // This is an example of a "BDVMem" instruction type.
1002   //
1003   // So when we parse this as an integer register, the register group
1004   // needs to be tied to "RegV". Usually when the prefix is passed in
1005   // as %<prefix><reg-number> its easy to check which group it should belong to
1006   // However, if we're passing in just the integer there's no real way to
1007   // "check" what register group it should belong to.
1008   //
1009   // When the user passes in the register as an integer, the user assumes that
1010   // the compiler is responsible for substituting it as the right kind of
1011   // register. Whereas, when the user specifies a "prefix", the onus is on
1012   // the user to make sure they pass in the right kind of register.
1013   //
1014   // The restriction only applies to the first Register (i.e. Reg1). Reg2 is
1015   // always a general register. Reg1 should be of group RegV if "HasVectorIndex"
1016   // (i.e. insn is of type BDVMem) is true.
1017   RegisterGroup RegGroup = HasVectorIndex ? RegV : RegGR;
1018 
1019   if (getLexer().is(AsmToken::LParen)) {
1020     Parser.Lex();
1021 
1022     if (getLexer().is(AsmToken::Percent)) {
1023       // Parse the first register.
1024       HaveReg1 = true;
1025       if (parseRegister(Reg1))
1026         return true;
1027     }
1028     // So if we have an integer as the first token in ([tok1], ..), it could:
1029     // 1. Refer to a "Register" (i.e X,R,V fields in BD[X|R|V]Mem type of
1030     // instructions)
1031     // 2. Refer to a "Length" field (i.e L field in BDLMem type of instructions)
1032     else if (getLexer().is(AsmToken::Integer)) {
1033       if (HasLength) {
1034         // Instruction has a "Length" field, safe to parse the first token as
1035         // the "Length" field
1036         if (getParser().parseExpression(Length))
1037           return true;
1038       } else {
1039         // Otherwise, if the instruction has no "Length" field, parse the
1040         // token as a "Register". We don't have to worry about whether the
1041         // instruction is invalid here, because the caller will take care of
1042         // error reporting.
1043         HaveReg1 = true;
1044         if (parseIntegerRegister(Reg1, RegGroup))
1045           return true;
1046       }
1047     } else {
1048       // If its not an integer or a percent token, then if the instruction
1049       // is reported to have a "Length" then, parse it as "Length".
1050       if (HasLength) {
1051         if (getParser().parseExpression(Length))
1052           return true;
1053       }
1054     }
1055 
1056     // Check whether there's a second register.
1057     if (getLexer().is(AsmToken::Comma)) {
1058       Parser.Lex();
1059       HaveReg2 = true;
1060 
1061       if (getLexer().is(AsmToken::Integer)) {
1062         if (parseIntegerRegister(Reg2, RegGR))
1063           return true;
1064       } else {
1065         if (parseRegister(Reg2))
1066           return true;
1067       }
1068     }
1069 
1070     // Consume the closing bracket.
1071     if (getLexer().isNot(AsmToken::RParen))
1072       return Error(Parser.getTok().getLoc(), "unexpected token in address");
1073     Parser.Lex();
1074   }
1075   return false;
1076 }
1077 
1078 // Verify that Reg is a valid address register (base or index).
1079 bool
1080 SystemZAsmParser::parseAddressRegister(Register &Reg) {
1081   if (Reg.Group == RegV) {
1082     Error(Reg.StartLoc, "invalid use of vector addressing");
1083     return true;
1084   } else if (Reg.Group != RegGR) {
1085     Error(Reg.StartLoc, "invalid address register");
1086     return true;
1087   }
1088   return false;
1089 }
1090 
1091 // Parse a memory operand and add it to Operands.  The other arguments
1092 // are as above.
1093 OperandMatchResultTy
1094 SystemZAsmParser::parseAddress(OperandVector &Operands, MemoryKind MemKind,
1095                                RegisterKind RegKind) {
1096   SMLoc StartLoc = Parser.getTok().getLoc();
1097   unsigned Base = 0, Index = 0, LengthReg = 0;
1098   Register Reg1, Reg2;
1099   bool HaveReg1, HaveReg2;
1100   const MCExpr *Disp;
1101   const MCExpr *Length;
1102 
1103   bool HasLength = (MemKind == BDLMem) ? true : false;
1104   bool HasVectorIndex = (MemKind == BDVMem) ? true : false;
1105   if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length, HasLength,
1106                    HasVectorIndex))
1107     return MatchOperand_ParseFail;
1108 
1109   const unsigned *Regs;
1110   switch (RegKind) {
1111   case GR32Reg: Regs = SystemZMC::GR32Regs; break;
1112   case GR64Reg: Regs = SystemZMC::GR64Regs; break;
1113   default: llvm_unreachable("invalid RegKind");
1114   }
1115 
1116   switch (MemKind) {
1117   case BDMem:
1118     // If we have Reg1, it must be an address register.
1119     if (HaveReg1) {
1120       if (parseAddressRegister(Reg1))
1121         return MatchOperand_ParseFail;
1122       Base = Regs[Reg1.Num];
1123     }
1124     // There must be no Reg2.
1125     if (HaveReg2) {
1126       Error(StartLoc, "invalid use of indexed addressing");
1127       return MatchOperand_ParseFail;
1128     }
1129     break;
1130   case BDXMem:
1131     // If we have Reg1, it must be an address register.
1132     if (HaveReg1) {
1133       if (parseAddressRegister(Reg1))
1134         return MatchOperand_ParseFail;
1135       // If the are two registers, the first one is the index and the
1136       // second is the base.
1137       if (HaveReg2)
1138         Index = Regs[Reg1.Num];
1139       else
1140         Base = Regs[Reg1.Num];
1141     }
1142     // If we have Reg2, it must be an address register.
1143     if (HaveReg2) {
1144       if (parseAddressRegister(Reg2))
1145         return MatchOperand_ParseFail;
1146       Base = Regs[Reg2.Num];
1147     }
1148     break;
1149   case BDLMem:
1150     // If we have Reg2, it must be an address register.
1151     if (HaveReg2) {
1152       if (parseAddressRegister(Reg2))
1153         return MatchOperand_ParseFail;
1154       Base = Regs[Reg2.Num];
1155     }
1156     // We cannot support base+index addressing.
1157     if (HaveReg1 && HaveReg2) {
1158       Error(StartLoc, "invalid use of indexed addressing");
1159       return MatchOperand_ParseFail;
1160     }
1161     // We must have a length.
1162     if (!Length) {
1163       Error(StartLoc, "missing length in address");
1164       return MatchOperand_ParseFail;
1165     }
1166     break;
1167   case BDRMem:
1168     // We must have Reg1, and it must be a GPR.
1169     if (!HaveReg1 || Reg1.Group != RegGR) {
1170       Error(StartLoc, "invalid operand for instruction");
1171       return MatchOperand_ParseFail;
1172     }
1173     LengthReg = SystemZMC::GR64Regs[Reg1.Num];
1174     // If we have Reg2, it must be an address register.
1175     if (HaveReg2) {
1176       if (parseAddressRegister(Reg2))
1177         return MatchOperand_ParseFail;
1178       Base = Regs[Reg2.Num];
1179     }
1180     break;
1181   case BDVMem:
1182     // We must have Reg1, and it must be a vector register.
1183     if (!HaveReg1 || Reg1.Group != RegV) {
1184       Error(StartLoc, "vector index required in address");
1185       return MatchOperand_ParseFail;
1186     }
1187     Index = SystemZMC::VR128Regs[Reg1.Num];
1188     // If we have Reg2, it must be an address register.
1189     if (HaveReg2) {
1190       if (parseAddressRegister(Reg2))
1191         return MatchOperand_ParseFail;
1192       Base = Regs[Reg2.Num];
1193     }
1194     break;
1195   }
1196 
1197   SMLoc EndLoc =
1198       SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1199   Operands.push_back(SystemZOperand::createMem(MemKind, RegKind, Base, Disp,
1200                                                Index, Length, LengthReg,
1201                                                StartLoc, EndLoc));
1202   return MatchOperand_Success;
1203 }
1204 
1205 bool SystemZAsmParser::ParseDirective(AsmToken DirectiveID) {
1206   StringRef IDVal = DirectiveID.getIdentifier();
1207 
1208   if (IDVal == ".insn")
1209     return ParseDirectiveInsn(DirectiveID.getLoc());
1210 
1211   return true;
1212 }
1213 
1214 /// ParseDirectiveInsn
1215 /// ::= .insn [ format, encoding, (operands (, operands)*) ]
1216 bool SystemZAsmParser::ParseDirectiveInsn(SMLoc L) {
1217   MCAsmParser &Parser = getParser();
1218 
1219   // Expect instruction format as identifier.
1220   StringRef Format;
1221   SMLoc ErrorLoc = Parser.getTok().getLoc();
1222   if (Parser.parseIdentifier(Format))
1223     return Error(ErrorLoc, "expected instruction format");
1224 
1225   SmallVector<std::unique_ptr<MCParsedAsmOperand>, 8> Operands;
1226 
1227   // Find entry for this format in InsnMatchTable.
1228   auto EntryRange =
1229     std::equal_range(std::begin(InsnMatchTable), std::end(InsnMatchTable),
1230                      Format, CompareInsn());
1231 
1232   // If first == second, couldn't find a match in the table.
1233   if (EntryRange.first == EntryRange.second)
1234     return Error(ErrorLoc, "unrecognized format");
1235 
1236   struct InsnMatchEntry *Entry = EntryRange.first;
1237 
1238   // Format should match from equal_range.
1239   assert(Entry->Format == Format);
1240 
1241   // Parse the following operands using the table's information.
1242   for (int i = 0; i < Entry->NumOperands; i++) {
1243     MatchClassKind Kind = Entry->OperandKinds[i];
1244 
1245     SMLoc StartLoc = Parser.getTok().getLoc();
1246 
1247     // Always expect commas as separators for operands.
1248     if (getLexer().isNot(AsmToken::Comma))
1249       return Error(StartLoc, "unexpected token in directive");
1250     Lex();
1251 
1252     // Parse operands.
1253     OperandMatchResultTy ResTy;
1254     if (Kind == MCK_AnyReg)
1255       ResTy = parseAnyReg(Operands);
1256     else if (Kind == MCK_VR128)
1257       ResTy = parseVR128(Operands);
1258     else if (Kind == MCK_BDXAddr64Disp12 || Kind == MCK_BDXAddr64Disp20)
1259       ResTy = parseBDXAddr64(Operands);
1260     else if (Kind == MCK_BDAddr64Disp12 || Kind == MCK_BDAddr64Disp20)
1261       ResTy = parseBDAddr64(Operands);
1262     else if (Kind == MCK_BDVAddr64Disp12)
1263       ResTy = parseBDVAddr64(Operands);
1264     else if (Kind == MCK_PCRel32)
1265       ResTy = parsePCRel32(Operands);
1266     else if (Kind == MCK_PCRel16)
1267       ResTy = parsePCRel16(Operands);
1268     else {
1269       // Only remaining operand kind is an immediate.
1270       const MCExpr *Expr;
1271       SMLoc StartLoc = Parser.getTok().getLoc();
1272 
1273       // Expect immediate expression.
1274       if (Parser.parseExpression(Expr))
1275         return Error(StartLoc, "unexpected token in directive");
1276 
1277       SMLoc EndLoc =
1278         SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1279 
1280       Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1281       ResTy = MatchOperand_Success;
1282     }
1283 
1284     if (ResTy != MatchOperand_Success)
1285       return true;
1286   }
1287 
1288   // Build the instruction with the parsed operands.
1289   MCInst Inst = MCInstBuilder(Entry->Opcode);
1290 
1291   for (size_t i = 0; i < Operands.size(); i++) {
1292     MCParsedAsmOperand &Operand = *Operands[i];
1293     MatchClassKind Kind = Entry->OperandKinds[i];
1294 
1295     // Verify operand.
1296     unsigned Res = validateOperandClass(Operand, Kind);
1297     if (Res != Match_Success)
1298       return Error(Operand.getStartLoc(), "unexpected operand type");
1299 
1300     // Add operands to instruction.
1301     SystemZOperand &ZOperand = static_cast<SystemZOperand &>(Operand);
1302     if (ZOperand.isReg())
1303       ZOperand.addRegOperands(Inst, 1);
1304     else if (ZOperand.isMem(BDMem))
1305       ZOperand.addBDAddrOperands(Inst, 2);
1306     else if (ZOperand.isMem(BDXMem))
1307       ZOperand.addBDXAddrOperands(Inst, 3);
1308     else if (ZOperand.isMem(BDVMem))
1309       ZOperand.addBDVAddrOperands(Inst, 3);
1310     else if (ZOperand.isImm())
1311       ZOperand.addImmOperands(Inst, 1);
1312     else
1313       llvm_unreachable("unexpected operand type");
1314   }
1315 
1316   // Emit as a regular instruction.
1317   Parser.getStreamer().emitInstruction(Inst, getSTI());
1318 
1319   return false;
1320 }
1321 
1322 bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1323                                      SMLoc &EndLoc, bool RestoreOnFailure) {
1324   Register Reg;
1325   if (parseRegister(Reg, RestoreOnFailure))
1326     return true;
1327   if (Reg.Group == RegGR)
1328     RegNo = SystemZMC::GR64Regs[Reg.Num];
1329   else if (Reg.Group == RegFP)
1330     RegNo = SystemZMC::FP64Regs[Reg.Num];
1331   else if (Reg.Group == RegV)
1332     RegNo = SystemZMC::VR128Regs[Reg.Num];
1333   else if (Reg.Group == RegAR)
1334     RegNo = SystemZMC::AR32Regs[Reg.Num];
1335   else if (Reg.Group == RegCR)
1336     RegNo = SystemZMC::CR64Regs[Reg.Num];
1337   StartLoc = Reg.StartLoc;
1338   EndLoc = Reg.EndLoc;
1339   return false;
1340 }
1341 
1342 bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1343                                      SMLoc &EndLoc) {
1344   return ParseRegister(RegNo, StartLoc, EndLoc, /*RestoreOnFailure=*/false);
1345 }
1346 
1347 OperandMatchResultTy SystemZAsmParser::tryParseRegister(unsigned &RegNo,
1348                                                         SMLoc &StartLoc,
1349                                                         SMLoc &EndLoc) {
1350   bool Result =
1351       ParseRegister(RegNo, StartLoc, EndLoc, /*RestoreOnFailure=*/true);
1352   bool PendingErrors = getParser().hasPendingError();
1353   getParser().clearPendingErrors();
1354   if (PendingErrors)
1355     return MatchOperand_ParseFail;
1356   if (Result)
1357     return MatchOperand_NoMatch;
1358   return MatchOperand_Success;
1359 }
1360 
1361 bool SystemZAsmParser::ParseInstruction(ParseInstructionInfo &Info,
1362                                         StringRef Name, SMLoc NameLoc,
1363                                         OperandVector &Operands) {
1364 
1365   // Apply mnemonic aliases first, before doing anything else, in
1366   // case the target uses it.
1367   applyMnemonicAliases(Name, getAvailableFeatures(), getMAIAssemblerDialect());
1368 
1369   Operands.push_back(SystemZOperand::createToken(Name, NameLoc));
1370 
1371   // Read the remaining operands.
1372   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1373     // Read the first operand.
1374     if (parseOperand(Operands, Name)) {
1375       return true;
1376     }
1377 
1378     // Read any subsequent operands.
1379     while (getLexer().is(AsmToken::Comma)) {
1380       Parser.Lex();
1381       if (parseOperand(Operands, Name)) {
1382         return true;
1383       }
1384     }
1385     if (getLexer().isNot(AsmToken::EndOfStatement)) {
1386       SMLoc Loc = getLexer().getLoc();
1387       return Error(Loc, "unexpected token in argument list");
1388     }
1389   }
1390 
1391   // Consume the EndOfStatement.
1392   Parser.Lex();
1393   return false;
1394 }
1395 
1396 bool SystemZAsmParser::parseOperand(OperandVector &Operands,
1397                                     StringRef Mnemonic) {
1398   // Check if the current operand has a custom associated parser, if so, try to
1399   // custom parse the operand, or fallback to the general approach.  Force all
1400   // features to be available during the operand check, or else we will fail to
1401   // find the custom parser, and then we will later get an InvalidOperand error
1402   // instead of a MissingFeature errror.
1403   FeatureBitset AvailableFeatures = getAvailableFeatures();
1404   FeatureBitset All;
1405   All.set();
1406   setAvailableFeatures(All);
1407   OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
1408   setAvailableFeatures(AvailableFeatures);
1409   if (ResTy == MatchOperand_Success)
1410     return false;
1411 
1412   // If there wasn't a custom match, try the generic matcher below. Otherwise,
1413   // there was a match, but an error occurred, in which case, just return that
1414   // the operand parsing failed.
1415   if (ResTy == MatchOperand_ParseFail)
1416     return true;
1417 
1418   // Check for a register.  All real register operands should have used
1419   // a context-dependent parse routine, which gives the required register
1420   // class.  The code is here to mop up other cases, like those where
1421   // the instruction isn't recognized.
1422   if (Parser.getTok().is(AsmToken::Percent)) {
1423     Register Reg;
1424     if (parseRegister(Reg))
1425       return true;
1426     Operands.push_back(SystemZOperand::createInvalid(Reg.StartLoc, Reg.EndLoc));
1427     return false;
1428   }
1429 
1430   // The only other type of operand is an immediate or address.  As above,
1431   // real address operands should have used a context-dependent parse routine,
1432   // so we treat any plain expression as an immediate.
1433   SMLoc StartLoc = Parser.getTok().getLoc();
1434   Register Reg1, Reg2;
1435   bool HaveReg1, HaveReg2;
1436   const MCExpr *Expr;
1437   const MCExpr *Length;
1438   if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Expr, Length,
1439                    /*HasLength*/ true, /*HasVectorIndex*/ true))
1440     return true;
1441   // If the register combination is not valid for any instruction, reject it.
1442   // Otherwise, fall back to reporting an unrecognized instruction.
1443   if (HaveReg1 && Reg1.Group != RegGR && Reg1.Group != RegV
1444       && parseAddressRegister(Reg1))
1445     return true;
1446   if (HaveReg2 && parseAddressRegister(Reg2))
1447     return true;
1448 
1449   SMLoc EndLoc =
1450     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1451   if (HaveReg1 || HaveReg2 || Length)
1452     Operands.push_back(SystemZOperand::createInvalid(StartLoc, EndLoc));
1453   else
1454     Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1455   return false;
1456 }
1457 
1458 static std::string SystemZMnemonicSpellCheck(StringRef S,
1459                                              const FeatureBitset &FBS,
1460                                              unsigned VariantID = 0);
1461 
1462 bool SystemZAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1463                                                OperandVector &Operands,
1464                                                MCStreamer &Out,
1465                                                uint64_t &ErrorInfo,
1466                                                bool MatchingInlineAsm) {
1467   MCInst Inst;
1468   unsigned MatchResult;
1469 
1470   unsigned Dialect = getMAIAssemblerDialect();
1471 
1472   FeatureBitset MissingFeatures;
1473   MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo, MissingFeatures,
1474                                      MatchingInlineAsm, Dialect);
1475   switch (MatchResult) {
1476   case Match_Success:
1477     Inst.setLoc(IDLoc);
1478     Out.emitInstruction(Inst, getSTI());
1479     return false;
1480 
1481   case Match_MissingFeature: {
1482     assert(MissingFeatures.any() && "Unknown missing feature!");
1483     // Special case the error message for the very common case where only
1484     // a single subtarget feature is missing
1485     std::string Msg = "instruction requires:";
1486     for (unsigned I = 0, E = MissingFeatures.size(); I != E; ++I) {
1487       if (MissingFeatures[I]) {
1488         Msg += " ";
1489         Msg += getSubtargetFeatureName(I);
1490       }
1491     }
1492     return Error(IDLoc, Msg);
1493   }
1494 
1495   case Match_InvalidOperand: {
1496     SMLoc ErrorLoc = IDLoc;
1497     if (ErrorInfo != ~0ULL) {
1498       if (ErrorInfo >= Operands.size())
1499         return Error(IDLoc, "too few operands for instruction");
1500 
1501       ErrorLoc = ((SystemZOperand &)*Operands[ErrorInfo]).getStartLoc();
1502       if (ErrorLoc == SMLoc())
1503         ErrorLoc = IDLoc;
1504     }
1505     return Error(ErrorLoc, "invalid operand for instruction");
1506   }
1507 
1508   case Match_MnemonicFail: {
1509     FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits());
1510     std::string Suggestion = SystemZMnemonicSpellCheck(
1511         ((SystemZOperand &)*Operands[0]).getToken(), FBS, Dialect);
1512     return Error(IDLoc, "invalid instruction" + Suggestion,
1513                  ((SystemZOperand &)*Operands[0]).getLocRange());
1514   }
1515   }
1516 
1517   llvm_unreachable("Unexpected match type");
1518 }
1519 
1520 OperandMatchResultTy
1521 SystemZAsmParser::parsePCRel(OperandVector &Operands, int64_t MinVal,
1522                              int64_t MaxVal, bool AllowTLS) {
1523   MCContext &Ctx = getContext();
1524   MCStreamer &Out = getStreamer();
1525   const MCExpr *Expr;
1526   SMLoc StartLoc = Parser.getTok().getLoc();
1527   if (getParser().parseExpression(Expr))
1528     return MatchOperand_NoMatch;
1529 
1530   auto isOutOfRangeConstant = [&](const MCExpr *E) -> bool {
1531     if (auto *CE = dyn_cast<MCConstantExpr>(E)) {
1532       int64_t Value = CE->getValue();
1533       if ((Value & 1) || Value < MinVal || Value > MaxVal)
1534         return true;
1535     }
1536     return false;
1537   };
1538 
1539   // For consistency with the GNU assembler, treat immediates as offsets
1540   // from ".".
1541   if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
1542     if (isOutOfRangeConstant(CE)) {
1543       Error(StartLoc, "offset out of range");
1544       return MatchOperand_ParseFail;
1545     }
1546     int64_t Value = CE->getValue();
1547     MCSymbol *Sym = Ctx.createTempSymbol();
1548     Out.emitLabel(Sym);
1549     const MCExpr *Base = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None,
1550                                                  Ctx);
1551     Expr = Value == 0 ? Base : MCBinaryExpr::createAdd(Base, Expr, Ctx);
1552   }
1553 
1554   // For consistency with the GNU assembler, conservatively assume that a
1555   // constant offset must by itself be within the given size range.
1556   if (const auto *BE = dyn_cast<MCBinaryExpr>(Expr))
1557     if (isOutOfRangeConstant(BE->getLHS()) ||
1558         isOutOfRangeConstant(BE->getRHS())) {
1559       Error(StartLoc, "offset out of range");
1560       return MatchOperand_ParseFail;
1561     }
1562 
1563   // Optionally match :tls_gdcall: or :tls_ldcall: followed by a TLS symbol.
1564   const MCExpr *Sym = nullptr;
1565   if (AllowTLS && getLexer().is(AsmToken::Colon)) {
1566     Parser.Lex();
1567 
1568     if (Parser.getTok().isNot(AsmToken::Identifier)) {
1569       Error(Parser.getTok().getLoc(), "unexpected token");
1570       return MatchOperand_ParseFail;
1571     }
1572 
1573     MCSymbolRefExpr::VariantKind Kind = MCSymbolRefExpr::VK_None;
1574     StringRef Name = Parser.getTok().getString();
1575     if (Name == "tls_gdcall")
1576       Kind = MCSymbolRefExpr::VK_TLSGD;
1577     else if (Name == "tls_ldcall")
1578       Kind = MCSymbolRefExpr::VK_TLSLDM;
1579     else {
1580       Error(Parser.getTok().getLoc(), "unknown TLS tag");
1581       return MatchOperand_ParseFail;
1582     }
1583     Parser.Lex();
1584 
1585     if (Parser.getTok().isNot(AsmToken::Colon)) {
1586       Error(Parser.getTok().getLoc(), "unexpected token");
1587       return MatchOperand_ParseFail;
1588     }
1589     Parser.Lex();
1590 
1591     if (Parser.getTok().isNot(AsmToken::Identifier)) {
1592       Error(Parser.getTok().getLoc(), "unexpected token");
1593       return MatchOperand_ParseFail;
1594     }
1595 
1596     StringRef Identifier = Parser.getTok().getString();
1597     Sym = MCSymbolRefExpr::create(Ctx.getOrCreateSymbol(Identifier),
1598                                   Kind, Ctx);
1599     Parser.Lex();
1600   }
1601 
1602   SMLoc EndLoc =
1603     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1604 
1605   if (AllowTLS)
1606     Operands.push_back(SystemZOperand::createImmTLS(Expr, Sym,
1607                                                     StartLoc, EndLoc));
1608   else
1609     Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1610 
1611   return MatchOperand_Success;
1612 }
1613 
1614 bool SystemZAsmParser::isLabel(AsmToken &Token) {
1615   if (isParsingATT())
1616     return true;
1617 
1618   // HLASM labels are ordinary symbols.
1619   // An HLASM label always starts at column 1.
1620   // An ordinary symbol syntax is laid out as follows:
1621   // Rules:
1622   // 1. Has to start with an "alphabetic character". Can be followed by up to
1623   //    62 alphanumeric characters. An "alphabetic character", in this scenario,
1624   //    is a letter from 'A' through 'Z', or from 'a' through 'z',
1625   //    or '$', '_', '#', or '@'
1626   // 2. Labels are case-insensitive. E.g. "lab123", "LAB123", "lAb123", etc.
1627   //    are all treated as the same symbol. However, the processing for the case
1628   //    folding will not be done in this function.
1629   StringRef RawLabel = Token.getString();
1630   SMLoc Loc = Token.getLoc();
1631 
1632   // An HLASM label cannot be empty.
1633   if (!RawLabel.size())
1634     return !Error(Loc, "HLASM Label cannot be empty");
1635 
1636   // An HLASM label cannot exceed greater than 63 characters.
1637   if (RawLabel.size() > 63)
1638     return !Error(Loc, "Maximum length for HLASM Label is 63 characters");
1639 
1640   // A label must start with an "alphabetic character".
1641   if (!isHLASMAlpha(RawLabel[0]))
1642     return !Error(Loc, "HLASM Label has to start with an alphabetic "
1643                        "character or the underscore character");
1644 
1645   // Now, we've established that the length is valid
1646   // and the first character is alphabetic.
1647   // Check whether remaining string is alphanumeric.
1648   for (unsigned I = 1; I < RawLabel.size(); ++I)
1649     if (!isHLASMAlnum(RawLabel[I]))
1650       return !Error(Loc, "HLASM Label has to be alphanumeric");
1651 
1652   return true;
1653 }
1654 
1655 // Force static initialization.
1656 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSystemZAsmParser() {
1657   RegisterMCAsmParser<SystemZAsmParser> X(getTheSystemZTarget());
1658 }
1659