xref: /llvm-project/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp (revision 7a46d34a1953625f03b71494c0f33fe00316e4ba) 
1 //===-- SystemZAsmParser.cpp - Parse SystemZ assembly instructions --------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "MCTargetDesc/SystemZInstPrinter.h"
10 #include "MCTargetDesc/SystemZMCAsmInfo.h"
11 #include "MCTargetDesc/SystemZMCTargetDesc.h"
12 #include "TargetInfo/SystemZTargetInfo.h"
13 #include "llvm/ADT/STLExtras.h"
14 #include "llvm/ADT/SmallVector.h"
15 #include "llvm/ADT/StringRef.h"
16 #include "llvm/MC/MCAsmInfo.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstBuilder.h"
21 #include "llvm/MC/MCParser/MCAsmLexer.h"
22 #include "llvm/MC/MCParser/MCAsmParser.h"
23 #include "llvm/MC/MCParser/MCAsmParserExtension.h"
24 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
25 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
26 #include "llvm/MC/MCStreamer.h"
27 #include "llvm/MC/MCSubtargetInfo.h"
28 #include "llvm/Support/Casting.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/SMLoc.h"
31 #include "llvm/Support/TargetRegistry.h"
32 #include <algorithm>
33 #include <cassert>
34 #include <cstddef>
35 #include <cstdint>
36 #include <iterator>
37 #include <memory>
38 #include <string>
39 
40 using namespace llvm;
41 
42 // Return true if Expr is in the range [MinValue, MaxValue].
43 static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue) {
44   if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
45     int64_t Value = CE->getValue();
46     return Value >= MinValue && Value <= MaxValue;
47   }
48   return false;
49 }
50 
51 namespace {
52 
53 enum RegisterKind {
54   GR32Reg,
55   GRH32Reg,
56   GR64Reg,
57   GR128Reg,
58   FP32Reg,
59   FP64Reg,
60   FP128Reg,
61   VR32Reg,
62   VR64Reg,
63   VR128Reg,
64   AR32Reg,
65   CR64Reg,
66 };
67 
68 enum MemoryKind {
69   BDMem,
70   BDXMem,
71   BDLMem,
72   BDRMem,
73   BDVMem
74 };
75 
76 class SystemZOperand : public MCParsedAsmOperand {
77 private:
78   enum OperandKind {
79     KindInvalid,
80     KindToken,
81     KindReg,
82     KindImm,
83     KindImmTLS,
84     KindMem
85   };
86 
87   OperandKind Kind;
88   SMLoc StartLoc, EndLoc;
89 
90   // A string of length Length, starting at Data.
91   struct TokenOp {
92     const char *Data;
93     unsigned Length;
94   };
95 
96   // LLVM register Num, which has kind Kind.  In some ways it might be
97   // easier for this class to have a register bank (general, floating-point
98   // or access) and a raw register number (0-15).  This would postpone the
99   // interpretation of the operand to the add*() methods and avoid the need
100   // for context-dependent parsing.  However, we do things the current way
101   // because of the virtual getReg() method, which needs to distinguish
102   // between (say) %r0 used as a single register and %r0 used as a pair.
103   // Context-dependent parsing can also give us slightly better error
104   // messages when invalid pairs like %r1 are used.
105   struct RegOp {
106     RegisterKind Kind;
107     unsigned Num;
108   };
109 
110   // Base + Disp + Index, where Base and Index are LLVM registers or 0.
111   // MemKind says what type of memory this is and RegKind says what type
112   // the base register has (GR32Reg or GR64Reg).  Length is the operand
113   // length for D(L,B)-style operands, otherwise it is null.
114   struct MemOp {
115     unsigned Base : 12;
116     unsigned Index : 12;
117     unsigned MemKind : 4;
118     unsigned RegKind : 4;
119     const MCExpr *Disp;
120     union {
121       const MCExpr *Imm;
122       unsigned Reg;
123     } Length;
124   };
125 
126   // Imm is an immediate operand, and Sym is an optional TLS symbol
127   // for use with a __tls_get_offset marker relocation.
128   struct ImmTLSOp {
129     const MCExpr *Imm;
130     const MCExpr *Sym;
131   };
132 
133   union {
134     TokenOp Token;
135     RegOp Reg;
136     const MCExpr *Imm;
137     ImmTLSOp ImmTLS;
138     MemOp Mem;
139   };
140 
141   void addExpr(MCInst &Inst, const MCExpr *Expr) const {
142     // Add as immediates when possible.  Null MCExpr = 0.
143     if (!Expr)
144       Inst.addOperand(MCOperand::createImm(0));
145     else if (auto *CE = dyn_cast<MCConstantExpr>(Expr))
146       Inst.addOperand(MCOperand::createImm(CE->getValue()));
147     else
148       Inst.addOperand(MCOperand::createExpr(Expr));
149   }
150 
151 public:
152   SystemZOperand(OperandKind kind, SMLoc startLoc, SMLoc endLoc)
153       : Kind(kind), StartLoc(startLoc), EndLoc(endLoc) {}
154 
155   // Create particular kinds of operand.
156   static std::unique_ptr<SystemZOperand> createInvalid(SMLoc StartLoc,
157                                                        SMLoc EndLoc) {
158     return std::make_unique<SystemZOperand>(KindInvalid, StartLoc, EndLoc);
159   }
160 
161   static std::unique_ptr<SystemZOperand> createToken(StringRef Str, SMLoc Loc) {
162     auto Op = std::make_unique<SystemZOperand>(KindToken, Loc, Loc);
163     Op->Token.Data = Str.data();
164     Op->Token.Length = Str.size();
165     return Op;
166   }
167 
168   static std::unique_ptr<SystemZOperand>
169   createReg(RegisterKind Kind, unsigned Num, SMLoc StartLoc, SMLoc EndLoc) {
170     auto Op = std::make_unique<SystemZOperand>(KindReg, StartLoc, EndLoc);
171     Op->Reg.Kind = Kind;
172     Op->Reg.Num = Num;
173     return Op;
174   }
175 
176   static std::unique_ptr<SystemZOperand>
177   createImm(const MCExpr *Expr, SMLoc StartLoc, SMLoc EndLoc) {
178     auto Op = std::make_unique<SystemZOperand>(KindImm, StartLoc, EndLoc);
179     Op->Imm = Expr;
180     return Op;
181   }
182 
183   static std::unique_ptr<SystemZOperand>
184   createMem(MemoryKind MemKind, RegisterKind RegKind, unsigned Base,
185             const MCExpr *Disp, unsigned Index, const MCExpr *LengthImm,
186             unsigned LengthReg, SMLoc StartLoc, SMLoc EndLoc) {
187     auto Op = std::make_unique<SystemZOperand>(KindMem, StartLoc, EndLoc);
188     Op->Mem.MemKind = MemKind;
189     Op->Mem.RegKind = RegKind;
190     Op->Mem.Base = Base;
191     Op->Mem.Index = Index;
192     Op->Mem.Disp = Disp;
193     if (MemKind == BDLMem)
194       Op->Mem.Length.Imm = LengthImm;
195     if (MemKind == BDRMem)
196       Op->Mem.Length.Reg = LengthReg;
197     return Op;
198   }
199 
200   static std::unique_ptr<SystemZOperand>
201   createImmTLS(const MCExpr *Imm, const MCExpr *Sym,
202                SMLoc StartLoc, SMLoc EndLoc) {
203     auto Op = std::make_unique<SystemZOperand>(KindImmTLS, StartLoc, EndLoc);
204     Op->ImmTLS.Imm = Imm;
205     Op->ImmTLS.Sym = Sym;
206     return Op;
207   }
208 
209   // Token operands
210   bool isToken() const override {
211     return Kind == KindToken;
212   }
213   StringRef getToken() const {
214     assert(Kind == KindToken && "Not a token");
215     return StringRef(Token.Data, Token.Length);
216   }
217 
218   // Register operands.
219   bool isReg() const override {
220     return Kind == KindReg;
221   }
222   bool isReg(RegisterKind RegKind) const {
223     return Kind == KindReg && Reg.Kind == RegKind;
224   }
225   unsigned getReg() const override {
226     assert(Kind == KindReg && "Not a register");
227     return Reg.Num;
228   }
229 
230   // Immediate operands.
231   bool isImm() const override {
232     return Kind == KindImm;
233   }
234   bool isImm(int64_t MinValue, int64_t MaxValue) const {
235     return Kind == KindImm && inRange(Imm, MinValue, MaxValue);
236   }
237   const MCExpr *getImm() const {
238     assert(Kind == KindImm && "Not an immediate");
239     return Imm;
240   }
241 
242   // Immediate operands with optional TLS symbol.
243   bool isImmTLS() const {
244     return Kind == KindImmTLS;
245   }
246 
247   const ImmTLSOp getImmTLS() const {
248     assert(Kind == KindImmTLS && "Not a TLS immediate");
249     return ImmTLS;
250   }
251 
252   // Memory operands.
253   bool isMem() const override {
254     return Kind == KindMem;
255   }
256   bool isMem(MemoryKind MemKind) const {
257     return (Kind == KindMem &&
258             (Mem.MemKind == MemKind ||
259              // A BDMem can be treated as a BDXMem in which the index
260              // register field is 0.
261              (Mem.MemKind == BDMem && MemKind == BDXMem)));
262   }
263   bool isMem(MemoryKind MemKind, RegisterKind RegKind) const {
264     return isMem(MemKind) && Mem.RegKind == RegKind;
265   }
266   bool isMemDisp12(MemoryKind MemKind, RegisterKind RegKind) const {
267     return isMem(MemKind, RegKind) && inRange(Mem.Disp, 0, 0xfff);
268   }
269   bool isMemDisp20(MemoryKind MemKind, RegisterKind RegKind) const {
270     return isMem(MemKind, RegKind) && inRange(Mem.Disp, -524288, 524287);
271   }
272   bool isMemDisp12Len4(RegisterKind RegKind) const {
273     return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length.Imm, 1, 0x10);
274   }
275   bool isMemDisp12Len8(RegisterKind RegKind) const {
276     return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length.Imm, 1, 0x100);
277   }
278 
279   const MemOp& getMem() const {
280     assert(Kind == KindMem && "Not a Mem operand");
281     return Mem;
282   }
283 
284   // Override MCParsedAsmOperand.
285   SMLoc getStartLoc() const override { return StartLoc; }
286   SMLoc getEndLoc() const override { return EndLoc; }
287   void print(raw_ostream &OS) const override;
288 
289   /// getLocRange - Get the range between the first and last token of this
290   /// operand.
291   SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
292 
293   // Used by the TableGen code to add particular types of operand
294   // to an instruction.
295   void addRegOperands(MCInst &Inst, unsigned N) const {
296     assert(N == 1 && "Invalid number of operands");
297     Inst.addOperand(MCOperand::createReg(getReg()));
298   }
299   void addImmOperands(MCInst &Inst, unsigned N) const {
300     assert(N == 1 && "Invalid number of operands");
301     addExpr(Inst, getImm());
302   }
303   void addBDAddrOperands(MCInst &Inst, unsigned N) const {
304     assert(N == 2 && "Invalid number of operands");
305     assert(isMem(BDMem) && "Invalid operand type");
306     Inst.addOperand(MCOperand::createReg(Mem.Base));
307     addExpr(Inst, Mem.Disp);
308   }
309   void addBDXAddrOperands(MCInst &Inst, unsigned N) const {
310     assert(N == 3 && "Invalid number of operands");
311     assert(isMem(BDXMem) && "Invalid operand type");
312     Inst.addOperand(MCOperand::createReg(Mem.Base));
313     addExpr(Inst, Mem.Disp);
314     Inst.addOperand(MCOperand::createReg(Mem.Index));
315   }
316   void addBDLAddrOperands(MCInst &Inst, unsigned N) const {
317     assert(N == 3 && "Invalid number of operands");
318     assert(isMem(BDLMem) && "Invalid operand type");
319     Inst.addOperand(MCOperand::createReg(Mem.Base));
320     addExpr(Inst, Mem.Disp);
321     addExpr(Inst, Mem.Length.Imm);
322   }
323   void addBDRAddrOperands(MCInst &Inst, unsigned N) const {
324     assert(N == 3 && "Invalid number of operands");
325     assert(isMem(BDRMem) && "Invalid operand type");
326     Inst.addOperand(MCOperand::createReg(Mem.Base));
327     addExpr(Inst, Mem.Disp);
328     Inst.addOperand(MCOperand::createReg(Mem.Length.Reg));
329   }
330   void addBDVAddrOperands(MCInst &Inst, unsigned N) const {
331     assert(N == 3 && "Invalid number of operands");
332     assert(isMem(BDVMem) && "Invalid operand type");
333     Inst.addOperand(MCOperand::createReg(Mem.Base));
334     addExpr(Inst, Mem.Disp);
335     Inst.addOperand(MCOperand::createReg(Mem.Index));
336   }
337   void addImmTLSOperands(MCInst &Inst, unsigned N) const {
338     assert(N == 2 && "Invalid number of operands");
339     assert(Kind == KindImmTLS && "Invalid operand type");
340     addExpr(Inst, ImmTLS.Imm);
341     if (ImmTLS.Sym)
342       addExpr(Inst, ImmTLS.Sym);
343   }
344 
345   // Used by the TableGen code to check for particular operand types.
346   bool isGR32() const { return isReg(GR32Reg); }
347   bool isGRH32() const { return isReg(GRH32Reg); }
348   bool isGRX32() const { return false; }
349   bool isGR64() const { return isReg(GR64Reg); }
350   bool isGR128() const { return isReg(GR128Reg); }
351   bool isADDR32() const { return isReg(GR32Reg); }
352   bool isADDR64() const { return isReg(GR64Reg); }
353   bool isADDR128() const { return false; }
354   bool isFP32() const { return isReg(FP32Reg); }
355   bool isFP64() const { return isReg(FP64Reg); }
356   bool isFP128() const { return isReg(FP128Reg); }
357   bool isVR32() const { return isReg(VR32Reg); }
358   bool isVR64() const { return isReg(VR64Reg); }
359   bool isVF128() const { return false; }
360   bool isVR128() const { return isReg(VR128Reg); }
361   bool isAR32() const { return isReg(AR32Reg); }
362   bool isCR64() const { return isReg(CR64Reg); }
363   bool isAnyReg() const { return (isReg() || isImm(0, 15)); }
364   bool isBDAddr32Disp12() const { return isMemDisp12(BDMem, GR32Reg); }
365   bool isBDAddr32Disp20() const { return isMemDisp20(BDMem, GR32Reg); }
366   bool isBDAddr64Disp12() const { return isMemDisp12(BDMem, GR64Reg); }
367   bool isBDAddr64Disp20() const { return isMemDisp20(BDMem, GR64Reg); }
368   bool isBDXAddr64Disp12() const { return isMemDisp12(BDXMem, GR64Reg); }
369   bool isBDXAddr64Disp20() const { return isMemDisp20(BDXMem, GR64Reg); }
370   bool isBDLAddr64Disp12Len4() const { return isMemDisp12Len4(GR64Reg); }
371   bool isBDLAddr64Disp12Len8() const { return isMemDisp12Len8(GR64Reg); }
372   bool isBDRAddr64Disp12() const { return isMemDisp12(BDRMem, GR64Reg); }
373   bool isBDVAddr64Disp12() const { return isMemDisp12(BDVMem, GR64Reg); }
374   bool isU1Imm() const { return isImm(0, 1); }
375   bool isU2Imm() const { return isImm(0, 3); }
376   bool isU3Imm() const { return isImm(0, 7); }
377   bool isU4Imm() const { return isImm(0, 15); }
378   bool isU6Imm() const { return isImm(0, 63); }
379   bool isU8Imm() const { return isImm(0, 255); }
380   bool isS8Imm() const { return isImm(-128, 127); }
381   bool isU12Imm() const { return isImm(0, 4095); }
382   bool isU16Imm() const { return isImm(0, 65535); }
383   bool isS16Imm() const { return isImm(-32768, 32767); }
384   bool isU32Imm() const { return isImm(0, (1LL << 32) - 1); }
385   bool isS32Imm() const { return isImm(-(1LL << 31), (1LL << 31) - 1); }
386   bool isU48Imm() const { return isImm(0, (1LL << 48) - 1); }
387 };
388 
389 class SystemZAsmParser : public MCTargetAsmParser {
390 #define GET_ASSEMBLER_HEADER
391 #include "SystemZGenAsmMatcher.inc"
392 
393 private:
394   MCAsmParser &Parser;
395   enum RegisterGroup {
396     RegGR,
397     RegFP,
398     RegV,
399     RegAR,
400     RegCR
401   };
402   struct Register {
403     RegisterGroup Group;
404     unsigned Num;
405     SMLoc StartLoc, EndLoc;
406   };
407 
408   bool parseRegister(Register &Reg, bool RestoreOnFailure = false);
409 
410   bool parseIntegerRegister(Register &Reg, RegisterGroup Group);
411 
412   OperandMatchResultTy parseRegister(OperandVector &Operands,
413                                      RegisterKind Kind);
414 
415   OperandMatchResultTy parseAnyRegister(OperandVector &Operands);
416 
417   bool parseAddress(bool &HaveReg1, Register &Reg1, bool &HaveReg2,
418                     Register &Reg2, const MCExpr *&Disp, const MCExpr *&Length,
419                     bool HasLength = false, bool HasVectorIndex = false);
420   bool parseAddressRegister(Register &Reg);
421 
422   bool ParseDirectiveInsn(SMLoc L);
423 
424   OperandMatchResultTy parseAddress(OperandVector &Operands,
425                                     MemoryKind MemKind,
426                                     RegisterKind RegKind);
427 
428   OperandMatchResultTy parsePCRel(OperandVector &Operands, int64_t MinVal,
429                                   int64_t MaxVal, bool AllowTLS);
430 
431   bool parseOperand(OperandVector &Operands, StringRef Mnemonic);
432 
433   // Both the hlasm and att variants still rely on the basic gnu asm
434   // format with respect to inputs, clobbers, outputs etc.
435   //
436   // However, calling the overriden getAssemblerDialect() method in
437   // AsmParser is problematic. It either returns the AssemblerDialect field
438   // in the MCAsmInfo instance if the AssemblerDialect field in AsmParser is
439   // unset, otherwise it returns the private AssemblerDialect field in
440   // AsmParser.
441   //
442   // The problematic part is because, we forcibly set the inline asm dialect
443   // in the AsmParser instance in AsmPrinterInlineAsm.cpp. Soo any query
444   // to the overriden getAssemblerDialect function in AsmParser.cpp, will
445   // not return the assembler dialect set in the respective MCAsmInfo instance.
446   //
447   // For this purpose, we explicitly query the SystemZMCAsmInfo instance
448   // here, to get the "correct" assembler dialect, and use it in various
449   // functions.
450   unsigned getMAIAssemblerDialect() {
451     return Parser.getContext().getAsmInfo()->getAssemblerDialect();
452   }
453 
454   // An alphabetic character in HLASM is a letter from 'A' through 'Z',
455   // or from 'a' through 'z', or '$', '_','#', or '@'.
456   inline bool isHLASMAlpha(char C) {
457     return isAlpha(C) || llvm::is_contained("_@#$", C);
458   }
459 
460   // A digit in HLASM is a number from 0 to 9.
461   inline bool isHLASMAlnum(char C) { return isHLASMAlpha(C) || isDigit(C); }
462 
463 public:
464   SystemZAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
465                    const MCInstrInfo &MII,
466                    const MCTargetOptions &Options)
467     : MCTargetAsmParser(Options, sti, MII), Parser(parser) {
468     MCAsmParserExtension::Initialize(Parser);
469 
470     // Alias the .word directive to .short.
471     parser.addAliasForDirective(".word", ".short");
472 
473     // Initialize the set of available features.
474     setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
475   }
476 
477   // Override MCTargetAsmParser.
478   bool ParseDirective(AsmToken DirectiveID) override;
479   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
480   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc,
481                      bool RestoreOnFailure);
482   OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc,
483                                         SMLoc &EndLoc) override;
484   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
485                         SMLoc NameLoc, OperandVector &Operands) override;
486   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
487                                OperandVector &Operands, MCStreamer &Out,
488                                uint64_t &ErrorInfo,
489                                bool MatchingInlineAsm) override;
490   bool isLabel(AsmToken &Token) override;
491 
492   // Used by the TableGen code to parse particular operand types.
493   OperandMatchResultTy parseGR32(OperandVector &Operands) {
494     return parseRegister(Operands, GR32Reg);
495   }
496   OperandMatchResultTy parseGRH32(OperandVector &Operands) {
497     return parseRegister(Operands, GRH32Reg);
498   }
499   OperandMatchResultTy parseGRX32(OperandVector &Operands) {
500     llvm_unreachable("GRX32 should only be used for pseudo instructions");
501   }
502   OperandMatchResultTy parseGR64(OperandVector &Operands) {
503     return parseRegister(Operands, GR64Reg);
504   }
505   OperandMatchResultTy parseGR128(OperandVector &Operands) {
506     return parseRegister(Operands, GR128Reg);
507   }
508   OperandMatchResultTy parseADDR32(OperandVector &Operands) {
509     // For the AsmParser, we will accept %r0 for ADDR32 as well.
510     return parseRegister(Operands, GR32Reg);
511   }
512   OperandMatchResultTy parseADDR64(OperandVector &Operands) {
513     // For the AsmParser, we will accept %r0 for ADDR64 as well.
514     return parseRegister(Operands, GR64Reg);
515   }
516   OperandMatchResultTy parseADDR128(OperandVector &Operands) {
517     llvm_unreachable("Shouldn't be used as an operand");
518   }
519   OperandMatchResultTy parseFP32(OperandVector &Operands) {
520     return parseRegister(Operands, FP32Reg);
521   }
522   OperandMatchResultTy parseFP64(OperandVector &Operands) {
523     return parseRegister(Operands, FP64Reg);
524   }
525   OperandMatchResultTy parseFP128(OperandVector &Operands) {
526     return parseRegister(Operands, FP128Reg);
527   }
528   OperandMatchResultTy parseVR32(OperandVector &Operands) {
529     return parseRegister(Operands, VR32Reg);
530   }
531   OperandMatchResultTy parseVR64(OperandVector &Operands) {
532     return parseRegister(Operands, VR64Reg);
533   }
534   OperandMatchResultTy parseVF128(OperandVector &Operands) {
535     llvm_unreachable("Shouldn't be used as an operand");
536   }
537   OperandMatchResultTy parseVR128(OperandVector &Operands) {
538     return parseRegister(Operands, VR128Reg);
539   }
540   OperandMatchResultTy parseAR32(OperandVector &Operands) {
541     return parseRegister(Operands, AR32Reg);
542   }
543   OperandMatchResultTy parseCR64(OperandVector &Operands) {
544     return parseRegister(Operands, CR64Reg);
545   }
546   OperandMatchResultTy parseAnyReg(OperandVector &Operands) {
547     return parseAnyRegister(Operands);
548   }
549   OperandMatchResultTy parseBDAddr32(OperandVector &Operands) {
550     return parseAddress(Operands, BDMem, GR32Reg);
551   }
552   OperandMatchResultTy parseBDAddr64(OperandVector &Operands) {
553     return parseAddress(Operands, BDMem, GR64Reg);
554   }
555   OperandMatchResultTy parseBDXAddr64(OperandVector &Operands) {
556     return parseAddress(Operands, BDXMem, GR64Reg);
557   }
558   OperandMatchResultTy parseBDLAddr64(OperandVector &Operands) {
559     return parseAddress(Operands, BDLMem, GR64Reg);
560   }
561   OperandMatchResultTy parseBDRAddr64(OperandVector &Operands) {
562     return parseAddress(Operands, BDRMem, GR64Reg);
563   }
564   OperandMatchResultTy parseBDVAddr64(OperandVector &Operands) {
565     return parseAddress(Operands, BDVMem, GR64Reg);
566   }
567   OperandMatchResultTy parsePCRel12(OperandVector &Operands) {
568     return parsePCRel(Operands, -(1LL << 12), (1LL << 12) - 1, false);
569   }
570   OperandMatchResultTy parsePCRel16(OperandVector &Operands) {
571     return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, false);
572   }
573   OperandMatchResultTy parsePCRel24(OperandVector &Operands) {
574     return parsePCRel(Operands, -(1LL << 24), (1LL << 24) - 1, false);
575   }
576   OperandMatchResultTy parsePCRel32(OperandVector &Operands) {
577     return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, false);
578   }
579   OperandMatchResultTy parsePCRelTLS16(OperandVector &Operands) {
580     return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, true);
581   }
582   OperandMatchResultTy parsePCRelTLS32(OperandVector &Operands) {
583     return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, true);
584   }
585 };
586 
587 } // end anonymous namespace
588 
589 #define GET_REGISTER_MATCHER
590 #define GET_SUBTARGET_FEATURE_NAME
591 #define GET_MATCHER_IMPLEMENTATION
592 #define GET_MNEMONIC_SPELL_CHECKER
593 #include "SystemZGenAsmMatcher.inc"
594 
595 // Used for the .insn directives; contains information needed to parse the
596 // operands in the directive.
597 struct InsnMatchEntry {
598   StringRef Format;
599   uint64_t Opcode;
600   int32_t NumOperands;
601   MatchClassKind OperandKinds[7];
602 };
603 
604 // For equal_range comparison.
605 struct CompareInsn {
606   bool operator() (const InsnMatchEntry &LHS, StringRef RHS) {
607     return LHS.Format < RHS;
608   }
609   bool operator() (StringRef LHS, const InsnMatchEntry &RHS) {
610     return LHS < RHS.Format;
611   }
612   bool operator() (const InsnMatchEntry &LHS, const InsnMatchEntry &RHS) {
613     return LHS.Format < RHS.Format;
614   }
615 };
616 
617 // Table initializing information for parsing the .insn directive.
618 static struct InsnMatchEntry InsnMatchTable[] = {
619   /* Format, Opcode, NumOperands, OperandKinds */
620   { "e", SystemZ::InsnE, 1,
621     { MCK_U16Imm } },
622   { "ri", SystemZ::InsnRI, 3,
623     { MCK_U32Imm, MCK_AnyReg, MCK_S16Imm } },
624   { "rie", SystemZ::InsnRIE, 4,
625     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
626   { "ril", SystemZ::InsnRIL, 3,
627     { MCK_U48Imm, MCK_AnyReg, MCK_PCRel32 } },
628   { "rilu", SystemZ::InsnRILU, 3,
629     { MCK_U48Imm, MCK_AnyReg, MCK_U32Imm } },
630   { "ris", SystemZ::InsnRIS, 5,
631     { MCK_U48Imm, MCK_AnyReg, MCK_S8Imm, MCK_U4Imm, MCK_BDAddr64Disp12 } },
632   { "rr", SystemZ::InsnRR, 3,
633     { MCK_U16Imm, MCK_AnyReg, MCK_AnyReg } },
634   { "rre", SystemZ::InsnRRE, 3,
635     { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg } },
636   { "rrf", SystemZ::InsnRRF, 5,
637     { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm } },
638   { "rrs", SystemZ::InsnRRS, 5,
639     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm, MCK_BDAddr64Disp12 } },
640   { "rs", SystemZ::InsnRS, 4,
641     { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
642   { "rse", SystemZ::InsnRSE, 4,
643     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
644   { "rsi", SystemZ::InsnRSI, 4,
645     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
646   { "rsy", SystemZ::InsnRSY, 4,
647     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp20 } },
648   { "rx", SystemZ::InsnRX, 3,
649     { MCK_U32Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
650   { "rxe", SystemZ::InsnRXE, 3,
651     { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
652   { "rxf", SystemZ::InsnRXF, 4,
653     { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
654   { "rxy", SystemZ::InsnRXY, 3,
655     { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp20 } },
656   { "s", SystemZ::InsnS, 2,
657     { MCK_U32Imm, MCK_BDAddr64Disp12 } },
658   { "si", SystemZ::InsnSI, 3,
659     { MCK_U32Imm, MCK_BDAddr64Disp12, MCK_S8Imm } },
660   { "sil", SystemZ::InsnSIL, 3,
661     { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_U16Imm } },
662   { "siy", SystemZ::InsnSIY, 3,
663     { MCK_U48Imm, MCK_BDAddr64Disp20, MCK_U8Imm } },
664   { "ss", SystemZ::InsnSS, 4,
665     { MCK_U48Imm, MCK_BDXAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } },
666   { "sse", SystemZ::InsnSSE, 3,
667     { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12 } },
668   { "ssf", SystemZ::InsnSSF, 4,
669     { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } },
670   { "vri", SystemZ::InsnVRI, 6,
671     { MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_U12Imm, MCK_U4Imm, MCK_U4Imm } },
672   { "vrr", SystemZ::InsnVRR, 7,
673     { MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_VR128, MCK_U4Imm, MCK_U4Imm,
674       MCK_U4Imm } },
675   { "vrs", SystemZ::InsnVRS, 5,
676     { MCK_U48Imm, MCK_AnyReg, MCK_VR128, MCK_BDAddr64Disp12, MCK_U4Imm } },
677   { "vrv", SystemZ::InsnVRV, 4,
678     { MCK_U48Imm, MCK_VR128, MCK_BDVAddr64Disp12, MCK_U4Imm } },
679   { "vrx", SystemZ::InsnVRX, 4,
680     { MCK_U48Imm, MCK_VR128, MCK_BDXAddr64Disp12, MCK_U4Imm } },
681   { "vsi", SystemZ::InsnVSI, 4,
682     { MCK_U48Imm, MCK_VR128, MCK_BDAddr64Disp12, MCK_U8Imm } }
683 };
684 
685 static void printMCExpr(const MCExpr *E, raw_ostream &OS) {
686   if (!E)
687     return;
688   if (auto *CE = dyn_cast<MCConstantExpr>(E))
689     OS << *CE;
690   else if (auto *UE = dyn_cast<MCUnaryExpr>(E))
691     OS << *UE;
692   else if (auto *BE = dyn_cast<MCBinaryExpr>(E))
693     OS << *BE;
694   else if (auto *SRE = dyn_cast<MCSymbolRefExpr>(E))
695     OS << *SRE;
696   else
697     OS << *E;
698 }
699 
700 void SystemZOperand::print(raw_ostream &OS) const {
701   switch (Kind) {
702   case KindToken:
703     OS << "Token:" << getToken();
704     break;
705   case KindReg:
706     OS << "Reg:" << SystemZInstPrinter::getRegisterName(getReg());
707     break;
708   case KindImm:
709     OS << "Imm:";
710     printMCExpr(getImm(), OS);
711     break;
712   case KindImmTLS:
713     OS << "ImmTLS:";
714     printMCExpr(getImmTLS().Imm, OS);
715     if (getImmTLS().Sym) {
716       OS << ", ";
717       printMCExpr(getImmTLS().Sym, OS);
718     }
719     break;
720   case KindMem: {
721     const MemOp &Op = getMem();
722     OS << "Mem:" << *cast<MCConstantExpr>(Op.Disp);
723     if (Op.Base) {
724       OS << "(";
725       if (Op.MemKind == BDLMem)
726         OS << *cast<MCConstantExpr>(Op.Length.Imm) << ",";
727       else if (Op.MemKind == BDRMem)
728         OS << SystemZInstPrinter::getRegisterName(Op.Length.Reg) << ",";
729       if (Op.Index)
730         OS << SystemZInstPrinter::getRegisterName(Op.Index) << ",";
731       OS << SystemZInstPrinter::getRegisterName(Op.Base);
732       OS << ")";
733     }
734     break;
735   }
736   case KindInvalid:
737     break;
738   }
739 }
740 
741 // Parse one register of the form %<prefix><number>.
742 bool SystemZAsmParser::parseRegister(Register &Reg, bool RestoreOnFailure) {
743   Reg.StartLoc = Parser.getTok().getLoc();
744 
745   // Eat the % prefix.
746   if (Parser.getTok().isNot(AsmToken::Percent))
747     return Error(Parser.getTok().getLoc(), "register expected");
748   const AsmToken &PercentTok = Parser.getTok();
749   Parser.Lex();
750 
751   // Expect a register name.
752   if (Parser.getTok().isNot(AsmToken::Identifier)) {
753     if (RestoreOnFailure)
754       getLexer().UnLex(PercentTok);
755     return Error(Reg.StartLoc, "invalid register");
756   }
757 
758   // Check that there's a prefix.
759   StringRef Name = Parser.getTok().getString();
760   if (Name.size() < 2) {
761     if (RestoreOnFailure)
762       getLexer().UnLex(PercentTok);
763     return Error(Reg.StartLoc, "invalid register");
764   }
765   char Prefix = Name[0];
766 
767   // Treat the rest of the register name as a register number.
768   if (Name.substr(1).getAsInteger(10, Reg.Num)) {
769     if (RestoreOnFailure)
770       getLexer().UnLex(PercentTok);
771     return Error(Reg.StartLoc, "invalid register");
772   }
773 
774   // Look for valid combinations of prefix and number.
775   if (Prefix == 'r' && Reg.Num < 16)
776     Reg.Group = RegGR;
777   else if (Prefix == 'f' && Reg.Num < 16)
778     Reg.Group = RegFP;
779   else if (Prefix == 'v' && Reg.Num < 32)
780     Reg.Group = RegV;
781   else if (Prefix == 'a' && Reg.Num < 16)
782     Reg.Group = RegAR;
783   else if (Prefix == 'c' && Reg.Num < 16)
784     Reg.Group = RegCR;
785   else {
786     if (RestoreOnFailure)
787       getLexer().UnLex(PercentTok);
788     return Error(Reg.StartLoc, "invalid register");
789   }
790 
791   Reg.EndLoc = Parser.getTok().getLoc();
792   Parser.Lex();
793   return false;
794 }
795 
796 // Parse a register of kind Kind and add it to Operands.
797 OperandMatchResultTy
798 SystemZAsmParser::parseRegister(OperandVector &Operands, RegisterKind Kind) {
799   Register Reg;
800   RegisterGroup Group;
801   switch (Kind) {
802   case GR32Reg:
803   case GRH32Reg:
804   case GR64Reg:
805   case GR128Reg:
806     Group = RegGR;
807     break;
808   case FP32Reg:
809   case FP64Reg:
810   case FP128Reg:
811     Group = RegFP;
812     break;
813   case VR32Reg:
814   case VR64Reg:
815   case VR128Reg:
816     Group = RegV;
817     break;
818   case AR32Reg:
819     Group = RegAR;
820     break;
821   case CR64Reg:
822     Group = RegCR;
823     break;
824   }
825 
826   // Handle register names of the form %<prefix><number>
827   if (Parser.getTok().is(AsmToken::Percent)) {
828     if (parseRegister(Reg))
829       return MatchOperand_ParseFail;
830 
831     // Check the parsed register group "Reg.Group" with the expected "Group"
832     // Have to error out if user specified wrong prefix.
833     switch (Group) {
834     case RegGR:
835     case RegFP:
836     case RegAR:
837     case RegCR:
838       if (Group != Reg.Group) {
839         Error(Reg.StartLoc, "invalid operand for instruction");
840         return MatchOperand_ParseFail;
841       }
842       break;
843     case RegV:
844       if (Reg.Group != RegV && Reg.Group != RegFP) {
845         Error(Reg.StartLoc, "invalid operand for instruction");
846         return MatchOperand_ParseFail;
847       }
848       break;
849     }
850   } else if (Parser.getTok().is(AsmToken::Integer)) {
851     if (parseIntegerRegister(Reg, Group))
852       return MatchOperand_ParseFail;
853   }
854   // Otherwise we didn't match a register operand.
855   else
856     return MatchOperand_NoMatch;
857 
858   // Determine the LLVM register number according to Kind.
859   const unsigned *Regs;
860   switch (Kind) {
861   case GR32Reg:  Regs = SystemZMC::GR32Regs;  break;
862   case GRH32Reg: Regs = SystemZMC::GRH32Regs; break;
863   case GR64Reg:  Regs = SystemZMC::GR64Regs;  break;
864   case GR128Reg: Regs = SystemZMC::GR128Regs; break;
865   case FP32Reg:  Regs = SystemZMC::FP32Regs;  break;
866   case FP64Reg:  Regs = SystemZMC::FP64Regs;  break;
867   case FP128Reg: Regs = SystemZMC::FP128Regs; break;
868   case VR32Reg:  Regs = SystemZMC::VR32Regs;  break;
869   case VR64Reg:  Regs = SystemZMC::VR64Regs;  break;
870   case VR128Reg: Regs = SystemZMC::VR128Regs; break;
871   case AR32Reg:  Regs = SystemZMC::AR32Regs;  break;
872   case CR64Reg:  Regs = SystemZMC::CR64Regs;  break;
873   }
874   if (Regs[Reg.Num] == 0) {
875     Error(Reg.StartLoc, "invalid register pair");
876     return MatchOperand_ParseFail;
877   }
878 
879   Operands.push_back(
880       SystemZOperand::createReg(Kind, Regs[Reg.Num], Reg.StartLoc, Reg.EndLoc));
881   return MatchOperand_Success;
882 }
883 
884 // Parse any type of register (including integers) and add it to Operands.
885 OperandMatchResultTy
886 SystemZAsmParser::parseAnyRegister(OperandVector &Operands) {
887   SMLoc StartLoc = Parser.getTok().getLoc();
888 
889   // Handle integer values.
890   if (Parser.getTok().is(AsmToken::Integer)) {
891     const MCExpr *Register;
892     if (Parser.parseExpression(Register))
893       return MatchOperand_ParseFail;
894 
895     if (auto *CE = dyn_cast<MCConstantExpr>(Register)) {
896       int64_t Value = CE->getValue();
897       if (Value < 0 || Value > 15) {
898         Error(StartLoc, "invalid register");
899         return MatchOperand_ParseFail;
900       }
901     }
902 
903     SMLoc EndLoc =
904       SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
905 
906     Operands.push_back(SystemZOperand::createImm(Register, StartLoc, EndLoc));
907   }
908   else {
909     Register Reg;
910     if (parseRegister(Reg))
911       return MatchOperand_ParseFail;
912 
913     if (Reg.Num > 15) {
914       Error(StartLoc, "invalid register");
915       return MatchOperand_ParseFail;
916     }
917 
918     // Map to the correct register kind.
919     RegisterKind Kind;
920     unsigned RegNo;
921     if (Reg.Group == RegGR) {
922       Kind = GR64Reg;
923       RegNo = SystemZMC::GR64Regs[Reg.Num];
924     }
925     else if (Reg.Group == RegFP) {
926       Kind = FP64Reg;
927       RegNo = SystemZMC::FP64Regs[Reg.Num];
928     }
929     else if (Reg.Group == RegV) {
930       Kind = VR128Reg;
931       RegNo = SystemZMC::VR128Regs[Reg.Num];
932     }
933     else if (Reg.Group == RegAR) {
934       Kind = AR32Reg;
935       RegNo = SystemZMC::AR32Regs[Reg.Num];
936     }
937     else if (Reg.Group == RegCR) {
938       Kind = CR64Reg;
939       RegNo = SystemZMC::CR64Regs[Reg.Num];
940     }
941     else {
942       return MatchOperand_ParseFail;
943     }
944 
945     Operands.push_back(SystemZOperand::createReg(Kind, RegNo,
946                                                  Reg.StartLoc, Reg.EndLoc));
947   }
948   return MatchOperand_Success;
949 }
950 
951 bool SystemZAsmParser::parseIntegerRegister(Register &Reg,
952                                             RegisterGroup Group) {
953   Reg.StartLoc = Parser.getTok().getLoc();
954   // We have an integer token
955   const MCExpr *Register;
956   if (Parser.parseExpression(Register))
957     return true;
958 
959   const auto *CE = dyn_cast<MCConstantExpr>(Register);
960   if (!CE)
961     return true;
962 
963   int64_t MaxRegNum = (Group == RegV) ? 31 : 15;
964   int64_t Value = CE->getValue();
965   if (Value < 0 || Value > MaxRegNum) {
966     Error(Parser.getTok().getLoc(), "invalid register");
967     return true;
968   }
969 
970   // Assign the Register Number
971   Reg.Num = (unsigned)Value;
972   Reg.Group = Group;
973   Reg.EndLoc = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
974 
975   // At this point, successfully parsed an integer register.
976   return false;
977 }
978 
979 // Parse a memory operand into Reg1, Reg2, Disp, and Length.
980 bool SystemZAsmParser::parseAddress(bool &HaveReg1, Register &Reg1,
981                                     bool &HaveReg2, Register &Reg2,
982                                     const MCExpr *&Disp, const MCExpr *&Length,
983                                     bool HasLength, bool HasVectorIndex) {
984   // Parse the displacement, which must always be present.
985   if (getParser().parseExpression(Disp))
986     return true;
987 
988   // Parse the optional base and index.
989   HaveReg1 = false;
990   HaveReg2 = false;
991   Length = nullptr;
992 
993   // If we have a scenario as below:
994   //   vgef %v0, 0(0), 0
995   // This is an example of a "BDVMem" instruction type.
996   //
997   // So when we parse this as an integer register, the register group
998   // needs to be tied to "RegV". Usually when the prefix is passed in
999   // as %<prefix><reg-number> its easy to check which group it should belong to
1000   // However, if we're passing in just the integer there's no real way to
1001   // "check" what register group it should belong to.
1002   //
1003   // When the user passes in the register as an integer, the user assumes that
1004   // the compiler is responsible for substituting it as the right kind of
1005   // register. Whereas, when the user specifies a "prefix", the onus is on
1006   // the user to make sure they pass in the right kind of register.
1007   //
1008   // The restriction only applies to the first Register (i.e. Reg1). Reg2 is
1009   // always a general register. Reg1 should be of group RegV if "HasVectorIndex"
1010   // (i.e. insn is of type BDVMem) is true.
1011   RegisterGroup RegGroup = HasVectorIndex ? RegV : RegGR;
1012 
1013   if (getLexer().is(AsmToken::LParen)) {
1014     Parser.Lex();
1015 
1016     if (getLexer().is(AsmToken::Percent)) {
1017       // Parse the first register.
1018       HaveReg1 = true;
1019       if (parseRegister(Reg1))
1020         return true;
1021     }
1022     // So if we have an integer as the first token in ([tok1], ..), it could:
1023     // 1. Refer to a "Register" (i.e X,R,V fields in BD[X|R|V]Mem type of
1024     // instructions)
1025     // 2. Refer to a "Length" field (i.e L field in BDLMem type of instructions)
1026     else if (getLexer().is(AsmToken::Integer)) {
1027       if (HasLength) {
1028         // Instruction has a "Length" field, safe to parse the first token as
1029         // the "Length" field
1030         if (getParser().parseExpression(Length))
1031           return true;
1032       } else {
1033         // Otherwise, if the instruction has no "Length" field, parse the
1034         // token as a "Register". We don't have to worry about whether the
1035         // instruction is invalid here, because the caller will take care of
1036         // error reporting.
1037         HaveReg1 = true;
1038         if (parseIntegerRegister(Reg1, RegGroup))
1039           return true;
1040       }
1041     } else {
1042       // If its not an integer or a percent token, then if the instruction
1043       // is reported to have a "Length" then, parse it as "Length".
1044       if (HasLength) {
1045         if (getParser().parseExpression(Length))
1046           return true;
1047       }
1048     }
1049 
1050     // Check whether there's a second register.
1051     if (getLexer().is(AsmToken::Comma)) {
1052       Parser.Lex();
1053       HaveReg2 = true;
1054 
1055       if (getLexer().is(AsmToken::Integer)) {
1056         if (parseIntegerRegister(Reg2, RegGR))
1057           return true;
1058       } else {
1059         if (parseRegister(Reg2))
1060           return true;
1061       }
1062     }
1063 
1064     // Consume the closing bracket.
1065     if (getLexer().isNot(AsmToken::RParen))
1066       return Error(Parser.getTok().getLoc(), "unexpected token in address");
1067     Parser.Lex();
1068   }
1069   return false;
1070 }
1071 
1072 // Verify that Reg is a valid address register (base or index).
1073 bool
1074 SystemZAsmParser::parseAddressRegister(Register &Reg) {
1075   if (Reg.Group == RegV) {
1076     Error(Reg.StartLoc, "invalid use of vector addressing");
1077     return true;
1078   } else if (Reg.Group != RegGR) {
1079     Error(Reg.StartLoc, "invalid address register");
1080     return true;
1081   }
1082   return false;
1083 }
1084 
1085 // Parse a memory operand and add it to Operands.  The other arguments
1086 // are as above.
1087 OperandMatchResultTy
1088 SystemZAsmParser::parseAddress(OperandVector &Operands, MemoryKind MemKind,
1089                                RegisterKind RegKind) {
1090   SMLoc StartLoc = Parser.getTok().getLoc();
1091   unsigned Base = 0, Index = 0, LengthReg = 0;
1092   Register Reg1, Reg2;
1093   bool HaveReg1, HaveReg2;
1094   const MCExpr *Disp;
1095   const MCExpr *Length;
1096 
1097   bool HasLength = (MemKind == BDLMem) ? true : false;
1098   bool HasVectorIndex = (MemKind == BDVMem) ? true : false;
1099   if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length, HasLength,
1100                    HasVectorIndex))
1101     return MatchOperand_ParseFail;
1102 
1103   const unsigned *Regs;
1104   switch (RegKind) {
1105   case GR32Reg: Regs = SystemZMC::GR32Regs; break;
1106   case GR64Reg: Regs = SystemZMC::GR64Regs; break;
1107   default: llvm_unreachable("invalid RegKind");
1108   }
1109 
1110   switch (MemKind) {
1111   case BDMem:
1112     // If we have Reg1, it must be an address register.
1113     if (HaveReg1) {
1114       if (parseAddressRegister(Reg1))
1115         return MatchOperand_ParseFail;
1116       Base = Regs[Reg1.Num];
1117     }
1118     // There must be no Reg2.
1119     if (HaveReg2) {
1120       Error(StartLoc, "invalid use of indexed addressing");
1121       return MatchOperand_ParseFail;
1122     }
1123     break;
1124   case BDXMem:
1125     // If we have Reg1, it must be an address register.
1126     if (HaveReg1) {
1127       if (parseAddressRegister(Reg1))
1128         return MatchOperand_ParseFail;
1129       // If the are two registers, the first one is the index and the
1130       // second is the base.
1131       if (HaveReg2)
1132         Index = Regs[Reg1.Num];
1133       else
1134         Base = Regs[Reg1.Num];
1135     }
1136     // If we have Reg2, it must be an address register.
1137     if (HaveReg2) {
1138       if (parseAddressRegister(Reg2))
1139         return MatchOperand_ParseFail;
1140       Base = Regs[Reg2.Num];
1141     }
1142     break;
1143   case BDLMem:
1144     // If we have Reg2, it must be an address register.
1145     if (HaveReg2) {
1146       if (parseAddressRegister(Reg2))
1147         return MatchOperand_ParseFail;
1148       Base = Regs[Reg2.Num];
1149     }
1150     // We cannot support base+index addressing.
1151     if (HaveReg1 && HaveReg2) {
1152       Error(StartLoc, "invalid use of indexed addressing");
1153       return MatchOperand_ParseFail;
1154     }
1155     // We must have a length.
1156     if (!Length) {
1157       Error(StartLoc, "missing length in address");
1158       return MatchOperand_ParseFail;
1159     }
1160     break;
1161   case BDRMem:
1162     // We must have Reg1, and it must be a GPR.
1163     if (!HaveReg1 || Reg1.Group != RegGR) {
1164       Error(StartLoc, "invalid operand for instruction");
1165       return MatchOperand_ParseFail;
1166     }
1167     LengthReg = SystemZMC::GR64Regs[Reg1.Num];
1168     // If we have Reg2, it must be an address register.
1169     if (HaveReg2) {
1170       if (parseAddressRegister(Reg2))
1171         return MatchOperand_ParseFail;
1172       Base = Regs[Reg2.Num];
1173     }
1174     break;
1175   case BDVMem:
1176     // We must have Reg1, and it must be a vector register.
1177     if (!HaveReg1 || Reg1.Group != RegV) {
1178       Error(StartLoc, "vector index required in address");
1179       return MatchOperand_ParseFail;
1180     }
1181     Index = SystemZMC::VR128Regs[Reg1.Num];
1182     // If we have Reg2, it must be an address register.
1183     if (HaveReg2) {
1184       if (parseAddressRegister(Reg2))
1185         return MatchOperand_ParseFail;
1186       Base = Regs[Reg2.Num];
1187     }
1188     break;
1189   }
1190 
1191   SMLoc EndLoc =
1192       SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1193   Operands.push_back(SystemZOperand::createMem(MemKind, RegKind, Base, Disp,
1194                                                Index, Length, LengthReg,
1195                                                StartLoc, EndLoc));
1196   return MatchOperand_Success;
1197 }
1198 
1199 bool SystemZAsmParser::ParseDirective(AsmToken DirectiveID) {
1200   StringRef IDVal = DirectiveID.getIdentifier();
1201 
1202   if (IDVal == ".insn")
1203     return ParseDirectiveInsn(DirectiveID.getLoc());
1204 
1205   return true;
1206 }
1207 
1208 /// ParseDirectiveInsn
1209 /// ::= .insn [ format, encoding, (operands (, operands)*) ]
1210 bool SystemZAsmParser::ParseDirectiveInsn(SMLoc L) {
1211   MCAsmParser &Parser = getParser();
1212 
1213   // Expect instruction format as identifier.
1214   StringRef Format;
1215   SMLoc ErrorLoc = Parser.getTok().getLoc();
1216   if (Parser.parseIdentifier(Format))
1217     return Error(ErrorLoc, "expected instruction format");
1218 
1219   SmallVector<std::unique_ptr<MCParsedAsmOperand>, 8> Operands;
1220 
1221   // Find entry for this format in InsnMatchTable.
1222   auto EntryRange =
1223     std::equal_range(std::begin(InsnMatchTable), std::end(InsnMatchTable),
1224                      Format, CompareInsn());
1225 
1226   // If first == second, couldn't find a match in the table.
1227   if (EntryRange.first == EntryRange.second)
1228     return Error(ErrorLoc, "unrecognized format");
1229 
1230   struct InsnMatchEntry *Entry = EntryRange.first;
1231 
1232   // Format should match from equal_range.
1233   assert(Entry->Format == Format);
1234 
1235   // Parse the following operands using the table's information.
1236   for (int i = 0; i < Entry->NumOperands; i++) {
1237     MatchClassKind Kind = Entry->OperandKinds[i];
1238 
1239     SMLoc StartLoc = Parser.getTok().getLoc();
1240 
1241     // Always expect commas as separators for operands.
1242     if (getLexer().isNot(AsmToken::Comma))
1243       return Error(StartLoc, "unexpected token in directive");
1244     Lex();
1245 
1246     // Parse operands.
1247     OperandMatchResultTy ResTy;
1248     if (Kind == MCK_AnyReg)
1249       ResTy = parseAnyReg(Operands);
1250     else if (Kind == MCK_VR128)
1251       ResTy = parseVR128(Operands);
1252     else if (Kind == MCK_BDXAddr64Disp12 || Kind == MCK_BDXAddr64Disp20)
1253       ResTy = parseBDXAddr64(Operands);
1254     else if (Kind == MCK_BDAddr64Disp12 || Kind == MCK_BDAddr64Disp20)
1255       ResTy = parseBDAddr64(Operands);
1256     else if (Kind == MCK_BDVAddr64Disp12)
1257       ResTy = parseBDVAddr64(Operands);
1258     else if (Kind == MCK_PCRel32)
1259       ResTy = parsePCRel32(Operands);
1260     else if (Kind == MCK_PCRel16)
1261       ResTy = parsePCRel16(Operands);
1262     else {
1263       // Only remaining operand kind is an immediate.
1264       const MCExpr *Expr;
1265       SMLoc StartLoc = Parser.getTok().getLoc();
1266 
1267       // Expect immediate expression.
1268       if (Parser.parseExpression(Expr))
1269         return Error(StartLoc, "unexpected token in directive");
1270 
1271       SMLoc EndLoc =
1272         SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1273 
1274       Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1275       ResTy = MatchOperand_Success;
1276     }
1277 
1278     if (ResTy != MatchOperand_Success)
1279       return true;
1280   }
1281 
1282   // Build the instruction with the parsed operands.
1283   MCInst Inst = MCInstBuilder(Entry->Opcode);
1284 
1285   for (size_t i = 0; i < Operands.size(); i++) {
1286     MCParsedAsmOperand &Operand = *Operands[i];
1287     MatchClassKind Kind = Entry->OperandKinds[i];
1288 
1289     // Verify operand.
1290     unsigned Res = validateOperandClass(Operand, Kind);
1291     if (Res != Match_Success)
1292       return Error(Operand.getStartLoc(), "unexpected operand type");
1293 
1294     // Add operands to instruction.
1295     SystemZOperand &ZOperand = static_cast<SystemZOperand &>(Operand);
1296     if (ZOperand.isReg())
1297       ZOperand.addRegOperands(Inst, 1);
1298     else if (ZOperand.isMem(BDMem))
1299       ZOperand.addBDAddrOperands(Inst, 2);
1300     else if (ZOperand.isMem(BDXMem))
1301       ZOperand.addBDXAddrOperands(Inst, 3);
1302     else if (ZOperand.isMem(BDVMem))
1303       ZOperand.addBDVAddrOperands(Inst, 3);
1304     else if (ZOperand.isImm())
1305       ZOperand.addImmOperands(Inst, 1);
1306     else
1307       llvm_unreachable("unexpected operand type");
1308   }
1309 
1310   // Emit as a regular instruction.
1311   Parser.getStreamer().emitInstruction(Inst, getSTI());
1312 
1313   return false;
1314 }
1315 
1316 bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1317                                      SMLoc &EndLoc, bool RestoreOnFailure) {
1318   Register Reg;
1319   if (parseRegister(Reg, RestoreOnFailure))
1320     return true;
1321   if (Reg.Group == RegGR)
1322     RegNo = SystemZMC::GR64Regs[Reg.Num];
1323   else if (Reg.Group == RegFP)
1324     RegNo = SystemZMC::FP64Regs[Reg.Num];
1325   else if (Reg.Group == RegV)
1326     RegNo = SystemZMC::VR128Regs[Reg.Num];
1327   else if (Reg.Group == RegAR)
1328     RegNo = SystemZMC::AR32Regs[Reg.Num];
1329   else if (Reg.Group == RegCR)
1330     RegNo = SystemZMC::CR64Regs[Reg.Num];
1331   StartLoc = Reg.StartLoc;
1332   EndLoc = Reg.EndLoc;
1333   return false;
1334 }
1335 
1336 bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1337                                      SMLoc &EndLoc) {
1338   return ParseRegister(RegNo, StartLoc, EndLoc, /*RestoreOnFailure=*/false);
1339 }
1340 
1341 OperandMatchResultTy SystemZAsmParser::tryParseRegister(unsigned &RegNo,
1342                                                         SMLoc &StartLoc,
1343                                                         SMLoc &EndLoc) {
1344   bool Result =
1345       ParseRegister(RegNo, StartLoc, EndLoc, /*RestoreOnFailure=*/true);
1346   bool PendingErrors = getParser().hasPendingError();
1347   getParser().clearPendingErrors();
1348   if (PendingErrors)
1349     return MatchOperand_ParseFail;
1350   if (Result)
1351     return MatchOperand_NoMatch;
1352   return MatchOperand_Success;
1353 }
1354 
1355 bool SystemZAsmParser::ParseInstruction(ParseInstructionInfo &Info,
1356                                         StringRef Name, SMLoc NameLoc,
1357                                         OperandVector &Operands) {
1358 
1359   // Apply mnemonic aliases first, before doing anything else, in
1360   // case the target uses it.
1361   applyMnemonicAliases(Name, getAvailableFeatures(), getMAIAssemblerDialect());
1362 
1363   Operands.push_back(SystemZOperand::createToken(Name, NameLoc));
1364 
1365   // Read the remaining operands.
1366   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1367     // Read the first operand.
1368     if (parseOperand(Operands, Name)) {
1369       return true;
1370     }
1371 
1372     // Read any subsequent operands.
1373     while (getLexer().is(AsmToken::Comma)) {
1374       Parser.Lex();
1375       if (parseOperand(Operands, Name)) {
1376         return true;
1377       }
1378     }
1379     if (getLexer().isNot(AsmToken::EndOfStatement)) {
1380       SMLoc Loc = getLexer().getLoc();
1381       return Error(Loc, "unexpected token in argument list");
1382     }
1383   }
1384 
1385   // Consume the EndOfStatement.
1386   Parser.Lex();
1387   return false;
1388 }
1389 
1390 bool SystemZAsmParser::parseOperand(OperandVector &Operands,
1391                                     StringRef Mnemonic) {
1392   // Check if the current operand has a custom associated parser, if so, try to
1393   // custom parse the operand, or fallback to the general approach.  Force all
1394   // features to be available during the operand check, or else we will fail to
1395   // find the custom parser, and then we will later get an InvalidOperand error
1396   // instead of a MissingFeature errror.
1397   FeatureBitset AvailableFeatures = getAvailableFeatures();
1398   FeatureBitset All;
1399   All.set();
1400   setAvailableFeatures(All);
1401   OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
1402   setAvailableFeatures(AvailableFeatures);
1403   if (ResTy == MatchOperand_Success)
1404     return false;
1405 
1406   // If there wasn't a custom match, try the generic matcher below. Otherwise,
1407   // there was a match, but an error occurred, in which case, just return that
1408   // the operand parsing failed.
1409   if (ResTy == MatchOperand_ParseFail)
1410     return true;
1411 
1412   // Check for a register.  All real register operands should have used
1413   // a context-dependent parse routine, which gives the required register
1414   // class.  The code is here to mop up other cases, like those where
1415   // the instruction isn't recognized.
1416   if (Parser.getTok().is(AsmToken::Percent)) {
1417     Register Reg;
1418     if (parseRegister(Reg))
1419       return true;
1420     Operands.push_back(SystemZOperand::createInvalid(Reg.StartLoc, Reg.EndLoc));
1421     return false;
1422   }
1423 
1424   // The only other type of operand is an immediate or address.  As above,
1425   // real address operands should have used a context-dependent parse routine,
1426   // so we treat any plain expression as an immediate.
1427   SMLoc StartLoc = Parser.getTok().getLoc();
1428   Register Reg1, Reg2;
1429   bool HaveReg1, HaveReg2;
1430   const MCExpr *Expr;
1431   const MCExpr *Length;
1432   if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Expr, Length,
1433                    /*HasLength*/ true, /*HasVectorIndex*/ true))
1434     return true;
1435   // If the register combination is not valid for any instruction, reject it.
1436   // Otherwise, fall back to reporting an unrecognized instruction.
1437   if (HaveReg1 && Reg1.Group != RegGR && Reg1.Group != RegV
1438       && parseAddressRegister(Reg1))
1439     return true;
1440   if (HaveReg2 && parseAddressRegister(Reg2))
1441     return true;
1442 
1443   SMLoc EndLoc =
1444     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1445   if (HaveReg1 || HaveReg2 || Length)
1446     Operands.push_back(SystemZOperand::createInvalid(StartLoc, EndLoc));
1447   else
1448     Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1449   return false;
1450 }
1451 
1452 static std::string SystemZMnemonicSpellCheck(StringRef S,
1453                                              const FeatureBitset &FBS,
1454                                              unsigned VariantID = 0);
1455 
1456 bool SystemZAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1457                                                OperandVector &Operands,
1458                                                MCStreamer &Out,
1459                                                uint64_t &ErrorInfo,
1460                                                bool MatchingInlineAsm) {
1461   MCInst Inst;
1462   unsigned MatchResult;
1463 
1464   unsigned Dialect = getMAIAssemblerDialect();
1465 
1466   FeatureBitset MissingFeatures;
1467   MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo, MissingFeatures,
1468                                      MatchingInlineAsm, Dialect);
1469   switch (MatchResult) {
1470   case Match_Success:
1471     Inst.setLoc(IDLoc);
1472     Out.emitInstruction(Inst, getSTI());
1473     return false;
1474 
1475   case Match_MissingFeature: {
1476     assert(MissingFeatures.any() && "Unknown missing feature!");
1477     // Special case the error message for the very common case where only
1478     // a single subtarget feature is missing
1479     std::string Msg = "instruction requires:";
1480     for (unsigned I = 0, E = MissingFeatures.size(); I != E; ++I) {
1481       if (MissingFeatures[I]) {
1482         Msg += " ";
1483         Msg += getSubtargetFeatureName(I);
1484       }
1485     }
1486     return Error(IDLoc, Msg);
1487   }
1488 
1489   case Match_InvalidOperand: {
1490     SMLoc ErrorLoc = IDLoc;
1491     if (ErrorInfo != ~0ULL) {
1492       if (ErrorInfo >= Operands.size())
1493         return Error(IDLoc, "too few operands for instruction");
1494 
1495       ErrorLoc = ((SystemZOperand &)*Operands[ErrorInfo]).getStartLoc();
1496       if (ErrorLoc == SMLoc())
1497         ErrorLoc = IDLoc;
1498     }
1499     return Error(ErrorLoc, "invalid operand for instruction");
1500   }
1501 
1502   case Match_MnemonicFail: {
1503     FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits());
1504     std::string Suggestion = SystemZMnemonicSpellCheck(
1505         ((SystemZOperand &)*Operands[0]).getToken(), FBS, Dialect);
1506     return Error(IDLoc, "invalid instruction" + Suggestion,
1507                  ((SystemZOperand &)*Operands[0]).getLocRange());
1508   }
1509   }
1510 
1511   llvm_unreachable("Unexpected match type");
1512 }
1513 
1514 OperandMatchResultTy
1515 SystemZAsmParser::parsePCRel(OperandVector &Operands, int64_t MinVal,
1516                              int64_t MaxVal, bool AllowTLS) {
1517   MCContext &Ctx = getContext();
1518   MCStreamer &Out = getStreamer();
1519   const MCExpr *Expr;
1520   SMLoc StartLoc = Parser.getTok().getLoc();
1521   if (getParser().parseExpression(Expr))
1522     return MatchOperand_NoMatch;
1523 
1524   auto isOutOfRangeConstant = [&](const MCExpr *E) -> bool {
1525     if (auto *CE = dyn_cast<MCConstantExpr>(E)) {
1526       int64_t Value = CE->getValue();
1527       if ((Value & 1) || Value < MinVal || Value > MaxVal)
1528         return true;
1529     }
1530     return false;
1531   };
1532 
1533   // For consistency with the GNU assembler, treat immediates as offsets
1534   // from ".".
1535   if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
1536     if (isOutOfRangeConstant(CE)) {
1537       Error(StartLoc, "offset out of range");
1538       return MatchOperand_ParseFail;
1539     }
1540     int64_t Value = CE->getValue();
1541     MCSymbol *Sym = Ctx.createTempSymbol();
1542     Out.emitLabel(Sym);
1543     const MCExpr *Base = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None,
1544                                                  Ctx);
1545     Expr = Value == 0 ? Base : MCBinaryExpr::createAdd(Base, Expr, Ctx);
1546   }
1547 
1548   // For consistency with the GNU assembler, conservatively assume that a
1549   // constant offset must by itself be within the given size range.
1550   if (const auto *BE = dyn_cast<MCBinaryExpr>(Expr))
1551     if (isOutOfRangeConstant(BE->getLHS()) ||
1552         isOutOfRangeConstant(BE->getRHS())) {
1553       Error(StartLoc, "offset out of range");
1554       return MatchOperand_ParseFail;
1555     }
1556 
1557   // Optionally match :tls_gdcall: or :tls_ldcall: followed by a TLS symbol.
1558   const MCExpr *Sym = nullptr;
1559   if (AllowTLS && getLexer().is(AsmToken::Colon)) {
1560     Parser.Lex();
1561 
1562     if (Parser.getTok().isNot(AsmToken::Identifier)) {
1563       Error(Parser.getTok().getLoc(), "unexpected token");
1564       return MatchOperand_ParseFail;
1565     }
1566 
1567     MCSymbolRefExpr::VariantKind Kind = MCSymbolRefExpr::VK_None;
1568     StringRef Name = Parser.getTok().getString();
1569     if (Name == "tls_gdcall")
1570       Kind = MCSymbolRefExpr::VK_TLSGD;
1571     else if (Name == "tls_ldcall")
1572       Kind = MCSymbolRefExpr::VK_TLSLDM;
1573     else {
1574       Error(Parser.getTok().getLoc(), "unknown TLS tag");
1575       return MatchOperand_ParseFail;
1576     }
1577     Parser.Lex();
1578 
1579     if (Parser.getTok().isNot(AsmToken::Colon)) {
1580       Error(Parser.getTok().getLoc(), "unexpected token");
1581       return MatchOperand_ParseFail;
1582     }
1583     Parser.Lex();
1584 
1585     if (Parser.getTok().isNot(AsmToken::Identifier)) {
1586       Error(Parser.getTok().getLoc(), "unexpected token");
1587       return MatchOperand_ParseFail;
1588     }
1589 
1590     StringRef Identifier = Parser.getTok().getString();
1591     Sym = MCSymbolRefExpr::create(Ctx.getOrCreateSymbol(Identifier),
1592                                   Kind, Ctx);
1593     Parser.Lex();
1594   }
1595 
1596   SMLoc EndLoc =
1597     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1598 
1599   if (AllowTLS)
1600     Operands.push_back(SystemZOperand::createImmTLS(Expr, Sym,
1601                                                     StartLoc, EndLoc));
1602   else
1603     Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1604 
1605   return MatchOperand_Success;
1606 }
1607 
1608 bool SystemZAsmParser::isLabel(AsmToken &Token) {
1609   if (getMAIAssemblerDialect() == AD_ATT)
1610     return true;
1611 
1612   // HLASM labels are ordinary symbols.
1613   // An HLASM label always starts at column 1.
1614   // An ordinary symbol syntax is laid out as follows:
1615   // Rules:
1616   // 1. Has to start with an "alphabetic character". Can be followed by up to
1617   //    62 alphanumeric characters. An "alphabetic character", in this scenario,
1618   //    is a letter from 'A' through 'Z', or from 'a' through 'z',
1619   //    or '$', '_', '#', or '@'
1620   // 2. Labels are case-insensitive. E.g. "lab123", "LAB123", "lAb123", etc.
1621   //    are all treated as the same symbol. However, the processing for the case
1622   //    folding will not be done in this function.
1623   StringRef RawLabel = Token.getString();
1624   SMLoc Loc = Token.getLoc();
1625 
1626   // An HLASM label cannot be empty.
1627   if (!RawLabel.size())
1628     return !Error(Loc, "HLASM Label cannot be empty");
1629 
1630   // An HLASM label cannot exceed greater than 63 characters.
1631   if (RawLabel.size() > 63)
1632     return !Error(Loc, "Maximum length for HLASM Label is 63 characters");
1633 
1634   // A label must start with an "alphabetic character".
1635   if (!isHLASMAlpha(RawLabel[0]))
1636     return !Error(Loc, "HLASM Label has to start with an alphabetic "
1637                        "character or the underscore character");
1638 
1639   // Now, we've established that the length is valid
1640   // and the first character is alphabetic.
1641   // Check whether remaining string is alphanumeric.
1642   for (unsigned I = 1; I < RawLabel.size(); ++I)
1643     if (!isHLASMAlnum(RawLabel[I]))
1644       return !Error(Loc, "HLASM Label has to be alphanumeric");
1645 
1646   return true;
1647 }
1648 
1649 // Force static initialization.
1650 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSystemZAsmParser() {
1651   RegisterMCAsmParser<SystemZAsmParser> X(getTheSystemZTarget());
1652 }
1653