1 //===-- SystemZAsmParser.cpp - Parse SystemZ assembly instructions --------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "MCTargetDesc/SystemZInstPrinter.h" 10 #include "MCTargetDesc/SystemZMCTargetDesc.h" 11 #include "TargetInfo/SystemZTargetInfo.h" 12 #include "llvm/ADT/STLExtras.h" 13 #include "llvm/ADT/SmallVector.h" 14 #include "llvm/ADT/StringRef.h" 15 #include "llvm/MC/MCContext.h" 16 #include "llvm/MC/MCExpr.h" 17 #include "llvm/MC/MCInst.h" 18 #include "llvm/MC/MCInstBuilder.h" 19 #include "llvm/MC/MCParser/MCAsmLexer.h" 20 #include "llvm/MC/MCParser/MCAsmParser.h" 21 #include "llvm/MC/MCParser/MCAsmParserExtension.h" 22 #include "llvm/MC/MCParser/MCParsedAsmOperand.h" 23 #include "llvm/MC/MCParser/MCTargetAsmParser.h" 24 #include "llvm/MC/MCStreamer.h" 25 #include "llvm/MC/MCSubtargetInfo.h" 26 #include "llvm/Support/Casting.h" 27 #include "llvm/Support/ErrorHandling.h" 28 #include "llvm/Support/SMLoc.h" 29 #include "llvm/Support/TargetRegistry.h" 30 #include <algorithm> 31 #include <cassert> 32 #include <cstddef> 33 #include <cstdint> 34 #include <iterator> 35 #include <memory> 36 #include <string> 37 38 using namespace llvm; 39 40 // Return true if Expr is in the range [MinValue, MaxValue]. 41 static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue) { 42 if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) { 43 int64_t Value = CE->getValue(); 44 return Value >= MinValue && Value <= MaxValue; 45 } 46 return false; 47 } 48 49 namespace { 50 51 enum RegisterKind { 52 GR32Reg, 53 GRH32Reg, 54 GR64Reg, 55 GR128Reg, 56 FP32Reg, 57 FP64Reg, 58 FP128Reg, 59 VR32Reg, 60 VR64Reg, 61 VR128Reg, 62 AR32Reg, 63 CR64Reg, 64 }; 65 66 enum MemoryKind { 67 BDMem, 68 BDXMem, 69 BDLMem, 70 BDRMem, 71 BDVMem 72 }; 73 74 class SystemZOperand : public MCParsedAsmOperand { 75 private: 76 enum OperandKind { 77 KindInvalid, 78 KindToken, 79 KindReg, 80 KindImm, 81 KindImmTLS, 82 KindMem 83 }; 84 85 OperandKind Kind; 86 SMLoc StartLoc, EndLoc; 87 88 // A string of length Length, starting at Data. 89 struct TokenOp { 90 const char *Data; 91 unsigned Length; 92 }; 93 94 // LLVM register Num, which has kind Kind. In some ways it might be 95 // easier for this class to have a register bank (general, floating-point 96 // or access) and a raw register number (0-15). This would postpone the 97 // interpretation of the operand to the add*() methods and avoid the need 98 // for context-dependent parsing. However, we do things the current way 99 // because of the virtual getReg() method, which needs to distinguish 100 // between (say) %r0 used as a single register and %r0 used as a pair. 101 // Context-dependent parsing can also give us slightly better error 102 // messages when invalid pairs like %r1 are used. 103 struct RegOp { 104 RegisterKind Kind; 105 unsigned Num; 106 }; 107 108 // Base + Disp + Index, where Base and Index are LLVM registers or 0. 109 // MemKind says what type of memory this is and RegKind says what type 110 // the base register has (GR32Reg or GR64Reg). Length is the operand 111 // length for D(L,B)-style operands, otherwise it is null. 112 struct MemOp { 113 unsigned Base : 12; 114 unsigned Index : 12; 115 unsigned MemKind : 4; 116 unsigned RegKind : 4; 117 const MCExpr *Disp; 118 union { 119 const MCExpr *Imm; 120 unsigned Reg; 121 } Length; 122 }; 123 124 // Imm is an immediate operand, and Sym is an optional TLS symbol 125 // for use with a __tls_get_offset marker relocation. 126 struct ImmTLSOp { 127 const MCExpr *Imm; 128 const MCExpr *Sym; 129 }; 130 131 union { 132 TokenOp Token; 133 RegOp Reg; 134 const MCExpr *Imm; 135 ImmTLSOp ImmTLS; 136 MemOp Mem; 137 }; 138 139 void addExpr(MCInst &Inst, const MCExpr *Expr) const { 140 // Add as immediates when possible. Null MCExpr = 0. 141 if (!Expr) 142 Inst.addOperand(MCOperand::createImm(0)); 143 else if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) 144 Inst.addOperand(MCOperand::createImm(CE->getValue())); 145 else 146 Inst.addOperand(MCOperand::createExpr(Expr)); 147 } 148 149 public: 150 SystemZOperand(OperandKind kind, SMLoc startLoc, SMLoc endLoc) 151 : Kind(kind), StartLoc(startLoc), EndLoc(endLoc) {} 152 153 // Create particular kinds of operand. 154 static std::unique_ptr<SystemZOperand> createInvalid(SMLoc StartLoc, 155 SMLoc EndLoc) { 156 return std::make_unique<SystemZOperand>(KindInvalid, StartLoc, EndLoc); 157 } 158 159 static std::unique_ptr<SystemZOperand> createToken(StringRef Str, SMLoc Loc) { 160 auto Op = std::make_unique<SystemZOperand>(KindToken, Loc, Loc); 161 Op->Token.Data = Str.data(); 162 Op->Token.Length = Str.size(); 163 return Op; 164 } 165 166 static std::unique_ptr<SystemZOperand> 167 createReg(RegisterKind Kind, unsigned Num, SMLoc StartLoc, SMLoc EndLoc) { 168 auto Op = std::make_unique<SystemZOperand>(KindReg, StartLoc, EndLoc); 169 Op->Reg.Kind = Kind; 170 Op->Reg.Num = Num; 171 return Op; 172 } 173 174 static std::unique_ptr<SystemZOperand> 175 createImm(const MCExpr *Expr, SMLoc StartLoc, SMLoc EndLoc) { 176 auto Op = std::make_unique<SystemZOperand>(KindImm, StartLoc, EndLoc); 177 Op->Imm = Expr; 178 return Op; 179 } 180 181 static std::unique_ptr<SystemZOperand> 182 createMem(MemoryKind MemKind, RegisterKind RegKind, unsigned Base, 183 const MCExpr *Disp, unsigned Index, const MCExpr *LengthImm, 184 unsigned LengthReg, SMLoc StartLoc, SMLoc EndLoc) { 185 auto Op = std::make_unique<SystemZOperand>(KindMem, StartLoc, EndLoc); 186 Op->Mem.MemKind = MemKind; 187 Op->Mem.RegKind = RegKind; 188 Op->Mem.Base = Base; 189 Op->Mem.Index = Index; 190 Op->Mem.Disp = Disp; 191 if (MemKind == BDLMem) 192 Op->Mem.Length.Imm = LengthImm; 193 if (MemKind == BDRMem) 194 Op->Mem.Length.Reg = LengthReg; 195 return Op; 196 } 197 198 static std::unique_ptr<SystemZOperand> 199 createImmTLS(const MCExpr *Imm, const MCExpr *Sym, 200 SMLoc StartLoc, SMLoc EndLoc) { 201 auto Op = std::make_unique<SystemZOperand>(KindImmTLS, StartLoc, EndLoc); 202 Op->ImmTLS.Imm = Imm; 203 Op->ImmTLS.Sym = Sym; 204 return Op; 205 } 206 207 // Token operands 208 bool isToken() const override { 209 return Kind == KindToken; 210 } 211 StringRef getToken() const { 212 assert(Kind == KindToken && "Not a token"); 213 return StringRef(Token.Data, Token.Length); 214 } 215 216 // Register operands. 217 bool isReg() const override { 218 return Kind == KindReg; 219 } 220 bool isReg(RegisterKind RegKind) const { 221 return Kind == KindReg && Reg.Kind == RegKind; 222 } 223 unsigned getReg() const override { 224 assert(Kind == KindReg && "Not a register"); 225 return Reg.Num; 226 } 227 228 // Immediate operands. 229 bool isImm() const override { 230 return Kind == KindImm; 231 } 232 bool isImm(int64_t MinValue, int64_t MaxValue) const { 233 return Kind == KindImm && inRange(Imm, MinValue, MaxValue); 234 } 235 const MCExpr *getImm() const { 236 assert(Kind == KindImm && "Not an immediate"); 237 return Imm; 238 } 239 240 // Immediate operands with optional TLS symbol. 241 bool isImmTLS() const { 242 return Kind == KindImmTLS; 243 } 244 245 const ImmTLSOp getImmTLS() const { 246 assert(Kind == KindImmTLS && "Not a TLS immediate"); 247 return ImmTLS; 248 } 249 250 // Memory operands. 251 bool isMem() const override { 252 return Kind == KindMem; 253 } 254 bool isMem(MemoryKind MemKind) const { 255 return (Kind == KindMem && 256 (Mem.MemKind == MemKind || 257 // A BDMem can be treated as a BDXMem in which the index 258 // register field is 0. 259 (Mem.MemKind == BDMem && MemKind == BDXMem))); 260 } 261 bool isMem(MemoryKind MemKind, RegisterKind RegKind) const { 262 return isMem(MemKind) && Mem.RegKind == RegKind; 263 } 264 bool isMemDisp12(MemoryKind MemKind, RegisterKind RegKind) const { 265 return isMem(MemKind, RegKind) && inRange(Mem.Disp, 0, 0xfff); 266 } 267 bool isMemDisp20(MemoryKind MemKind, RegisterKind RegKind) const { 268 return isMem(MemKind, RegKind) && inRange(Mem.Disp, -524288, 524287); 269 } 270 bool isMemDisp12Len4(RegisterKind RegKind) const { 271 return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length.Imm, 1, 0x10); 272 } 273 bool isMemDisp12Len8(RegisterKind RegKind) const { 274 return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length.Imm, 1, 0x100); 275 } 276 277 const MemOp& getMem() const { 278 assert(Kind == KindMem && "Not a Mem operand"); 279 return Mem; 280 } 281 282 // Override MCParsedAsmOperand. 283 SMLoc getStartLoc() const override { return StartLoc; } 284 SMLoc getEndLoc() const override { return EndLoc; } 285 void print(raw_ostream &OS) const override; 286 287 /// getLocRange - Get the range between the first and last token of this 288 /// operand. 289 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); } 290 291 // Used by the TableGen code to add particular types of operand 292 // to an instruction. 293 void addRegOperands(MCInst &Inst, unsigned N) const { 294 assert(N == 1 && "Invalid number of operands"); 295 Inst.addOperand(MCOperand::createReg(getReg())); 296 } 297 void addImmOperands(MCInst &Inst, unsigned N) const { 298 assert(N == 1 && "Invalid number of operands"); 299 addExpr(Inst, getImm()); 300 } 301 void addBDAddrOperands(MCInst &Inst, unsigned N) const { 302 assert(N == 2 && "Invalid number of operands"); 303 assert(isMem(BDMem) && "Invalid operand type"); 304 Inst.addOperand(MCOperand::createReg(Mem.Base)); 305 addExpr(Inst, Mem.Disp); 306 } 307 void addBDXAddrOperands(MCInst &Inst, unsigned N) const { 308 assert(N == 3 && "Invalid number of operands"); 309 assert(isMem(BDXMem) && "Invalid operand type"); 310 Inst.addOperand(MCOperand::createReg(Mem.Base)); 311 addExpr(Inst, Mem.Disp); 312 Inst.addOperand(MCOperand::createReg(Mem.Index)); 313 } 314 void addBDLAddrOperands(MCInst &Inst, unsigned N) const { 315 assert(N == 3 && "Invalid number of operands"); 316 assert(isMem(BDLMem) && "Invalid operand type"); 317 Inst.addOperand(MCOperand::createReg(Mem.Base)); 318 addExpr(Inst, Mem.Disp); 319 addExpr(Inst, Mem.Length.Imm); 320 } 321 void addBDRAddrOperands(MCInst &Inst, unsigned N) const { 322 assert(N == 3 && "Invalid number of operands"); 323 assert(isMem(BDRMem) && "Invalid operand type"); 324 Inst.addOperand(MCOperand::createReg(Mem.Base)); 325 addExpr(Inst, Mem.Disp); 326 Inst.addOperand(MCOperand::createReg(Mem.Length.Reg)); 327 } 328 void addBDVAddrOperands(MCInst &Inst, unsigned N) const { 329 assert(N == 3 && "Invalid number of operands"); 330 assert(isMem(BDVMem) && "Invalid operand type"); 331 Inst.addOperand(MCOperand::createReg(Mem.Base)); 332 addExpr(Inst, Mem.Disp); 333 Inst.addOperand(MCOperand::createReg(Mem.Index)); 334 } 335 void addImmTLSOperands(MCInst &Inst, unsigned N) const { 336 assert(N == 2 && "Invalid number of operands"); 337 assert(Kind == KindImmTLS && "Invalid operand type"); 338 addExpr(Inst, ImmTLS.Imm); 339 if (ImmTLS.Sym) 340 addExpr(Inst, ImmTLS.Sym); 341 } 342 343 // Used by the TableGen code to check for particular operand types. 344 bool isGR32() const { return isReg(GR32Reg); } 345 bool isGRH32() const { return isReg(GRH32Reg); } 346 bool isGRX32() const { return false; } 347 bool isGR64() const { return isReg(GR64Reg); } 348 bool isGR128() const { return isReg(GR128Reg); } 349 bool isADDR32() const { return isReg(GR32Reg); } 350 bool isADDR64() const { return isReg(GR64Reg); } 351 bool isADDR128() const { return false; } 352 bool isFP32() const { return isReg(FP32Reg); } 353 bool isFP64() const { return isReg(FP64Reg); } 354 bool isFP128() const { return isReg(FP128Reg); } 355 bool isVR32() const { return isReg(VR32Reg); } 356 bool isVR64() const { return isReg(VR64Reg); } 357 bool isVF128() const { return false; } 358 bool isVR128() const { return isReg(VR128Reg); } 359 bool isAR32() const { return isReg(AR32Reg); } 360 bool isCR64() const { return isReg(CR64Reg); } 361 bool isAnyReg() const { return (isReg() || isImm(0, 15)); } 362 bool isBDAddr32Disp12() const { return isMemDisp12(BDMem, GR32Reg); } 363 bool isBDAddr32Disp20() const { return isMemDisp20(BDMem, GR32Reg); } 364 bool isBDAddr64Disp12() const { return isMemDisp12(BDMem, GR64Reg); } 365 bool isBDAddr64Disp20() const { return isMemDisp20(BDMem, GR64Reg); } 366 bool isBDXAddr64Disp12() const { return isMemDisp12(BDXMem, GR64Reg); } 367 bool isBDXAddr64Disp20() const { return isMemDisp20(BDXMem, GR64Reg); } 368 bool isBDLAddr64Disp12Len4() const { return isMemDisp12Len4(GR64Reg); } 369 bool isBDLAddr64Disp12Len8() const { return isMemDisp12Len8(GR64Reg); } 370 bool isBDRAddr64Disp12() const { return isMemDisp12(BDRMem, GR64Reg); } 371 bool isBDVAddr64Disp12() const { return isMemDisp12(BDVMem, GR64Reg); } 372 bool isU1Imm() const { return isImm(0, 1); } 373 bool isU2Imm() const { return isImm(0, 3); } 374 bool isU3Imm() const { return isImm(0, 7); } 375 bool isU4Imm() const { return isImm(0, 15); } 376 bool isU6Imm() const { return isImm(0, 63); } 377 bool isU8Imm() const { return isImm(0, 255); } 378 bool isS8Imm() const { return isImm(-128, 127); } 379 bool isU12Imm() const { return isImm(0, 4095); } 380 bool isU16Imm() const { return isImm(0, 65535); } 381 bool isS16Imm() const { return isImm(-32768, 32767); } 382 bool isU32Imm() const { return isImm(0, (1LL << 32) - 1); } 383 bool isS32Imm() const { return isImm(-(1LL << 31), (1LL << 31) - 1); } 384 bool isU48Imm() const { return isImm(0, (1LL << 48) - 1); } 385 }; 386 387 class SystemZAsmParser : public MCTargetAsmParser { 388 #define GET_ASSEMBLER_HEADER 389 #include "SystemZGenAsmMatcher.inc" 390 391 private: 392 MCAsmParser &Parser; 393 enum RegisterGroup { 394 RegGR, 395 RegFP, 396 RegV, 397 RegAR, 398 RegCR 399 }; 400 struct Register { 401 RegisterGroup Group; 402 unsigned Num; 403 SMLoc StartLoc, EndLoc; 404 }; 405 406 bool parseRegister(Register &Reg, bool RestoreOnFailure = false); 407 408 OperandMatchResultTy parseRegister(OperandVector &Operands, 409 RegisterKind Kind); 410 411 OperandMatchResultTy parseAnyRegister(OperandVector &Operands); 412 413 bool parseAddress(bool &HaveReg1, Register &Reg1, 414 bool &HaveReg2, Register &Reg2, 415 const MCExpr *&Disp, const MCExpr *&Length); 416 bool parseAddressRegister(Register &Reg); 417 418 bool ParseDirectiveInsn(SMLoc L); 419 420 OperandMatchResultTy parseAddress(OperandVector &Operands, 421 MemoryKind MemKind, 422 RegisterKind RegKind); 423 424 OperandMatchResultTy parsePCRel(OperandVector &Operands, int64_t MinVal, 425 int64_t MaxVal, bool AllowTLS); 426 427 bool parseOperand(OperandVector &Operands, StringRef Mnemonic); 428 429 public: 430 SystemZAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser, 431 const MCInstrInfo &MII, 432 const MCTargetOptions &Options) 433 : MCTargetAsmParser(Options, sti, MII), Parser(parser) { 434 MCAsmParserExtension::Initialize(Parser); 435 436 // Alias the .word directive to .short. 437 parser.addAliasForDirective(".word", ".short"); 438 439 // Initialize the set of available features. 440 setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits())); 441 } 442 443 // Override MCTargetAsmParser. 444 bool ParseDirective(AsmToken DirectiveID) override; 445 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; 446 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc, 447 bool RestoreOnFailure); 448 OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc, 449 SMLoc &EndLoc) override; 450 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, 451 SMLoc NameLoc, OperandVector &Operands) override; 452 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 453 OperandVector &Operands, MCStreamer &Out, 454 uint64_t &ErrorInfo, 455 bool MatchingInlineAsm) override; 456 457 // Used by the TableGen code to parse particular operand types. 458 OperandMatchResultTy parseGR32(OperandVector &Operands) { 459 return parseRegister(Operands, GR32Reg); 460 } 461 OperandMatchResultTy parseGRH32(OperandVector &Operands) { 462 return parseRegister(Operands, GRH32Reg); 463 } 464 OperandMatchResultTy parseGRX32(OperandVector &Operands) { 465 llvm_unreachable("GRX32 should only be used for pseudo instructions"); 466 } 467 OperandMatchResultTy parseGR64(OperandVector &Operands) { 468 return parseRegister(Operands, GR64Reg); 469 } 470 OperandMatchResultTy parseGR128(OperandVector &Operands) { 471 return parseRegister(Operands, GR128Reg); 472 } 473 OperandMatchResultTy parseADDR32(OperandVector &Operands) { 474 // For the AsmParser, we will accept %r0 for ADDR32 as well. 475 return parseRegister(Operands, GR32Reg); 476 } 477 OperandMatchResultTy parseADDR64(OperandVector &Operands) { 478 // For the AsmParser, we will accept %r0 for ADDR64 as well. 479 return parseRegister(Operands, GR64Reg); 480 } 481 OperandMatchResultTy parseADDR128(OperandVector &Operands) { 482 llvm_unreachable("Shouldn't be used as an operand"); 483 } 484 OperandMatchResultTy parseFP32(OperandVector &Operands) { 485 return parseRegister(Operands, FP32Reg); 486 } 487 OperandMatchResultTy parseFP64(OperandVector &Operands) { 488 return parseRegister(Operands, FP64Reg); 489 } 490 OperandMatchResultTy parseFP128(OperandVector &Operands) { 491 return parseRegister(Operands, FP128Reg); 492 } 493 OperandMatchResultTy parseVR32(OperandVector &Operands) { 494 return parseRegister(Operands, VR32Reg); 495 } 496 OperandMatchResultTy parseVR64(OperandVector &Operands) { 497 return parseRegister(Operands, VR64Reg); 498 } 499 OperandMatchResultTy parseVF128(OperandVector &Operands) { 500 llvm_unreachable("Shouldn't be used as an operand"); 501 } 502 OperandMatchResultTy parseVR128(OperandVector &Operands) { 503 return parseRegister(Operands, VR128Reg); 504 } 505 OperandMatchResultTy parseAR32(OperandVector &Operands) { 506 return parseRegister(Operands, AR32Reg); 507 } 508 OperandMatchResultTy parseCR64(OperandVector &Operands) { 509 return parseRegister(Operands, CR64Reg); 510 } 511 OperandMatchResultTy parseAnyReg(OperandVector &Operands) { 512 return parseAnyRegister(Operands); 513 } 514 OperandMatchResultTy parseBDAddr32(OperandVector &Operands) { 515 return parseAddress(Operands, BDMem, GR32Reg); 516 } 517 OperandMatchResultTy parseBDAddr64(OperandVector &Operands) { 518 return parseAddress(Operands, BDMem, GR64Reg); 519 } 520 OperandMatchResultTy parseBDXAddr64(OperandVector &Operands) { 521 return parseAddress(Operands, BDXMem, GR64Reg); 522 } 523 OperandMatchResultTy parseBDLAddr64(OperandVector &Operands) { 524 return parseAddress(Operands, BDLMem, GR64Reg); 525 } 526 OperandMatchResultTy parseBDRAddr64(OperandVector &Operands) { 527 return parseAddress(Operands, BDRMem, GR64Reg); 528 } 529 OperandMatchResultTy parseBDVAddr64(OperandVector &Operands) { 530 return parseAddress(Operands, BDVMem, GR64Reg); 531 } 532 OperandMatchResultTy parsePCRel12(OperandVector &Operands) { 533 return parsePCRel(Operands, -(1LL << 12), (1LL << 12) - 1, false); 534 } 535 OperandMatchResultTy parsePCRel16(OperandVector &Operands) { 536 return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, false); 537 } 538 OperandMatchResultTy parsePCRel24(OperandVector &Operands) { 539 return parsePCRel(Operands, -(1LL << 24), (1LL << 24) - 1, false); 540 } 541 OperandMatchResultTy parsePCRel32(OperandVector &Operands) { 542 return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, false); 543 } 544 OperandMatchResultTy parsePCRelTLS16(OperandVector &Operands) { 545 return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, true); 546 } 547 OperandMatchResultTy parsePCRelTLS32(OperandVector &Operands) { 548 return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, true); 549 } 550 }; 551 552 } // end anonymous namespace 553 554 #define GET_REGISTER_MATCHER 555 #define GET_SUBTARGET_FEATURE_NAME 556 #define GET_MATCHER_IMPLEMENTATION 557 #define GET_MNEMONIC_SPELL_CHECKER 558 #include "SystemZGenAsmMatcher.inc" 559 560 // Used for the .insn directives; contains information needed to parse the 561 // operands in the directive. 562 struct InsnMatchEntry { 563 StringRef Format; 564 uint64_t Opcode; 565 int32_t NumOperands; 566 MatchClassKind OperandKinds[5]; 567 }; 568 569 // For equal_range comparison. 570 struct CompareInsn { 571 bool operator() (const InsnMatchEntry &LHS, StringRef RHS) { 572 return LHS.Format < RHS; 573 } 574 bool operator() (StringRef LHS, const InsnMatchEntry &RHS) { 575 return LHS < RHS.Format; 576 } 577 bool operator() (const InsnMatchEntry &LHS, const InsnMatchEntry &RHS) { 578 return LHS.Format < RHS.Format; 579 } 580 }; 581 582 // Table initializing information for parsing the .insn directive. 583 static struct InsnMatchEntry InsnMatchTable[] = { 584 /* Format, Opcode, NumOperands, OperandKinds */ 585 { "e", SystemZ::InsnE, 1, 586 { MCK_U16Imm } }, 587 { "ri", SystemZ::InsnRI, 3, 588 { MCK_U32Imm, MCK_AnyReg, MCK_S16Imm } }, 589 { "rie", SystemZ::InsnRIE, 4, 590 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } }, 591 { "ril", SystemZ::InsnRIL, 3, 592 { MCK_U48Imm, MCK_AnyReg, MCK_PCRel32 } }, 593 { "rilu", SystemZ::InsnRILU, 3, 594 { MCK_U48Imm, MCK_AnyReg, MCK_U32Imm } }, 595 { "ris", SystemZ::InsnRIS, 5, 596 { MCK_U48Imm, MCK_AnyReg, MCK_S8Imm, MCK_U4Imm, MCK_BDAddr64Disp12 } }, 597 { "rr", SystemZ::InsnRR, 3, 598 { MCK_U16Imm, MCK_AnyReg, MCK_AnyReg } }, 599 { "rre", SystemZ::InsnRRE, 3, 600 { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg } }, 601 { "rrf", SystemZ::InsnRRF, 5, 602 { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm } }, 603 { "rrs", SystemZ::InsnRRS, 5, 604 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm, MCK_BDAddr64Disp12 } }, 605 { "rs", SystemZ::InsnRS, 4, 606 { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } }, 607 { "rse", SystemZ::InsnRSE, 4, 608 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } }, 609 { "rsi", SystemZ::InsnRSI, 4, 610 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } }, 611 { "rsy", SystemZ::InsnRSY, 4, 612 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp20 } }, 613 { "rx", SystemZ::InsnRX, 3, 614 { MCK_U32Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } }, 615 { "rxe", SystemZ::InsnRXE, 3, 616 { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } }, 617 { "rxf", SystemZ::InsnRXF, 4, 618 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDXAddr64Disp12 } }, 619 { "rxy", SystemZ::InsnRXY, 3, 620 { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp20 } }, 621 { "s", SystemZ::InsnS, 2, 622 { MCK_U32Imm, MCK_BDAddr64Disp12 } }, 623 { "si", SystemZ::InsnSI, 3, 624 { MCK_U32Imm, MCK_BDAddr64Disp12, MCK_S8Imm } }, 625 { "sil", SystemZ::InsnSIL, 3, 626 { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_U16Imm } }, 627 { "siy", SystemZ::InsnSIY, 3, 628 { MCK_U48Imm, MCK_BDAddr64Disp20, MCK_U8Imm } }, 629 { "ss", SystemZ::InsnSS, 4, 630 { MCK_U48Imm, MCK_BDXAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } }, 631 { "sse", SystemZ::InsnSSE, 3, 632 { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12 } }, 633 { "ssf", SystemZ::InsnSSF, 4, 634 { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } } 635 }; 636 637 static void printMCExpr(const MCExpr *E, raw_ostream &OS) { 638 if (!E) 639 return; 640 if (auto *CE = dyn_cast<MCConstantExpr>(E)) 641 OS << *CE; 642 else if (auto *UE = dyn_cast<MCUnaryExpr>(E)) 643 OS << *UE; 644 else if (auto *BE = dyn_cast<MCBinaryExpr>(E)) 645 OS << *BE; 646 else if (auto *SRE = dyn_cast<MCSymbolRefExpr>(E)) 647 OS << *SRE; 648 else 649 OS << *E; 650 } 651 652 void SystemZOperand::print(raw_ostream &OS) const { 653 switch (Kind) { 654 case KindToken: 655 OS << "Token:" << getToken(); 656 break; 657 case KindReg: 658 OS << "Reg:" << SystemZInstPrinter::getRegisterName(getReg()); 659 break; 660 case KindImm: 661 OS << "Imm:"; 662 printMCExpr(getImm(), OS); 663 break; 664 case KindImmTLS: 665 OS << "ImmTLS:"; 666 printMCExpr(getImmTLS().Imm, OS); 667 if (getImmTLS().Sym) { 668 OS << ", "; 669 printMCExpr(getImmTLS().Sym, OS); 670 } 671 break; 672 case KindMem: { 673 const MemOp &Op = getMem(); 674 OS << "Mem:" << *cast<MCConstantExpr>(Op.Disp); 675 if (Op.Base) { 676 OS << "("; 677 if (Op.MemKind == BDLMem) 678 OS << *cast<MCConstantExpr>(Op.Length.Imm) << ","; 679 else if (Op.MemKind == BDRMem) 680 OS << SystemZInstPrinter::getRegisterName(Op.Length.Reg) << ","; 681 if (Op.Index) 682 OS << SystemZInstPrinter::getRegisterName(Op.Index) << ","; 683 OS << SystemZInstPrinter::getRegisterName(Op.Base); 684 OS << ")"; 685 } 686 break; 687 } 688 case KindInvalid: 689 break; 690 } 691 } 692 693 // Parse one register of the form %<prefix><number>. 694 bool SystemZAsmParser::parseRegister(Register &Reg, bool RestoreOnFailure) { 695 Reg.StartLoc = Parser.getTok().getLoc(); 696 697 // Eat the % prefix. 698 if (Parser.getTok().isNot(AsmToken::Percent)) 699 return Error(Parser.getTok().getLoc(), "register expected"); 700 const AsmToken &PercentTok = Parser.getTok(); 701 Parser.Lex(); 702 703 // Expect a register name. 704 if (Parser.getTok().isNot(AsmToken::Identifier)) { 705 if (RestoreOnFailure) 706 getLexer().UnLex(PercentTok); 707 return Error(Reg.StartLoc, "invalid register"); 708 } 709 710 // Check that there's a prefix. 711 StringRef Name = Parser.getTok().getString(); 712 if (Name.size() < 2) { 713 if (RestoreOnFailure) 714 getLexer().UnLex(PercentTok); 715 return Error(Reg.StartLoc, "invalid register"); 716 } 717 char Prefix = Name[0]; 718 719 // Treat the rest of the register name as a register number. 720 if (Name.substr(1).getAsInteger(10, Reg.Num)) { 721 if (RestoreOnFailure) 722 getLexer().UnLex(PercentTok); 723 return Error(Reg.StartLoc, "invalid register"); 724 } 725 726 // Look for valid combinations of prefix and number. 727 if (Prefix == 'r' && Reg.Num < 16) 728 Reg.Group = RegGR; 729 else if (Prefix == 'f' && Reg.Num < 16) 730 Reg.Group = RegFP; 731 else if (Prefix == 'v' && Reg.Num < 32) 732 Reg.Group = RegV; 733 else if (Prefix == 'a' && Reg.Num < 16) 734 Reg.Group = RegAR; 735 else if (Prefix == 'c' && Reg.Num < 16) 736 Reg.Group = RegCR; 737 else { 738 if (RestoreOnFailure) 739 getLexer().UnLex(PercentTok); 740 return Error(Reg.StartLoc, "invalid register"); 741 } 742 743 Reg.EndLoc = Parser.getTok().getLoc(); 744 Parser.Lex(); 745 return false; 746 } 747 748 // Parse a register of kind Kind and add it to Operands. 749 OperandMatchResultTy 750 SystemZAsmParser::parseRegister(OperandVector &Operands, RegisterKind Kind) { 751 if (Parser.getTok().isNot(AsmToken::Percent)) 752 return MatchOperand_NoMatch; 753 754 Register Reg; 755 if (parseRegister(Reg)) 756 return MatchOperand_ParseFail; 757 758 // Verify that a register prefix appropriate for Kind was used. 759 bool PrefixMatch; 760 switch (Kind) { 761 case GR32Reg: 762 case GRH32Reg: 763 case GR64Reg: 764 case GR128Reg: 765 PrefixMatch = Reg.Group == RegGR; 766 break; 767 case FP32Reg: 768 case FP64Reg: 769 case FP128Reg: 770 PrefixMatch = Reg.Group == RegFP; 771 break; 772 case VR32Reg: 773 case VR64Reg: 774 case VR128Reg: 775 // It is OK to use the %f prefix with vector instructions that 776 // expect some VR..Reg kind, so accept the RegFP group as well. 777 PrefixMatch = Reg.Group == RegV || Reg.Group == RegFP; 778 break; 779 case AR32Reg: 780 PrefixMatch = Reg.Group == RegAR; 781 break; 782 case CR64Reg: 783 PrefixMatch = Reg.Group == RegCR; 784 break; 785 } 786 if (!PrefixMatch) { 787 Error(Reg.StartLoc, "invalid operand for instruction"); 788 return MatchOperand_ParseFail; 789 } 790 791 // Determine the LLVM register number according to Kind. 792 const unsigned *Regs; 793 switch (Kind) { 794 case GR32Reg: Regs = SystemZMC::GR32Regs; break; 795 case GRH32Reg: Regs = SystemZMC::GRH32Regs; break; 796 case GR64Reg: Regs = SystemZMC::GR64Regs; break; 797 case GR128Reg: Regs = SystemZMC::GR128Regs; break; 798 case FP32Reg: Regs = SystemZMC::FP32Regs; break; 799 case FP64Reg: Regs = SystemZMC::FP64Regs; break; 800 case FP128Reg: Regs = SystemZMC::FP128Regs; break; 801 case VR32Reg: Regs = SystemZMC::VR32Regs; break; 802 case VR64Reg: Regs = SystemZMC::VR64Regs; break; 803 case VR128Reg: Regs = SystemZMC::VR128Regs; break; 804 case AR32Reg: Regs = SystemZMC::AR32Regs; break; 805 case CR64Reg: Regs = SystemZMC::CR64Regs; break; 806 } 807 if (Regs[Reg.Num] == 0) { 808 Error(Reg.StartLoc, "invalid register pair"); 809 return MatchOperand_ParseFail; 810 } 811 812 Operands.push_back(SystemZOperand::createReg(Kind, Regs[Reg.Num], 813 Reg.StartLoc, Reg.EndLoc)); 814 return MatchOperand_Success; 815 } 816 817 // Parse any type of register (including integers) and add it to Operands. 818 OperandMatchResultTy 819 SystemZAsmParser::parseAnyRegister(OperandVector &Operands) { 820 // Handle integer values. 821 if (Parser.getTok().is(AsmToken::Integer)) { 822 const MCExpr *Register; 823 SMLoc StartLoc = Parser.getTok().getLoc(); 824 if (Parser.parseExpression(Register)) 825 return MatchOperand_ParseFail; 826 827 if (auto *CE = dyn_cast<MCConstantExpr>(Register)) { 828 int64_t Value = CE->getValue(); 829 if (Value < 0 || Value > 15) { 830 Error(StartLoc, "invalid register"); 831 return MatchOperand_ParseFail; 832 } 833 } 834 835 SMLoc EndLoc = 836 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 837 838 Operands.push_back(SystemZOperand::createImm(Register, StartLoc, EndLoc)); 839 } 840 else { 841 Register Reg; 842 if (parseRegister(Reg)) 843 return MatchOperand_ParseFail; 844 845 // Map to the correct register kind. 846 RegisterKind Kind; 847 unsigned RegNo; 848 if (Reg.Group == RegGR) { 849 Kind = GR64Reg; 850 RegNo = SystemZMC::GR64Regs[Reg.Num]; 851 } 852 else if (Reg.Group == RegFP) { 853 Kind = FP64Reg; 854 RegNo = SystemZMC::FP64Regs[Reg.Num]; 855 } 856 else if (Reg.Group == RegV) { 857 Kind = VR128Reg; 858 RegNo = SystemZMC::VR128Regs[Reg.Num]; 859 } 860 else if (Reg.Group == RegAR) { 861 Kind = AR32Reg; 862 RegNo = SystemZMC::AR32Regs[Reg.Num]; 863 } 864 else if (Reg.Group == RegCR) { 865 Kind = CR64Reg; 866 RegNo = SystemZMC::CR64Regs[Reg.Num]; 867 } 868 else { 869 return MatchOperand_ParseFail; 870 } 871 872 Operands.push_back(SystemZOperand::createReg(Kind, RegNo, 873 Reg.StartLoc, Reg.EndLoc)); 874 } 875 return MatchOperand_Success; 876 } 877 878 // Parse a memory operand into Reg1, Reg2, Disp, and Length. 879 bool SystemZAsmParser::parseAddress(bool &HaveReg1, Register &Reg1, 880 bool &HaveReg2, Register &Reg2, 881 const MCExpr *&Disp, 882 const MCExpr *&Length) { 883 // Parse the displacement, which must always be present. 884 if (getParser().parseExpression(Disp)) 885 return true; 886 887 // Parse the optional base and index. 888 HaveReg1 = false; 889 HaveReg2 = false; 890 Length = nullptr; 891 if (getLexer().is(AsmToken::LParen)) { 892 Parser.Lex(); 893 894 if (getLexer().is(AsmToken::Percent)) { 895 // Parse the first register. 896 HaveReg1 = true; 897 if (parseRegister(Reg1)) 898 return true; 899 } else { 900 // Parse the length. 901 if (getParser().parseExpression(Length)) 902 return true; 903 } 904 905 // Check whether there's a second register. 906 if (getLexer().is(AsmToken::Comma)) { 907 Parser.Lex(); 908 HaveReg2 = true; 909 if (parseRegister(Reg2)) 910 return true; 911 } 912 913 // Consume the closing bracket. 914 if (getLexer().isNot(AsmToken::RParen)) 915 return Error(Parser.getTok().getLoc(), "unexpected token in address"); 916 Parser.Lex(); 917 } 918 return false; 919 } 920 921 // Verify that Reg is a valid address register (base or index). 922 bool 923 SystemZAsmParser::parseAddressRegister(Register &Reg) { 924 if (Reg.Group == RegV) { 925 Error(Reg.StartLoc, "invalid use of vector addressing"); 926 return true; 927 } else if (Reg.Group != RegGR) { 928 Error(Reg.StartLoc, "invalid address register"); 929 return true; 930 } 931 return false; 932 } 933 934 // Parse a memory operand and add it to Operands. The other arguments 935 // are as above. 936 OperandMatchResultTy 937 SystemZAsmParser::parseAddress(OperandVector &Operands, MemoryKind MemKind, 938 RegisterKind RegKind) { 939 SMLoc StartLoc = Parser.getTok().getLoc(); 940 unsigned Base = 0, Index = 0, LengthReg = 0; 941 Register Reg1, Reg2; 942 bool HaveReg1, HaveReg2; 943 const MCExpr *Disp; 944 const MCExpr *Length; 945 if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length)) 946 return MatchOperand_ParseFail; 947 948 const unsigned *Regs; 949 switch (RegKind) { 950 case GR32Reg: Regs = SystemZMC::GR32Regs; break; 951 case GR64Reg: Regs = SystemZMC::GR64Regs; break; 952 default: llvm_unreachable("invalid RegKind"); 953 } 954 955 switch (MemKind) { 956 case BDMem: 957 // If we have Reg1, it must be an address register. 958 if (HaveReg1) { 959 if (parseAddressRegister(Reg1)) 960 return MatchOperand_ParseFail; 961 Base = Regs[Reg1.Num]; 962 } 963 // There must be no Reg2 or length. 964 if (Length) { 965 Error(StartLoc, "invalid use of length addressing"); 966 return MatchOperand_ParseFail; 967 } 968 if (HaveReg2) { 969 Error(StartLoc, "invalid use of indexed addressing"); 970 return MatchOperand_ParseFail; 971 } 972 break; 973 case BDXMem: 974 // If we have Reg1, it must be an address register. 975 if (HaveReg1) { 976 if (parseAddressRegister(Reg1)) 977 return MatchOperand_ParseFail; 978 // If the are two registers, the first one is the index and the 979 // second is the base. 980 if (HaveReg2) 981 Index = Regs[Reg1.Num]; 982 else 983 Base = Regs[Reg1.Num]; 984 } 985 // If we have Reg2, it must be an address register. 986 if (HaveReg2) { 987 if (parseAddressRegister(Reg2)) 988 return MatchOperand_ParseFail; 989 Base = Regs[Reg2.Num]; 990 } 991 // There must be no length. 992 if (Length) { 993 Error(StartLoc, "invalid use of length addressing"); 994 return MatchOperand_ParseFail; 995 } 996 break; 997 case BDLMem: 998 // If we have Reg2, it must be an address register. 999 if (HaveReg2) { 1000 if (parseAddressRegister(Reg2)) 1001 return MatchOperand_ParseFail; 1002 Base = Regs[Reg2.Num]; 1003 } 1004 // We cannot support base+index addressing. 1005 if (HaveReg1 && HaveReg2) { 1006 Error(StartLoc, "invalid use of indexed addressing"); 1007 return MatchOperand_ParseFail; 1008 } 1009 // We must have a length. 1010 if (!Length) { 1011 Error(StartLoc, "missing length in address"); 1012 return MatchOperand_ParseFail; 1013 } 1014 break; 1015 case BDRMem: 1016 // We must have Reg1, and it must be a GPR. 1017 if (!HaveReg1 || Reg1.Group != RegGR) { 1018 Error(StartLoc, "invalid operand for instruction"); 1019 return MatchOperand_ParseFail; 1020 } 1021 LengthReg = SystemZMC::GR64Regs[Reg1.Num]; 1022 // If we have Reg2, it must be an address register. 1023 if (HaveReg2) { 1024 if (parseAddressRegister(Reg2)) 1025 return MatchOperand_ParseFail; 1026 Base = Regs[Reg2.Num]; 1027 } 1028 // There must be no length. 1029 if (Length) { 1030 Error(StartLoc, "invalid use of length addressing"); 1031 return MatchOperand_ParseFail; 1032 } 1033 break; 1034 case BDVMem: 1035 // We must have Reg1, and it must be a vector register. 1036 if (!HaveReg1 || Reg1.Group != RegV) { 1037 Error(StartLoc, "vector index required in address"); 1038 return MatchOperand_ParseFail; 1039 } 1040 Index = SystemZMC::VR128Regs[Reg1.Num]; 1041 // If we have Reg2, it must be an address register. 1042 if (HaveReg2) { 1043 if (parseAddressRegister(Reg2)) 1044 return MatchOperand_ParseFail; 1045 Base = Regs[Reg2.Num]; 1046 } 1047 // There must be no length. 1048 if (Length) { 1049 Error(StartLoc, "invalid use of length addressing"); 1050 return MatchOperand_ParseFail; 1051 } 1052 break; 1053 } 1054 1055 SMLoc EndLoc = 1056 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 1057 Operands.push_back(SystemZOperand::createMem(MemKind, RegKind, Base, Disp, 1058 Index, Length, LengthReg, 1059 StartLoc, EndLoc)); 1060 return MatchOperand_Success; 1061 } 1062 1063 bool SystemZAsmParser::ParseDirective(AsmToken DirectiveID) { 1064 StringRef IDVal = DirectiveID.getIdentifier(); 1065 1066 if (IDVal == ".insn") 1067 return ParseDirectiveInsn(DirectiveID.getLoc()); 1068 1069 return true; 1070 } 1071 1072 /// ParseDirectiveInsn 1073 /// ::= .insn [ format, encoding, (operands (, operands)*) ] 1074 bool SystemZAsmParser::ParseDirectiveInsn(SMLoc L) { 1075 MCAsmParser &Parser = getParser(); 1076 1077 // Expect instruction format as identifier. 1078 StringRef Format; 1079 SMLoc ErrorLoc = Parser.getTok().getLoc(); 1080 if (Parser.parseIdentifier(Format)) 1081 return Error(ErrorLoc, "expected instruction format"); 1082 1083 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 8> Operands; 1084 1085 // Find entry for this format in InsnMatchTable. 1086 auto EntryRange = 1087 std::equal_range(std::begin(InsnMatchTable), std::end(InsnMatchTable), 1088 Format, CompareInsn()); 1089 1090 // If first == second, couldn't find a match in the table. 1091 if (EntryRange.first == EntryRange.second) 1092 return Error(ErrorLoc, "unrecognized format"); 1093 1094 struct InsnMatchEntry *Entry = EntryRange.first; 1095 1096 // Format should match from equal_range. 1097 assert(Entry->Format == Format); 1098 1099 // Parse the following operands using the table's information. 1100 for (int i = 0; i < Entry->NumOperands; i++) { 1101 MatchClassKind Kind = Entry->OperandKinds[i]; 1102 1103 SMLoc StartLoc = Parser.getTok().getLoc(); 1104 1105 // Always expect commas as separators for operands. 1106 if (getLexer().isNot(AsmToken::Comma)) 1107 return Error(StartLoc, "unexpected token in directive"); 1108 Lex(); 1109 1110 // Parse operands. 1111 OperandMatchResultTy ResTy; 1112 if (Kind == MCK_AnyReg) 1113 ResTy = parseAnyReg(Operands); 1114 else if (Kind == MCK_BDXAddr64Disp12 || Kind == MCK_BDXAddr64Disp20) 1115 ResTy = parseBDXAddr64(Operands); 1116 else if (Kind == MCK_BDAddr64Disp12 || Kind == MCK_BDAddr64Disp20) 1117 ResTy = parseBDAddr64(Operands); 1118 else if (Kind == MCK_PCRel32) 1119 ResTy = parsePCRel32(Operands); 1120 else if (Kind == MCK_PCRel16) 1121 ResTy = parsePCRel16(Operands); 1122 else { 1123 // Only remaining operand kind is an immediate. 1124 const MCExpr *Expr; 1125 SMLoc StartLoc = Parser.getTok().getLoc(); 1126 1127 // Expect immediate expression. 1128 if (Parser.parseExpression(Expr)) 1129 return Error(StartLoc, "unexpected token in directive"); 1130 1131 SMLoc EndLoc = 1132 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 1133 1134 Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc)); 1135 ResTy = MatchOperand_Success; 1136 } 1137 1138 if (ResTy != MatchOperand_Success) 1139 return true; 1140 } 1141 1142 // Build the instruction with the parsed operands. 1143 MCInst Inst = MCInstBuilder(Entry->Opcode); 1144 1145 for (size_t i = 0; i < Operands.size(); i++) { 1146 MCParsedAsmOperand &Operand = *Operands[i]; 1147 MatchClassKind Kind = Entry->OperandKinds[i]; 1148 1149 // Verify operand. 1150 unsigned Res = validateOperandClass(Operand, Kind); 1151 if (Res != Match_Success) 1152 return Error(Operand.getStartLoc(), "unexpected operand type"); 1153 1154 // Add operands to instruction. 1155 SystemZOperand &ZOperand = static_cast<SystemZOperand &>(Operand); 1156 if (ZOperand.isReg()) 1157 ZOperand.addRegOperands(Inst, 1); 1158 else if (ZOperand.isMem(BDMem)) 1159 ZOperand.addBDAddrOperands(Inst, 2); 1160 else if (ZOperand.isMem(BDXMem)) 1161 ZOperand.addBDXAddrOperands(Inst, 3); 1162 else if (ZOperand.isImm()) 1163 ZOperand.addImmOperands(Inst, 1); 1164 else 1165 llvm_unreachable("unexpected operand type"); 1166 } 1167 1168 // Emit as a regular instruction. 1169 Parser.getStreamer().emitInstruction(Inst, getSTI()); 1170 1171 return false; 1172 } 1173 1174 bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, 1175 SMLoc &EndLoc, bool RestoreOnFailure) { 1176 Register Reg; 1177 if (parseRegister(Reg, RestoreOnFailure)) 1178 return true; 1179 if (Reg.Group == RegGR) 1180 RegNo = SystemZMC::GR64Regs[Reg.Num]; 1181 else if (Reg.Group == RegFP) 1182 RegNo = SystemZMC::FP64Regs[Reg.Num]; 1183 else if (Reg.Group == RegV) 1184 RegNo = SystemZMC::VR128Regs[Reg.Num]; 1185 else if (Reg.Group == RegAR) 1186 RegNo = SystemZMC::AR32Regs[Reg.Num]; 1187 else if (Reg.Group == RegCR) 1188 RegNo = SystemZMC::CR64Regs[Reg.Num]; 1189 StartLoc = Reg.StartLoc; 1190 EndLoc = Reg.EndLoc; 1191 return false; 1192 } 1193 1194 bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, 1195 SMLoc &EndLoc) { 1196 return ParseRegister(RegNo, StartLoc, EndLoc, /*RestoreOnFailure=*/false); 1197 } 1198 1199 OperandMatchResultTy SystemZAsmParser::tryParseRegister(unsigned &RegNo, 1200 SMLoc &StartLoc, 1201 SMLoc &EndLoc) { 1202 bool Result = 1203 ParseRegister(RegNo, StartLoc, EndLoc, /*RestoreOnFailure=*/true); 1204 bool PendingErrors = getParser().hasPendingError(); 1205 getParser().clearPendingErrors(); 1206 if (PendingErrors) 1207 return MatchOperand_ParseFail; 1208 if (Result) 1209 return MatchOperand_NoMatch; 1210 return MatchOperand_Success; 1211 } 1212 1213 bool SystemZAsmParser::ParseInstruction(ParseInstructionInfo &Info, 1214 StringRef Name, SMLoc NameLoc, 1215 OperandVector &Operands) { 1216 Operands.push_back(SystemZOperand::createToken(Name, NameLoc)); 1217 1218 // Read the remaining operands. 1219 if (getLexer().isNot(AsmToken::EndOfStatement)) { 1220 // Read the first operand. 1221 if (parseOperand(Operands, Name)) { 1222 return true; 1223 } 1224 1225 // Read any subsequent operands. 1226 while (getLexer().is(AsmToken::Comma)) { 1227 Parser.Lex(); 1228 if (parseOperand(Operands, Name)) { 1229 return true; 1230 } 1231 } 1232 if (getLexer().isNot(AsmToken::EndOfStatement)) { 1233 SMLoc Loc = getLexer().getLoc(); 1234 return Error(Loc, "unexpected token in argument list"); 1235 } 1236 } 1237 1238 // Consume the EndOfStatement. 1239 Parser.Lex(); 1240 return false; 1241 } 1242 1243 bool SystemZAsmParser::parseOperand(OperandVector &Operands, 1244 StringRef Mnemonic) { 1245 // Check if the current operand has a custom associated parser, if so, try to 1246 // custom parse the operand, or fallback to the general approach. Force all 1247 // features to be available during the operand check, or else we will fail to 1248 // find the custom parser, and then we will later get an InvalidOperand error 1249 // instead of a MissingFeature errror. 1250 FeatureBitset AvailableFeatures = getAvailableFeatures(); 1251 FeatureBitset All; 1252 All.set(); 1253 setAvailableFeatures(All); 1254 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic); 1255 setAvailableFeatures(AvailableFeatures); 1256 if (ResTy == MatchOperand_Success) 1257 return false; 1258 1259 // If there wasn't a custom match, try the generic matcher below. Otherwise, 1260 // there was a match, but an error occurred, in which case, just return that 1261 // the operand parsing failed. 1262 if (ResTy == MatchOperand_ParseFail) 1263 return true; 1264 1265 // Check for a register. All real register operands should have used 1266 // a context-dependent parse routine, which gives the required register 1267 // class. The code is here to mop up other cases, like those where 1268 // the instruction isn't recognized. 1269 if (Parser.getTok().is(AsmToken::Percent)) { 1270 Register Reg; 1271 if (parseRegister(Reg)) 1272 return true; 1273 Operands.push_back(SystemZOperand::createInvalid(Reg.StartLoc, Reg.EndLoc)); 1274 return false; 1275 } 1276 1277 // The only other type of operand is an immediate or address. As above, 1278 // real address operands should have used a context-dependent parse routine, 1279 // so we treat any plain expression as an immediate. 1280 SMLoc StartLoc = Parser.getTok().getLoc(); 1281 Register Reg1, Reg2; 1282 bool HaveReg1, HaveReg2; 1283 const MCExpr *Expr; 1284 const MCExpr *Length; 1285 if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Expr, Length)) 1286 return true; 1287 // If the register combination is not valid for any instruction, reject it. 1288 // Otherwise, fall back to reporting an unrecognized instruction. 1289 if (HaveReg1 && Reg1.Group != RegGR && Reg1.Group != RegV 1290 && parseAddressRegister(Reg1)) 1291 return true; 1292 if (HaveReg2 && parseAddressRegister(Reg2)) 1293 return true; 1294 1295 SMLoc EndLoc = 1296 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 1297 if (HaveReg1 || HaveReg2 || Length) 1298 Operands.push_back(SystemZOperand::createInvalid(StartLoc, EndLoc)); 1299 else 1300 Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc)); 1301 return false; 1302 } 1303 1304 static std::string SystemZMnemonicSpellCheck(StringRef S, 1305 const FeatureBitset &FBS, 1306 unsigned VariantID = 0); 1307 1308 bool SystemZAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 1309 OperandVector &Operands, 1310 MCStreamer &Out, 1311 uint64_t &ErrorInfo, 1312 bool MatchingInlineAsm) { 1313 MCInst Inst; 1314 unsigned MatchResult; 1315 1316 FeatureBitset MissingFeatures; 1317 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo, 1318 MissingFeatures, MatchingInlineAsm); 1319 switch (MatchResult) { 1320 case Match_Success: 1321 Inst.setLoc(IDLoc); 1322 Out.emitInstruction(Inst, getSTI()); 1323 return false; 1324 1325 case Match_MissingFeature: { 1326 assert(MissingFeatures.any() && "Unknown missing feature!"); 1327 // Special case the error message for the very common case where only 1328 // a single subtarget feature is missing 1329 std::string Msg = "instruction requires:"; 1330 for (unsigned I = 0, E = MissingFeatures.size(); I != E; ++I) { 1331 if (MissingFeatures[I]) { 1332 Msg += " "; 1333 Msg += getSubtargetFeatureName(I); 1334 } 1335 } 1336 return Error(IDLoc, Msg); 1337 } 1338 1339 case Match_InvalidOperand: { 1340 SMLoc ErrorLoc = IDLoc; 1341 if (ErrorInfo != ~0ULL) { 1342 if (ErrorInfo >= Operands.size()) 1343 return Error(IDLoc, "too few operands for instruction"); 1344 1345 ErrorLoc = ((SystemZOperand &)*Operands[ErrorInfo]).getStartLoc(); 1346 if (ErrorLoc == SMLoc()) 1347 ErrorLoc = IDLoc; 1348 } 1349 return Error(ErrorLoc, "invalid operand for instruction"); 1350 } 1351 1352 case Match_MnemonicFail: { 1353 FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits()); 1354 std::string Suggestion = SystemZMnemonicSpellCheck( 1355 ((SystemZOperand &)*Operands[0]).getToken(), FBS); 1356 return Error(IDLoc, "invalid instruction" + Suggestion, 1357 ((SystemZOperand &)*Operands[0]).getLocRange()); 1358 } 1359 } 1360 1361 llvm_unreachable("Unexpected match type"); 1362 } 1363 1364 OperandMatchResultTy 1365 SystemZAsmParser::parsePCRel(OperandVector &Operands, int64_t MinVal, 1366 int64_t MaxVal, bool AllowTLS) { 1367 MCContext &Ctx = getContext(); 1368 MCStreamer &Out = getStreamer(); 1369 const MCExpr *Expr; 1370 SMLoc StartLoc = Parser.getTok().getLoc(); 1371 if (getParser().parseExpression(Expr)) 1372 return MatchOperand_NoMatch; 1373 1374 auto isOutOfRangeConstant = [&](const MCExpr *E) -> bool { 1375 if (auto *CE = dyn_cast<MCConstantExpr>(E)) { 1376 int64_t Value = CE->getValue(); 1377 if ((Value & 1) || Value < MinVal || Value > MaxVal) 1378 return true; 1379 } 1380 return false; 1381 }; 1382 1383 // For consistency with the GNU assembler, treat immediates as offsets 1384 // from ".". 1385 if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) { 1386 if (isOutOfRangeConstant(CE)) { 1387 Error(StartLoc, "offset out of range"); 1388 return MatchOperand_ParseFail; 1389 } 1390 int64_t Value = CE->getValue(); 1391 MCSymbol *Sym = Ctx.createTempSymbol(); 1392 Out.emitLabel(Sym); 1393 const MCExpr *Base = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, 1394 Ctx); 1395 Expr = Value == 0 ? Base : MCBinaryExpr::createAdd(Base, Expr, Ctx); 1396 } 1397 1398 // For consistency with the GNU assembler, conservatively assume that a 1399 // constant offset must by itself be within the given size range. 1400 if (const auto *BE = dyn_cast<MCBinaryExpr>(Expr)) 1401 if (isOutOfRangeConstant(BE->getLHS()) || 1402 isOutOfRangeConstant(BE->getRHS())) { 1403 Error(StartLoc, "offset out of range"); 1404 return MatchOperand_ParseFail; 1405 } 1406 1407 // Optionally match :tls_gdcall: or :tls_ldcall: followed by a TLS symbol. 1408 const MCExpr *Sym = nullptr; 1409 if (AllowTLS && getLexer().is(AsmToken::Colon)) { 1410 Parser.Lex(); 1411 1412 if (Parser.getTok().isNot(AsmToken::Identifier)) { 1413 Error(Parser.getTok().getLoc(), "unexpected token"); 1414 return MatchOperand_ParseFail; 1415 } 1416 1417 MCSymbolRefExpr::VariantKind Kind = MCSymbolRefExpr::VK_None; 1418 StringRef Name = Parser.getTok().getString(); 1419 if (Name == "tls_gdcall") 1420 Kind = MCSymbolRefExpr::VK_TLSGD; 1421 else if (Name == "tls_ldcall") 1422 Kind = MCSymbolRefExpr::VK_TLSLDM; 1423 else { 1424 Error(Parser.getTok().getLoc(), "unknown TLS tag"); 1425 return MatchOperand_ParseFail; 1426 } 1427 Parser.Lex(); 1428 1429 if (Parser.getTok().isNot(AsmToken::Colon)) { 1430 Error(Parser.getTok().getLoc(), "unexpected token"); 1431 return MatchOperand_ParseFail; 1432 } 1433 Parser.Lex(); 1434 1435 if (Parser.getTok().isNot(AsmToken::Identifier)) { 1436 Error(Parser.getTok().getLoc(), "unexpected token"); 1437 return MatchOperand_ParseFail; 1438 } 1439 1440 StringRef Identifier = Parser.getTok().getString(); 1441 Sym = MCSymbolRefExpr::create(Ctx.getOrCreateSymbol(Identifier), 1442 Kind, Ctx); 1443 Parser.Lex(); 1444 } 1445 1446 SMLoc EndLoc = 1447 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 1448 1449 if (AllowTLS) 1450 Operands.push_back(SystemZOperand::createImmTLS(Expr, Sym, 1451 StartLoc, EndLoc)); 1452 else 1453 Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc)); 1454 1455 return MatchOperand_Success; 1456 } 1457 1458 // Force static initialization. 1459 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSystemZAsmParser() { 1460 RegisterMCAsmParser<SystemZAsmParser> X(getTheSystemZTarget()); 1461 } 1462