1 //===- SparcDisassembler.cpp - Disassembler for Sparc -----------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the Sparc Disassembler. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "Sparc.h" 15 #include "SparcRegisterInfo.h" 16 #include "SparcSubtarget.h" 17 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 18 #include "llvm/MC/MCFixedLenDisassembler.h" 19 #include "llvm/MC/MCInst.h" 20 #include "llvm/MC/MCContext.h" 21 #include "llvm/MC/MCAsmInfo.h" 22 #include "llvm/Support/TargetRegistry.h" 23 24 using namespace llvm; 25 26 #define DEBUG_TYPE "sparc-disassembler" 27 28 typedef MCDisassembler::DecodeStatus DecodeStatus; 29 30 namespace { 31 32 /// A disassembler class for Sparc. 33 class SparcDisassembler : public MCDisassembler { 34 public: 35 SparcDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) 36 : MCDisassembler(STI, Ctx) {} 37 virtual ~SparcDisassembler() {} 38 39 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 40 ArrayRef<uint8_t> Bytes, uint64_t Address, 41 raw_ostream &VStream, 42 raw_ostream &CStream) const override; 43 }; 44 } 45 46 namespace llvm { 47 extern Target TheSparcTarget, TheSparcV9Target, TheSparcelTarget; 48 } 49 50 static MCDisassembler *createSparcDisassembler(const Target &T, 51 const MCSubtargetInfo &STI, 52 MCContext &Ctx) { 53 return new SparcDisassembler(STI, Ctx); 54 } 55 56 57 extern "C" void LLVMInitializeSparcDisassembler() { 58 // Register the disassembler. 59 TargetRegistry::RegisterMCDisassembler(TheSparcTarget, 60 createSparcDisassembler); 61 TargetRegistry::RegisterMCDisassembler(TheSparcV9Target, 62 createSparcDisassembler); 63 TargetRegistry::RegisterMCDisassembler(TheSparcelTarget, 64 createSparcDisassembler); 65 } 66 67 static const unsigned IntRegDecoderTable[] = { 68 SP::G0, SP::G1, SP::G2, SP::G3, 69 SP::G4, SP::G5, SP::G6, SP::G7, 70 SP::O0, SP::O1, SP::O2, SP::O3, 71 SP::O4, SP::O5, SP::O6, SP::O7, 72 SP::L0, SP::L1, SP::L2, SP::L3, 73 SP::L4, SP::L5, SP::L6, SP::L7, 74 SP::I0, SP::I1, SP::I2, SP::I3, 75 SP::I4, SP::I5, SP::I6, SP::I7 }; 76 77 static const unsigned FPRegDecoderTable[] = { 78 SP::F0, SP::F1, SP::F2, SP::F3, 79 SP::F4, SP::F5, SP::F6, SP::F7, 80 SP::F8, SP::F9, SP::F10, SP::F11, 81 SP::F12, SP::F13, SP::F14, SP::F15, 82 SP::F16, SP::F17, SP::F18, SP::F19, 83 SP::F20, SP::F21, SP::F22, SP::F23, 84 SP::F24, SP::F25, SP::F26, SP::F27, 85 SP::F28, SP::F29, SP::F30, SP::F31 }; 86 87 static const unsigned DFPRegDecoderTable[] = { 88 SP::D0, SP::D16, SP::D1, SP::D17, 89 SP::D2, SP::D18, SP::D3, SP::D19, 90 SP::D4, SP::D20, SP::D5, SP::D21, 91 SP::D6, SP::D22, SP::D7, SP::D23, 92 SP::D8, SP::D24, SP::D9, SP::D25, 93 SP::D10, SP::D26, SP::D11, SP::D27, 94 SP::D12, SP::D28, SP::D13, SP::D29, 95 SP::D14, SP::D30, SP::D15, SP::D31 }; 96 97 static const unsigned QFPRegDecoderTable[] = { 98 SP::Q0, SP::Q8, ~0U, ~0U, 99 SP::Q1, SP::Q9, ~0U, ~0U, 100 SP::Q2, SP::Q10, ~0U, ~0U, 101 SP::Q3, SP::Q11, ~0U, ~0U, 102 SP::Q4, SP::Q12, ~0U, ~0U, 103 SP::Q5, SP::Q13, ~0U, ~0U, 104 SP::Q6, SP::Q14, ~0U, ~0U, 105 SP::Q7, SP::Q15, ~0U, ~0U } ; 106 107 static const unsigned FCCRegDecoderTable[] = { 108 SP::FCC0, SP::FCC1, SP::FCC2, SP::FCC3 }; 109 110 static const unsigned ASRRegDecoderTable[] = { 111 SP::Y, SP::ASR1, SP::ASR2, SP::ASR3, 112 SP::ASR4, SP::ASR5, SP::ASR6, SP::ASR7, 113 SP::ASR8, SP::ASR9, SP::ASR10, SP::ASR11, 114 SP::ASR12, SP::ASR13, SP::ASR14, SP::ASR15, 115 SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19, 116 SP::ASR20, SP::ASR21, SP::ASR22, SP::ASR23, 117 SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27, 118 SP::ASR28, SP::ASR29, SP::ASR30, SP::ASR31}; 119 120 static const unsigned PRRegDecoderTable[] = { 121 SP::TPC, SP::TNPC, SP::TSTATE, SP::TT, SP::TICK, SP::TBA, SP::PSTATE, 122 SP::TL, SP::PIL, SP::CWP, SP::CANSAVE, SP::CANRESTORE, SP::CLEANWIN, 123 SP::OTHERWIN, SP::WSTATE 124 }; 125 126 static const uint16_t IntPairDecoderTable[] = { 127 SP::G0_G1, SP::G2_G3, SP::G4_G5, SP::G6_G7, 128 SP::O0_O1, SP::O2_O3, SP::O4_O5, SP::O6_O7, 129 SP::L0_L1, SP::L2_L3, SP::L4_L5, SP::L6_L7, 130 SP::I0_I1, SP::I2_I3, SP::I4_I5, SP::I6_I7, 131 }; 132 133 static const unsigned CPRegDecoderTable[] = { 134 SP::C0, SP::C1, SP::C2, SP::C3, 135 SP::C4, SP::C5, SP::C6, SP::C7, 136 SP::C8, SP::C9, SP::C10, SP::C11, 137 SP::C12, SP::C13, SP::C14, SP::C15, 138 SP::C16, SP::C17, SP::C18, SP::C19, 139 SP::C20, SP::C21, SP::C22, SP::C23, 140 SP::C24, SP::C25, SP::C26, SP::C27, 141 SP::C28, SP::C29, SP::C30, SP::C31 142 }; 143 144 145 static const uint16_t CPPairDecoderTable[] = { 146 SP::C0_C1, SP::C2_C3, SP::C4_C5, SP::C6_C7, 147 SP::C8_C9, SP::C10_C11, SP::C12_C13, SP::C14_C15, 148 SP::C16_C17, SP::C18_C19, SP::C20_C21, SP::C22_C23, 149 SP::C24_C25, SP::C26_C27, SP::C28_C29, SP::C30_C31 150 }; 151 152 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, 153 unsigned RegNo, 154 uint64_t Address, 155 const void *Decoder) { 156 if (RegNo > 31) 157 return MCDisassembler::Fail; 158 unsigned Reg = IntRegDecoderTable[RegNo]; 159 Inst.addOperand(MCOperand::createReg(Reg)); 160 return MCDisassembler::Success; 161 } 162 163 static DecodeStatus DecodeI64RegsRegisterClass(MCInst &Inst, 164 unsigned RegNo, 165 uint64_t Address, 166 const void *Decoder) { 167 if (RegNo > 31) 168 return MCDisassembler::Fail; 169 unsigned Reg = IntRegDecoderTable[RegNo]; 170 Inst.addOperand(MCOperand::createReg(Reg)); 171 return MCDisassembler::Success; 172 } 173 174 175 static DecodeStatus DecodeFPRegsRegisterClass(MCInst &Inst, 176 unsigned RegNo, 177 uint64_t Address, 178 const void *Decoder) { 179 if (RegNo > 31) 180 return MCDisassembler::Fail; 181 unsigned Reg = FPRegDecoderTable[RegNo]; 182 Inst.addOperand(MCOperand::createReg(Reg)); 183 return MCDisassembler::Success; 184 } 185 186 187 static DecodeStatus DecodeDFPRegsRegisterClass(MCInst &Inst, 188 unsigned RegNo, 189 uint64_t Address, 190 const void *Decoder) { 191 if (RegNo > 31) 192 return MCDisassembler::Fail; 193 unsigned Reg = DFPRegDecoderTable[RegNo]; 194 Inst.addOperand(MCOperand::createReg(Reg)); 195 return MCDisassembler::Success; 196 } 197 198 199 static DecodeStatus DecodeQFPRegsRegisterClass(MCInst &Inst, 200 unsigned RegNo, 201 uint64_t Address, 202 const void *Decoder) { 203 if (RegNo > 31) 204 return MCDisassembler::Fail; 205 206 unsigned Reg = QFPRegDecoderTable[RegNo]; 207 if (Reg == ~0U) 208 return MCDisassembler::Fail; 209 Inst.addOperand(MCOperand::createReg(Reg)); 210 return MCDisassembler::Success; 211 } 212 213 static DecodeStatus DecodeCPRegsRegisterClass(MCInst &Inst, 214 unsigned RegNo, 215 uint64_t Address, 216 const void *Decoder) { 217 if (RegNo > 31) 218 return MCDisassembler::Fail; 219 unsigned Reg = CPRegDecoderTable[RegNo]; 220 Inst.addOperand(MCOperand::createReg(Reg)); 221 return MCDisassembler::Success; 222 } 223 224 static DecodeStatus DecodeFCCRegsRegisterClass(MCInst &Inst, unsigned RegNo, 225 uint64_t Address, 226 const void *Decoder) { 227 if (RegNo > 3) 228 return MCDisassembler::Fail; 229 Inst.addOperand(MCOperand::createReg(FCCRegDecoderTable[RegNo])); 230 return MCDisassembler::Success; 231 } 232 233 static DecodeStatus DecodeASRRegsRegisterClass(MCInst &Inst, unsigned RegNo, 234 uint64_t Address, 235 const void *Decoder) { 236 if (RegNo > 31) 237 return MCDisassembler::Fail; 238 Inst.addOperand(MCOperand::createReg(ASRRegDecoderTable[RegNo])); 239 return MCDisassembler::Success; 240 } 241 242 static DecodeStatus DecodePRRegsRegisterClass(MCInst &Inst, unsigned RegNo, 243 uint64_t Address, 244 const void *Decoder) { 245 if (RegNo >= array_lengthof(PRRegDecoderTable)) 246 return MCDisassembler::Fail; 247 Inst.addOperand(MCOperand::createReg(PRRegDecoderTable[RegNo])); 248 return MCDisassembler::Success; 249 } 250 251 static DecodeStatus DecodeIntPairRegisterClass(MCInst &Inst, unsigned RegNo, 252 uint64_t Address, const void *Decoder) { 253 DecodeStatus S = MCDisassembler::Success; 254 255 if (RegNo > 31) 256 return MCDisassembler::Fail; 257 258 if ((RegNo & 1)) 259 S = MCDisassembler::SoftFail; 260 261 unsigned RegisterPair = IntPairDecoderTable[RegNo/2]; 262 Inst.addOperand(MCOperand::createReg(RegisterPair)); 263 return S; 264 } 265 266 static DecodeStatus DecodeCPPairRegisterClass(MCInst &Inst, unsigned RegNo, 267 uint64_t Address, const void *Decoder) { 268 if (RegNo > 31) 269 return MCDisassembler::Fail; 270 271 unsigned RegisterPair = CPPairDecoderTable[RegNo/2]; 272 Inst.addOperand(MCOperand::createReg(RegisterPair)); 273 return MCDisassembler::Success; 274 } 275 276 static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address, 277 const void *Decoder); 278 static DecodeStatus DecodeLoadIntPair(MCInst &Inst, unsigned insn, uint64_t Address, 279 const void *Decoder); 280 static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address, 281 const void *Decoder); 282 static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address, 283 const void *Decoder); 284 static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address, 285 const void *Decoder); 286 static DecodeStatus DecodeLoadCP(MCInst &Inst, unsigned insn, uint64_t Address, 287 const void *Decoder); 288 static DecodeStatus DecodeLoadCPPair(MCInst &Inst, unsigned insn, uint64_t Address, 289 const void *Decoder); 290 static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn, 291 uint64_t Address, const void *Decoder); 292 static DecodeStatus DecodeStoreIntPair(MCInst &Inst, unsigned insn, 293 uint64_t Address, const void *Decoder); 294 static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn, 295 uint64_t Address, const void *Decoder); 296 static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn, 297 uint64_t Address, const void *Decoder); 298 static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn, 299 uint64_t Address, const void *Decoder); 300 static DecodeStatus DecodeStoreCP(MCInst &Inst, unsigned insn, 301 uint64_t Address, const void *Decoder); 302 static DecodeStatus DecodeStoreCPPair(MCInst &Inst, unsigned insn, 303 uint64_t Address, const void *Decoder); 304 static DecodeStatus DecodeCall(MCInst &Inst, unsigned insn, 305 uint64_t Address, const void *Decoder); 306 static DecodeStatus DecodeSIMM13(MCInst &Inst, unsigned insn, 307 uint64_t Address, const void *Decoder); 308 static DecodeStatus DecodeJMPL(MCInst &Inst, unsigned insn, uint64_t Address, 309 const void *Decoder); 310 static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address, 311 const void *Decoder); 312 static DecodeStatus DecodeSWAP(MCInst &Inst, unsigned insn, uint64_t Address, 313 const void *Decoder); 314 315 #include "SparcGenDisassemblerTables.inc" 316 317 /// Read four bytes from the ArrayRef and return 32 bit word. 318 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, 319 uint64_t &Size, uint32_t &Insn, 320 bool IsLittleEndian) { 321 // We want to read exactly 4 Bytes of data. 322 if (Bytes.size() < 4) { 323 Size = 0; 324 return MCDisassembler::Fail; 325 } 326 327 Insn = IsLittleEndian 328 ? (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | 329 (Bytes[3] << 24) 330 : (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | 331 (Bytes[0] << 24); 332 333 return MCDisassembler::Success; 334 } 335 336 DecodeStatus SparcDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, 337 ArrayRef<uint8_t> Bytes, 338 uint64_t Address, 339 raw_ostream &VStream, 340 raw_ostream &CStream) const { 341 uint32_t Insn; 342 bool isLittleEndian = getContext().getAsmInfo()->isLittleEndian(); 343 DecodeStatus Result = 344 readInstruction32(Bytes, Address, Size, Insn, isLittleEndian); 345 if (Result == MCDisassembler::Fail) 346 return MCDisassembler::Fail; 347 348 // Calling the auto-generated decoder function. 349 Result = 350 decodeInstruction(DecoderTableSparc32, Instr, Insn, Address, this, STI); 351 352 if (Result != MCDisassembler::Fail) { 353 Size = 4; 354 return Result; 355 } 356 357 return MCDisassembler::Fail; 358 } 359 360 361 typedef DecodeStatus (*DecodeFunc)(MCInst &MI, unsigned insn, uint64_t Address, 362 const void *Decoder); 363 364 static DecodeStatus DecodeMem(MCInst &MI, unsigned insn, uint64_t Address, 365 const void *Decoder, 366 bool isLoad, DecodeFunc DecodeRD) { 367 unsigned rd = fieldFromInstruction(insn, 25, 5); 368 unsigned rs1 = fieldFromInstruction(insn, 14, 5); 369 bool isImm = fieldFromInstruction(insn, 13, 1); 370 bool hasAsi = fieldFromInstruction(insn, 23, 1); // (in op3 field) 371 unsigned asi = fieldFromInstruction(insn, 5, 8); 372 unsigned rs2 = 0; 373 unsigned simm13 = 0; 374 if (isImm) 375 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13)); 376 else 377 rs2 = fieldFromInstruction(insn, 0, 5); 378 379 DecodeStatus status; 380 if (isLoad) { 381 status = DecodeRD(MI, rd, Address, Decoder); 382 if (status != MCDisassembler::Success) 383 return status; 384 } 385 386 // Decode rs1. 387 status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); 388 if (status != MCDisassembler::Success) 389 return status; 390 391 // Decode imm|rs2. 392 if (isImm) 393 MI.addOperand(MCOperand::createImm(simm13)); 394 else { 395 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); 396 if (status != MCDisassembler::Success) 397 return status; 398 } 399 400 if (hasAsi) 401 MI.addOperand(MCOperand::createImm(asi)); 402 403 if (!isLoad) { 404 status = DecodeRD(MI, rd, Address, Decoder); 405 if (status != MCDisassembler::Success) 406 return status; 407 } 408 return MCDisassembler::Success; 409 } 410 411 static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address, 412 const void *Decoder) { 413 return DecodeMem(Inst, insn, Address, Decoder, true, 414 DecodeIntRegsRegisterClass); 415 } 416 417 static DecodeStatus DecodeLoadIntPair(MCInst &Inst, unsigned insn, uint64_t Address, 418 const void *Decoder) { 419 return DecodeMem(Inst, insn, Address, Decoder, true, 420 DecodeIntPairRegisterClass); 421 } 422 423 static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address, 424 const void *Decoder) { 425 return DecodeMem(Inst, insn, Address, Decoder, true, 426 DecodeFPRegsRegisterClass); 427 } 428 429 static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address, 430 const void *Decoder) { 431 return DecodeMem(Inst, insn, Address, Decoder, true, 432 DecodeDFPRegsRegisterClass); 433 } 434 435 static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address, 436 const void *Decoder) { 437 return DecodeMem(Inst, insn, Address, Decoder, true, 438 DecodeQFPRegsRegisterClass); 439 } 440 441 static DecodeStatus DecodeLoadCP(MCInst &Inst, unsigned insn, uint64_t Address, 442 const void *Decoder) { 443 return DecodeMem(Inst, insn, Address, Decoder, true, 444 DecodeCPRegsRegisterClass); 445 } 446 447 static DecodeStatus DecodeLoadCPPair(MCInst &Inst, unsigned insn, uint64_t Address, 448 const void *Decoder) { 449 return DecodeMem(Inst, insn, Address, Decoder, true, 450 DecodeCPPairRegisterClass); 451 } 452 453 static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn, 454 uint64_t Address, const void *Decoder) { 455 return DecodeMem(Inst, insn, Address, Decoder, false, 456 DecodeIntRegsRegisterClass); 457 } 458 459 static DecodeStatus DecodeStoreIntPair(MCInst &Inst, unsigned insn, 460 uint64_t Address, const void *Decoder) { 461 return DecodeMem(Inst, insn, Address, Decoder, false, 462 DecodeIntPairRegisterClass); 463 } 464 465 static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn, uint64_t Address, 466 const void *Decoder) { 467 return DecodeMem(Inst, insn, Address, Decoder, false, 468 DecodeFPRegsRegisterClass); 469 } 470 471 static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn, 472 uint64_t Address, const void *Decoder) { 473 return DecodeMem(Inst, insn, Address, Decoder, false, 474 DecodeDFPRegsRegisterClass); 475 } 476 477 static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn, 478 uint64_t Address, const void *Decoder) { 479 return DecodeMem(Inst, insn, Address, Decoder, false, 480 DecodeQFPRegsRegisterClass); 481 } 482 483 static DecodeStatus DecodeStoreCP(MCInst &Inst, unsigned insn, 484 uint64_t Address, const void *Decoder) { 485 return DecodeMem(Inst, insn, Address, Decoder, false, 486 DecodeCPRegsRegisterClass); 487 } 488 489 static DecodeStatus DecodeStoreCPPair(MCInst &Inst, unsigned insn, 490 uint64_t Address, const void *Decoder) { 491 return DecodeMem(Inst, insn, Address, Decoder, false, 492 DecodeCPPairRegisterClass); 493 } 494 495 static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch, 496 uint64_t Address, uint64_t Offset, 497 uint64_t Width, MCInst &MI, 498 const void *Decoder) { 499 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 500 return Dis->tryAddingSymbolicOperand(MI, Value, Address, isBranch, 501 Offset, Width); 502 } 503 504 static DecodeStatus DecodeCall(MCInst &MI, unsigned insn, 505 uint64_t Address, const void *Decoder) { 506 unsigned tgt = fieldFromInstruction(insn, 0, 30); 507 tgt <<= 2; 508 if (!tryAddingSymbolicOperand(tgt+Address, false, Address, 509 0, 30, MI, Decoder)) 510 MI.addOperand(MCOperand::createImm(tgt)); 511 return MCDisassembler::Success; 512 } 513 514 static DecodeStatus DecodeSIMM13(MCInst &MI, unsigned insn, 515 uint64_t Address, const void *Decoder) { 516 unsigned tgt = SignExtend32<13>(fieldFromInstruction(insn, 0, 13)); 517 MI.addOperand(MCOperand::createImm(tgt)); 518 return MCDisassembler::Success; 519 } 520 521 static DecodeStatus DecodeJMPL(MCInst &MI, unsigned insn, uint64_t Address, 522 const void *Decoder) { 523 524 unsigned rd = fieldFromInstruction(insn, 25, 5); 525 unsigned rs1 = fieldFromInstruction(insn, 14, 5); 526 unsigned isImm = fieldFromInstruction(insn, 13, 1); 527 unsigned rs2 = 0; 528 unsigned simm13 = 0; 529 if (isImm) 530 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13)); 531 else 532 rs2 = fieldFromInstruction(insn, 0, 5); 533 534 // Decode RD. 535 DecodeStatus status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder); 536 if (status != MCDisassembler::Success) 537 return status; 538 539 // Decode RS1. 540 status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); 541 if (status != MCDisassembler::Success) 542 return status; 543 544 // Decode RS1 | SIMM13. 545 if (isImm) 546 MI.addOperand(MCOperand::createImm(simm13)); 547 else { 548 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); 549 if (status != MCDisassembler::Success) 550 return status; 551 } 552 return MCDisassembler::Success; 553 } 554 555 static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address, 556 const void *Decoder) { 557 558 unsigned rs1 = fieldFromInstruction(insn, 14, 5); 559 unsigned isImm = fieldFromInstruction(insn, 13, 1); 560 unsigned rs2 = 0; 561 unsigned simm13 = 0; 562 if (isImm) 563 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13)); 564 else 565 rs2 = fieldFromInstruction(insn, 0, 5); 566 567 // Decode RS1. 568 DecodeStatus status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); 569 if (status != MCDisassembler::Success) 570 return status; 571 572 // Decode RS2 | SIMM13. 573 if (isImm) 574 MI.addOperand(MCOperand::createImm(simm13)); 575 else { 576 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); 577 if (status != MCDisassembler::Success) 578 return status; 579 } 580 return MCDisassembler::Success; 581 } 582 583 static DecodeStatus DecodeSWAP(MCInst &MI, unsigned insn, uint64_t Address, 584 const void *Decoder) { 585 586 unsigned rd = fieldFromInstruction(insn, 25, 5); 587 unsigned rs1 = fieldFromInstruction(insn, 14, 5); 588 unsigned isImm = fieldFromInstruction(insn, 13, 1); 589 bool hasAsi = fieldFromInstruction(insn, 23, 1); // (in op3 field) 590 unsigned asi = fieldFromInstruction(insn, 5, 8); 591 unsigned rs2 = 0; 592 unsigned simm13 = 0; 593 if (isImm) 594 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13)); 595 else 596 rs2 = fieldFromInstruction(insn, 0, 5); 597 598 // Decode RD. 599 DecodeStatus status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder); 600 if (status != MCDisassembler::Success) 601 return status; 602 603 // Decode RS1. 604 status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); 605 if (status != MCDisassembler::Success) 606 return status; 607 608 // Decode RS1 | SIMM13. 609 if (isImm) 610 MI.addOperand(MCOperand::createImm(simm13)); 611 else { 612 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); 613 if (status != MCDisassembler::Success) 614 return status; 615 } 616 617 if (hasAsi) 618 MI.addOperand(MCOperand::createImm(asi)); 619 620 return MCDisassembler::Success; 621 } 622