1 //===- SparcDisassembler.cpp - Disassembler for Sparc -----------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the Sparc Disassembler. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "Sparc.h" 15 #include "SparcRegisterInfo.h" 16 #include "SparcSubtarget.h" 17 #include "llvm/MC/MCDisassembler.h" 18 #include "llvm/MC/MCFixedLenDisassembler.h" 19 #include "llvm/Support/MemoryObject.h" 20 #include "llvm/Support/TargetRegistry.h" 21 22 using namespace llvm; 23 24 #define DEBUG_TYPE "sparc-disassembler" 25 26 typedef MCDisassembler::DecodeStatus DecodeStatus; 27 28 namespace { 29 30 /// A disassembler class for Sparc. 31 class SparcDisassembler : public MCDisassembler { 32 public: 33 SparcDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) 34 : MCDisassembler(STI, Ctx) {} 35 virtual ~SparcDisassembler() {} 36 37 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 38 const MemoryObject &Region, uint64_t Address, 39 raw_ostream &VStream, 40 raw_ostream &CStream) const override; 41 }; 42 43 } 44 45 namespace llvm { 46 extern Target TheSparcTarget, TheSparcV9Target; 47 } 48 49 static MCDisassembler *createSparcDisassembler( 50 const Target &T, 51 const MCSubtargetInfo &STI, 52 MCContext &Ctx) { 53 return new SparcDisassembler(STI, Ctx); 54 } 55 56 57 extern "C" void LLVMInitializeSparcDisassembler() { 58 // Register the disassembler. 59 TargetRegistry::RegisterMCDisassembler(TheSparcTarget, 60 createSparcDisassembler); 61 TargetRegistry::RegisterMCDisassembler(TheSparcV9Target, 62 createSparcDisassembler); 63 } 64 65 66 67 static const unsigned IntRegDecoderTable[] = { 68 SP::G0, SP::G1, SP::G2, SP::G3, 69 SP::G4, SP::G5, SP::G6, SP::G7, 70 SP::O0, SP::O1, SP::O2, SP::O3, 71 SP::O4, SP::O5, SP::O6, SP::O7, 72 SP::L0, SP::L1, SP::L2, SP::L3, 73 SP::L4, SP::L5, SP::L6, SP::L7, 74 SP::I0, SP::I1, SP::I2, SP::I3, 75 SP::I4, SP::I5, SP::I6, SP::I7 }; 76 77 static const unsigned FPRegDecoderTable[] = { 78 SP::F0, SP::F1, SP::F2, SP::F3, 79 SP::F4, SP::F5, SP::F6, SP::F7, 80 SP::F8, SP::F9, SP::F10, SP::F11, 81 SP::F12, SP::F13, SP::F14, SP::F15, 82 SP::F16, SP::F17, SP::F18, SP::F19, 83 SP::F20, SP::F21, SP::F22, SP::F23, 84 SP::F24, SP::F25, SP::F26, SP::F27, 85 SP::F28, SP::F29, SP::F30, SP::F31 }; 86 87 static const unsigned DFPRegDecoderTable[] = { 88 SP::D0, SP::D16, SP::D1, SP::D17, 89 SP::D2, SP::D18, SP::D3, SP::D19, 90 SP::D4, SP::D20, SP::D5, SP::D21, 91 SP::D6, SP::D22, SP::D7, SP::D23, 92 SP::D8, SP::D24, SP::D9, SP::D25, 93 SP::D10, SP::D26, SP::D11, SP::D27, 94 SP::D12, SP::D28, SP::D13, SP::D29, 95 SP::D14, SP::D30, SP::D15, SP::D31 }; 96 97 static const unsigned QFPRegDecoderTable[] = { 98 SP::Q0, SP::Q8, ~0U, ~0U, 99 SP::Q1, SP::Q9, ~0U, ~0U, 100 SP::Q2, SP::Q10, ~0U, ~0U, 101 SP::Q3, SP::Q11, ~0U, ~0U, 102 SP::Q4, SP::Q12, ~0U, ~0U, 103 SP::Q5, SP::Q13, ~0U, ~0U, 104 SP::Q6, SP::Q14, ~0U, ~0U, 105 SP::Q7, SP::Q15, ~0U, ~0U } ; 106 107 static const unsigned FCCRegDecoderTable[] = { 108 SP::FCC0, SP::FCC1, SP::FCC2, SP::FCC3 }; 109 110 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, 111 unsigned RegNo, 112 uint64_t Address, 113 const void *Decoder) { 114 if (RegNo > 31) 115 return MCDisassembler::Fail; 116 unsigned Reg = IntRegDecoderTable[RegNo]; 117 Inst.addOperand(MCOperand::CreateReg(Reg)); 118 return MCDisassembler::Success; 119 } 120 121 static DecodeStatus DecodeI64RegsRegisterClass(MCInst &Inst, 122 unsigned RegNo, 123 uint64_t Address, 124 const void *Decoder) { 125 if (RegNo > 31) 126 return MCDisassembler::Fail; 127 unsigned Reg = IntRegDecoderTable[RegNo]; 128 Inst.addOperand(MCOperand::CreateReg(Reg)); 129 return MCDisassembler::Success; 130 } 131 132 133 static DecodeStatus DecodeFPRegsRegisterClass(MCInst &Inst, 134 unsigned RegNo, 135 uint64_t Address, 136 const void *Decoder) { 137 if (RegNo > 31) 138 return MCDisassembler::Fail; 139 unsigned Reg = FPRegDecoderTable[RegNo]; 140 Inst.addOperand(MCOperand::CreateReg(Reg)); 141 return MCDisassembler::Success; 142 } 143 144 145 static DecodeStatus DecodeDFPRegsRegisterClass(MCInst &Inst, 146 unsigned RegNo, 147 uint64_t Address, 148 const void *Decoder) { 149 if (RegNo > 31) 150 return MCDisassembler::Fail; 151 unsigned Reg = DFPRegDecoderTable[RegNo]; 152 Inst.addOperand(MCOperand::CreateReg(Reg)); 153 return MCDisassembler::Success; 154 } 155 156 157 static DecodeStatus DecodeQFPRegsRegisterClass(MCInst &Inst, 158 unsigned RegNo, 159 uint64_t Address, 160 const void *Decoder) { 161 if (RegNo > 31) 162 return MCDisassembler::Fail; 163 164 unsigned Reg = QFPRegDecoderTable[RegNo]; 165 if (Reg == ~0U) 166 return MCDisassembler::Fail; 167 Inst.addOperand(MCOperand::CreateReg(Reg)); 168 return MCDisassembler::Success; 169 } 170 171 static DecodeStatus DecodeFCCRegsRegisterClass(MCInst &Inst, unsigned RegNo, 172 uint64_t Address, 173 const void *Decoder) { 174 if (RegNo > 3) 175 return MCDisassembler::Fail; 176 Inst.addOperand(MCOperand::CreateReg(FCCRegDecoderTable[RegNo])); 177 return MCDisassembler::Success; 178 } 179 180 181 static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address, 182 const void *Decoder); 183 static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address, 184 const void *Decoder); 185 static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address, 186 const void *Decoder); 187 static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address, 188 const void *Decoder); 189 static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn, 190 uint64_t Address, const void *Decoder); 191 static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn, 192 uint64_t Address, const void *Decoder); 193 static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn, 194 uint64_t Address, const void *Decoder); 195 static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn, 196 uint64_t Address, const void *Decoder); 197 static DecodeStatus DecodeCall(MCInst &Inst, unsigned insn, 198 uint64_t Address, const void *Decoder); 199 static DecodeStatus DecodeSIMM13(MCInst &Inst, unsigned insn, 200 uint64_t Address, const void *Decoder); 201 static DecodeStatus DecodeJMPL(MCInst &Inst, unsigned insn, uint64_t Address, 202 const void *Decoder); 203 static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address, 204 const void *Decoder); 205 static DecodeStatus DecodeSWAP(MCInst &Inst, unsigned insn, uint64_t Address, 206 const void *Decoder); 207 208 #include "SparcGenDisassemblerTables.inc" 209 210 /// Read four bytes from the MemoryObject and return 32 bit word. 211 static DecodeStatus readInstruction32(const MemoryObject &Region, 212 uint64_t Address, uint64_t &Size, 213 uint32_t &Insn) { 214 uint8_t Bytes[4]; 215 216 // We want to read exactly 4 Bytes of data. 217 if (Region.readBytes(Address, 4, Bytes) == -1) { 218 Size = 0; 219 return MCDisassembler::Fail; 220 } 221 222 // Encoded as a big-endian 32-bit word in the stream. 223 Insn = 224 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24); 225 226 return MCDisassembler::Success; 227 } 228 229 DecodeStatus SparcDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, 230 const MemoryObject &Region, 231 uint64_t Address, 232 raw_ostream &VStream, 233 raw_ostream &CStream) const { 234 uint32_t Insn; 235 236 DecodeStatus Result = readInstruction32(Region, Address, Size, Insn); 237 if (Result == MCDisassembler::Fail) 238 return MCDisassembler::Fail; 239 240 241 // Calling the auto-generated decoder function. 242 Result = 243 decodeInstruction(DecoderTableSparc32, Instr, Insn, Address, this, STI); 244 245 if (Result != MCDisassembler::Fail) { 246 Size = 4; 247 return Result; 248 } 249 250 return MCDisassembler::Fail; 251 } 252 253 254 typedef DecodeStatus (*DecodeFunc)(MCInst &MI, unsigned insn, uint64_t Address, 255 const void *Decoder); 256 257 static DecodeStatus DecodeMem(MCInst &MI, unsigned insn, uint64_t Address, 258 const void *Decoder, 259 bool isLoad, DecodeFunc DecodeRD) { 260 unsigned rd = fieldFromInstruction(insn, 25, 5); 261 unsigned rs1 = fieldFromInstruction(insn, 14, 5); 262 bool isImm = fieldFromInstruction(insn, 13, 1); 263 unsigned rs2 = 0; 264 unsigned simm13 = 0; 265 if (isImm) 266 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13)); 267 else 268 rs2 = fieldFromInstruction(insn, 0, 5); 269 270 DecodeStatus status; 271 if (isLoad) { 272 status = DecodeRD(MI, rd, Address, Decoder); 273 if (status != MCDisassembler::Success) 274 return status; 275 } 276 277 // Decode rs1. 278 status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); 279 if (status != MCDisassembler::Success) 280 return status; 281 282 // Decode imm|rs2. 283 if (isImm) 284 MI.addOperand(MCOperand::CreateImm(simm13)); 285 else { 286 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); 287 if (status != MCDisassembler::Success) 288 return status; 289 } 290 291 if (!isLoad) { 292 status = DecodeRD(MI, rd, Address, Decoder); 293 if (status != MCDisassembler::Success) 294 return status; 295 } 296 return MCDisassembler::Success; 297 } 298 299 static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address, 300 const void *Decoder) { 301 return DecodeMem(Inst, insn, Address, Decoder, true, 302 DecodeIntRegsRegisterClass); 303 } 304 305 static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address, 306 const void *Decoder) { 307 return DecodeMem(Inst, insn, Address, Decoder, true, 308 DecodeFPRegsRegisterClass); 309 } 310 311 static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address, 312 const void *Decoder) { 313 return DecodeMem(Inst, insn, Address, Decoder, true, 314 DecodeDFPRegsRegisterClass); 315 } 316 317 static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address, 318 const void *Decoder) { 319 return DecodeMem(Inst, insn, Address, Decoder, true, 320 DecodeQFPRegsRegisterClass); 321 } 322 323 static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn, 324 uint64_t Address, const void *Decoder) { 325 return DecodeMem(Inst, insn, Address, Decoder, false, 326 DecodeIntRegsRegisterClass); 327 } 328 329 static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn, uint64_t Address, 330 const void *Decoder) { 331 return DecodeMem(Inst, insn, Address, Decoder, false, 332 DecodeFPRegsRegisterClass); 333 } 334 335 static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn, 336 uint64_t Address, const void *Decoder) { 337 return DecodeMem(Inst, insn, Address, Decoder, false, 338 DecodeDFPRegsRegisterClass); 339 } 340 341 static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn, 342 uint64_t Address, const void *Decoder) { 343 return DecodeMem(Inst, insn, Address, Decoder, false, 344 DecodeQFPRegsRegisterClass); 345 } 346 347 static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch, 348 uint64_t Address, uint64_t Offset, 349 uint64_t Width, MCInst &MI, 350 const void *Decoder) { 351 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 352 return Dis->tryAddingSymbolicOperand(MI, Value, Address, isBranch, 353 Offset, Width); 354 } 355 356 static DecodeStatus DecodeCall(MCInst &MI, unsigned insn, 357 uint64_t Address, const void *Decoder) { 358 unsigned tgt = fieldFromInstruction(insn, 0, 30); 359 tgt <<= 2; 360 if (!tryAddingSymbolicOperand(tgt+Address, false, Address, 361 0, 30, MI, Decoder)) 362 MI.addOperand(MCOperand::CreateImm(tgt)); 363 return MCDisassembler::Success; 364 } 365 366 static DecodeStatus DecodeSIMM13(MCInst &MI, unsigned insn, 367 uint64_t Address, const void *Decoder) { 368 unsigned tgt = SignExtend32<13>(fieldFromInstruction(insn, 0, 13)); 369 MI.addOperand(MCOperand::CreateImm(tgt)); 370 return MCDisassembler::Success; 371 } 372 373 static DecodeStatus DecodeJMPL(MCInst &MI, unsigned insn, uint64_t Address, 374 const void *Decoder) { 375 376 unsigned rd = fieldFromInstruction(insn, 25, 5); 377 unsigned rs1 = fieldFromInstruction(insn, 14, 5); 378 unsigned isImm = fieldFromInstruction(insn, 13, 1); 379 unsigned rs2 = 0; 380 unsigned simm13 = 0; 381 if (isImm) 382 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13)); 383 else 384 rs2 = fieldFromInstruction(insn, 0, 5); 385 386 // Decode RD. 387 DecodeStatus status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder); 388 if (status != MCDisassembler::Success) 389 return status; 390 391 // Decode RS1. 392 status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); 393 if (status != MCDisassembler::Success) 394 return status; 395 396 // Decode RS1 | SIMM13. 397 if (isImm) 398 MI.addOperand(MCOperand::CreateImm(simm13)); 399 else { 400 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); 401 if (status != MCDisassembler::Success) 402 return status; 403 } 404 return MCDisassembler::Success; 405 } 406 407 static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address, 408 const void *Decoder) { 409 410 unsigned rs1 = fieldFromInstruction(insn, 14, 5); 411 unsigned isImm = fieldFromInstruction(insn, 13, 1); 412 unsigned rs2 = 0; 413 unsigned simm13 = 0; 414 if (isImm) 415 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13)); 416 else 417 rs2 = fieldFromInstruction(insn, 0, 5); 418 419 // Decode RS1. 420 DecodeStatus status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); 421 if (status != MCDisassembler::Success) 422 return status; 423 424 // Decode RS2 | SIMM13. 425 if (isImm) 426 MI.addOperand(MCOperand::CreateImm(simm13)); 427 else { 428 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); 429 if (status != MCDisassembler::Success) 430 return status; 431 } 432 return MCDisassembler::Success; 433 } 434 435 static DecodeStatus DecodeSWAP(MCInst &MI, unsigned insn, uint64_t Address, 436 const void *Decoder) { 437 438 unsigned rd = fieldFromInstruction(insn, 25, 5); 439 unsigned rs1 = fieldFromInstruction(insn, 14, 5); 440 unsigned isImm = fieldFromInstruction(insn, 13, 1); 441 unsigned rs2 = 0; 442 unsigned simm13 = 0; 443 if (isImm) 444 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13)); 445 else 446 rs2 = fieldFromInstruction(insn, 0, 5); 447 448 // Decode RD. 449 DecodeStatus status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder); 450 if (status != MCDisassembler::Success) 451 return status; 452 453 // Decode RS1. 454 status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); 455 if (status != MCDisassembler::Success) 456 return status; 457 458 // Decode RS1 | SIMM13. 459 if (isImm) 460 MI.addOperand(MCOperand::CreateImm(simm13)); 461 else { 462 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); 463 if (status != MCDisassembler::Success) 464 return status; 465 } 466 return MCDisassembler::Success; 467 } 468