1 //===- SparcDisassembler.cpp - Disassembler for Sparc -----------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file is part of the Sparc Disassembler. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "MCTargetDesc/SparcMCTargetDesc.h" 14 #include "TargetInfo/SparcTargetInfo.h" 15 #include "llvm/MC/MCAsmInfo.h" 16 #include "llvm/MC/MCContext.h" 17 #include "llvm/MC/MCDecoderOps.h" 18 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 19 #include "llvm/MC/MCInst.h" 20 #include "llvm/MC/TargetRegistry.h" 21 22 using namespace llvm; 23 24 #define DEBUG_TYPE "sparc-disassembler" 25 26 typedef MCDisassembler::DecodeStatus DecodeStatus; 27 28 namespace { 29 30 /// A disassembler class for Sparc. 31 class SparcDisassembler : public MCDisassembler { 32 public: 33 SparcDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) 34 : MCDisassembler(STI, Ctx) {} 35 virtual ~SparcDisassembler() = default; 36 37 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 38 ArrayRef<uint8_t> Bytes, uint64_t Address, 39 raw_ostream &CStream) const override; 40 }; 41 } 42 43 static MCDisassembler *createSparcDisassembler(const Target &T, 44 const MCSubtargetInfo &STI, 45 MCContext &Ctx) { 46 return new SparcDisassembler(STI, Ctx); 47 } 48 49 50 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSparcDisassembler() { 51 // Register the disassembler. 52 TargetRegistry::RegisterMCDisassembler(getTheSparcTarget(), 53 createSparcDisassembler); 54 TargetRegistry::RegisterMCDisassembler(getTheSparcV9Target(), 55 createSparcDisassembler); 56 TargetRegistry::RegisterMCDisassembler(getTheSparcelTarget(), 57 createSparcDisassembler); 58 } 59 60 static const unsigned IntRegDecoderTable[] = { 61 SP::G0, SP::G1, SP::G2, SP::G3, 62 SP::G4, SP::G5, SP::G6, SP::G7, 63 SP::O0, SP::O1, SP::O2, SP::O3, 64 SP::O4, SP::O5, SP::O6, SP::O7, 65 SP::L0, SP::L1, SP::L2, SP::L3, 66 SP::L4, SP::L5, SP::L6, SP::L7, 67 SP::I0, SP::I1, SP::I2, SP::I3, 68 SP::I4, SP::I5, SP::I6, SP::I7 }; 69 70 static const unsigned FPRegDecoderTable[] = { 71 SP::F0, SP::F1, SP::F2, SP::F3, 72 SP::F4, SP::F5, SP::F6, SP::F7, 73 SP::F8, SP::F9, SP::F10, SP::F11, 74 SP::F12, SP::F13, SP::F14, SP::F15, 75 SP::F16, SP::F17, SP::F18, SP::F19, 76 SP::F20, SP::F21, SP::F22, SP::F23, 77 SP::F24, SP::F25, SP::F26, SP::F27, 78 SP::F28, SP::F29, SP::F30, SP::F31 }; 79 80 static const unsigned DFPRegDecoderTable[] = { 81 SP::D0, SP::D16, SP::D1, SP::D17, 82 SP::D2, SP::D18, SP::D3, SP::D19, 83 SP::D4, SP::D20, SP::D5, SP::D21, 84 SP::D6, SP::D22, SP::D7, SP::D23, 85 SP::D8, SP::D24, SP::D9, SP::D25, 86 SP::D10, SP::D26, SP::D11, SP::D27, 87 SP::D12, SP::D28, SP::D13, SP::D29, 88 SP::D14, SP::D30, SP::D15, SP::D31 }; 89 90 static const unsigned QFPRegDecoderTable[] = { 91 SP::Q0, SP::Q8, ~0U, ~0U, 92 SP::Q1, SP::Q9, ~0U, ~0U, 93 SP::Q2, SP::Q10, ~0U, ~0U, 94 SP::Q3, SP::Q11, ~0U, ~0U, 95 SP::Q4, SP::Q12, ~0U, ~0U, 96 SP::Q5, SP::Q13, ~0U, ~0U, 97 SP::Q6, SP::Q14, ~0U, ~0U, 98 SP::Q7, SP::Q15, ~0U, ~0U } ; 99 100 static const unsigned FCCRegDecoderTable[] = { 101 SP::FCC0, SP::FCC1, SP::FCC2, SP::FCC3 }; 102 103 static const unsigned ASRRegDecoderTable[] = { 104 SP::Y, SP::ASR1, SP::ASR2, SP::ASR3, 105 SP::ASR4, SP::ASR5, SP::ASR6, SP::ASR7, 106 SP::ASR8, SP::ASR9, SP::ASR10, SP::ASR11, 107 SP::ASR12, SP::ASR13, SP::ASR14, SP::ASR15, 108 SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19, 109 SP::ASR20, SP::ASR21, SP::ASR22, SP::ASR23, 110 SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27, 111 SP::ASR28, SP::ASR29, SP::ASR30, SP::ASR31}; 112 113 static const unsigned PRRegDecoderTable[] = { 114 SP::TPC, SP::TNPC, SP::TSTATE, SP::TT, SP::TICK, SP::TBA, SP::PSTATE, 115 SP::TL, SP::PIL, SP::CWP, SP::CANSAVE, SP::CANRESTORE, SP::CLEANWIN, 116 SP::OTHERWIN, SP::WSTATE, SP::PC 117 }; 118 119 static const uint16_t IntPairDecoderTable[] = { 120 SP::G0_G1, SP::G2_G3, SP::G4_G5, SP::G6_G7, 121 SP::O0_O1, SP::O2_O3, SP::O4_O5, SP::O6_O7, 122 SP::L0_L1, SP::L2_L3, SP::L4_L5, SP::L6_L7, 123 SP::I0_I1, SP::I2_I3, SP::I4_I5, SP::I6_I7, 124 }; 125 126 static const unsigned CPRegDecoderTable[] = { 127 SP::C0, SP::C1, SP::C2, SP::C3, 128 SP::C4, SP::C5, SP::C6, SP::C7, 129 SP::C8, SP::C9, SP::C10, SP::C11, 130 SP::C12, SP::C13, SP::C14, SP::C15, 131 SP::C16, SP::C17, SP::C18, SP::C19, 132 SP::C20, SP::C21, SP::C22, SP::C23, 133 SP::C24, SP::C25, SP::C26, SP::C27, 134 SP::C28, SP::C29, SP::C30, SP::C31 135 }; 136 137 138 static const uint16_t CPPairDecoderTable[] = { 139 SP::C0_C1, SP::C2_C3, SP::C4_C5, SP::C6_C7, 140 SP::C8_C9, SP::C10_C11, SP::C12_C13, SP::C14_C15, 141 SP::C16_C17, SP::C18_C19, SP::C20_C21, SP::C22_C23, 142 SP::C24_C25, SP::C26_C27, SP::C28_C29, SP::C30_C31 143 }; 144 145 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, 146 uint64_t Address, 147 const MCDisassembler *Decoder) { 148 if (RegNo > 31) 149 return MCDisassembler::Fail; 150 unsigned Reg = IntRegDecoderTable[RegNo]; 151 Inst.addOperand(MCOperand::createReg(Reg)); 152 return MCDisassembler::Success; 153 } 154 155 static DecodeStatus DecodeI64RegsRegisterClass(MCInst &Inst, unsigned RegNo, 156 uint64_t Address, 157 const MCDisassembler *Decoder) { 158 if (RegNo > 31) 159 return MCDisassembler::Fail; 160 unsigned Reg = IntRegDecoderTable[RegNo]; 161 Inst.addOperand(MCOperand::createReg(Reg)); 162 return MCDisassembler::Success; 163 } 164 165 static DecodeStatus DecodeFPRegsRegisterClass(MCInst &Inst, unsigned RegNo, 166 uint64_t Address, 167 const MCDisassembler *Decoder) { 168 if (RegNo > 31) 169 return MCDisassembler::Fail; 170 unsigned Reg = FPRegDecoderTable[RegNo]; 171 Inst.addOperand(MCOperand::createReg(Reg)); 172 return MCDisassembler::Success; 173 } 174 175 static DecodeStatus DecodeDFPRegsRegisterClass(MCInst &Inst, unsigned RegNo, 176 uint64_t Address, 177 const MCDisassembler *Decoder) { 178 if (RegNo > 31) 179 return MCDisassembler::Fail; 180 unsigned Reg = DFPRegDecoderTable[RegNo]; 181 Inst.addOperand(MCOperand::createReg(Reg)); 182 return MCDisassembler::Success; 183 } 184 185 static DecodeStatus DecodeQFPRegsRegisterClass(MCInst &Inst, unsigned RegNo, 186 uint64_t Address, 187 const MCDisassembler *Decoder) { 188 if (RegNo > 31) 189 return MCDisassembler::Fail; 190 191 unsigned Reg = QFPRegDecoderTable[RegNo]; 192 if (Reg == ~0U) 193 return MCDisassembler::Fail; 194 Inst.addOperand(MCOperand::createReg(Reg)); 195 return MCDisassembler::Success; 196 } 197 198 static DecodeStatus DecodeCPRegsRegisterClass(MCInst &Inst, unsigned RegNo, 199 uint64_t Address, 200 const MCDisassembler *Decoder) { 201 if (RegNo > 31) 202 return MCDisassembler::Fail; 203 unsigned Reg = CPRegDecoderTable[RegNo]; 204 Inst.addOperand(MCOperand::createReg(Reg)); 205 return MCDisassembler::Success; 206 } 207 208 static DecodeStatus DecodeFCCRegsRegisterClass(MCInst &Inst, unsigned RegNo, 209 uint64_t Address, 210 const MCDisassembler *Decoder) { 211 if (RegNo > 3) 212 return MCDisassembler::Fail; 213 Inst.addOperand(MCOperand::createReg(FCCRegDecoderTable[RegNo])); 214 return MCDisassembler::Success; 215 } 216 217 static DecodeStatus DecodeASRRegsRegisterClass(MCInst &Inst, unsigned RegNo, 218 uint64_t Address, 219 const MCDisassembler *Decoder) { 220 if (RegNo > 31) 221 return MCDisassembler::Fail; 222 Inst.addOperand(MCOperand::createReg(ASRRegDecoderTable[RegNo])); 223 return MCDisassembler::Success; 224 } 225 226 static DecodeStatus DecodePRRegsRegisterClass(MCInst &Inst, unsigned RegNo, 227 uint64_t Address, 228 const MCDisassembler *Decoder) { 229 if (RegNo >= std::size(PRRegDecoderTable)) 230 return MCDisassembler::Fail; 231 Inst.addOperand(MCOperand::createReg(PRRegDecoderTable[RegNo])); 232 return MCDisassembler::Success; 233 } 234 235 static DecodeStatus DecodeIntPairRegisterClass(MCInst &Inst, unsigned RegNo, 236 uint64_t Address, 237 const MCDisassembler *Decoder) { 238 DecodeStatus S = MCDisassembler::Success; 239 240 if (RegNo > 31) 241 return MCDisassembler::Fail; 242 243 if ((RegNo & 1)) 244 S = MCDisassembler::SoftFail; 245 246 unsigned RegisterPair = IntPairDecoderTable[RegNo/2]; 247 Inst.addOperand(MCOperand::createReg(RegisterPair)); 248 return S; 249 } 250 251 static DecodeStatus DecodeCPPairRegisterClass(MCInst &Inst, unsigned RegNo, 252 uint64_t Address, 253 const MCDisassembler *Decoder) { 254 if (RegNo > 31) 255 return MCDisassembler::Fail; 256 257 unsigned RegisterPair = CPPairDecoderTable[RegNo/2]; 258 Inst.addOperand(MCOperand::createReg(RegisterPair)); 259 return MCDisassembler::Success; 260 } 261 262 static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address, 263 const MCDisassembler *Decoder); 264 static DecodeStatus DecodeLoadIntPair(MCInst &Inst, unsigned insn, 265 uint64_t Address, 266 const MCDisassembler *Decoder); 267 static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address, 268 const MCDisassembler *Decoder); 269 static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address, 270 const MCDisassembler *Decoder); 271 static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address, 272 const MCDisassembler *Decoder); 273 static DecodeStatus DecodeLoadCP(MCInst &Inst, unsigned insn, uint64_t Address, 274 const MCDisassembler *Decoder); 275 static DecodeStatus DecodeLoadCPPair(MCInst &Inst, unsigned insn, 276 uint64_t Address, 277 const MCDisassembler *Decoder); 278 static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn, 279 uint64_t Address, 280 const MCDisassembler *Decoder); 281 static DecodeStatus DecodeStoreIntPair(MCInst &Inst, unsigned insn, 282 uint64_t Address, 283 const MCDisassembler *Decoder); 284 static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn, uint64_t Address, 285 const MCDisassembler *Decoder); 286 static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn, 287 uint64_t Address, 288 const MCDisassembler *Decoder); 289 static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn, 290 uint64_t Address, 291 const MCDisassembler *Decoder); 292 static DecodeStatus DecodeStoreCP(MCInst &Inst, unsigned insn, uint64_t Address, 293 const MCDisassembler *Decoder); 294 static DecodeStatus DecodeStoreCPPair(MCInst &Inst, unsigned insn, 295 uint64_t Address, 296 const MCDisassembler *Decoder); 297 static DecodeStatus DecodeCall(MCInst &Inst, unsigned insn, uint64_t Address, 298 const MCDisassembler *Decoder); 299 static DecodeStatus DecodeSIMM13(MCInst &Inst, unsigned insn, uint64_t Address, 300 const MCDisassembler *Decoder); 301 static DecodeStatus DecodeJMPL(MCInst &Inst, unsigned insn, uint64_t Address, 302 const MCDisassembler *Decoder); 303 static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address, 304 const MCDisassembler *Decoder); 305 static DecodeStatus DecodeSWAP(MCInst &Inst, unsigned insn, uint64_t Address, 306 const MCDisassembler *Decoder); 307 static DecodeStatus DecodeTRAP(MCInst &Inst, unsigned insn, uint64_t Address, 308 const MCDisassembler *Decoder); 309 static DecodeStatus DecodeFIXMEInstruction(MCInst &MI, unsigned insn, 310 uint64_t Address, 311 const MCDisassembler *Decoder); 312 313 #include "SparcGenDisassemblerTables.inc" 314 315 /// Read four bytes from the ArrayRef and return 32 bit word. 316 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, 317 uint64_t &Size, uint32_t &Insn, 318 bool IsLittleEndian) { 319 // We want to read exactly 4 Bytes of data. 320 if (Bytes.size() < 4) { 321 Size = 0; 322 return MCDisassembler::Fail; 323 } 324 325 Insn = IsLittleEndian 326 ? (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | 327 (Bytes[3] << 24) 328 : (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | 329 (Bytes[0] << 24); 330 331 return MCDisassembler::Success; 332 } 333 334 DecodeStatus SparcDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, 335 ArrayRef<uint8_t> Bytes, 336 uint64_t Address, 337 raw_ostream &CStream) const { 338 uint32_t Insn; 339 bool isLittleEndian = getContext().getAsmInfo()->isLittleEndian(); 340 DecodeStatus Result = 341 readInstruction32(Bytes, Address, Size, Insn, isLittleEndian); 342 if (Result == MCDisassembler::Fail) 343 return MCDisassembler::Fail; 344 345 // Calling the auto-generated decoder function. 346 347 if (STI.getFeatureBits()[Sparc::FeatureV9]) 348 { 349 Result = decodeInstruction(DecoderTableSparcV932, Instr, Insn, Address, this, STI); 350 } 351 else 352 { 353 Result = decodeInstruction(DecoderTableSparcV832, Instr, Insn, Address, this, STI); 354 } 355 if (Result != MCDisassembler::Fail) 356 return Result; 357 358 Result = 359 decodeInstruction(DecoderTableSparc32, Instr, Insn, Address, this, STI); 360 361 if (Result != MCDisassembler::Fail) { 362 Size = 4; 363 return Result; 364 } 365 366 return MCDisassembler::Fail; 367 } 368 369 typedef DecodeStatus (*DecodeFunc)(MCInst &MI, unsigned insn, uint64_t Address, 370 const MCDisassembler *Decoder); 371 372 static DecodeStatus DecodeMem(MCInst &MI, unsigned insn, uint64_t Address, 373 const MCDisassembler *Decoder, bool isLoad, 374 DecodeFunc DecodeRD) { 375 unsigned rd = fieldFromInstruction(insn, 25, 5); 376 unsigned rs1 = fieldFromInstruction(insn, 14, 5); 377 bool isImm = fieldFromInstruction(insn, 13, 1); 378 bool hasAsi = fieldFromInstruction(insn, 23, 1); // (in op3 field) 379 unsigned asi = fieldFromInstruction(insn, 5, 8); 380 unsigned rs2 = 0; 381 unsigned simm13 = 0; 382 if (isImm) 383 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13)); 384 else 385 rs2 = fieldFromInstruction(insn, 0, 5); 386 387 DecodeStatus status; 388 if (isLoad) { 389 status = DecodeRD(MI, rd, Address, Decoder); 390 if (status != MCDisassembler::Success) 391 return status; 392 } 393 394 // Decode rs1. 395 status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); 396 if (status != MCDisassembler::Success) 397 return status; 398 399 // Decode imm|rs2. 400 if (isImm) 401 MI.addOperand(MCOperand::createImm(simm13)); 402 else { 403 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); 404 if (status != MCDisassembler::Success) 405 return status; 406 } 407 408 if (hasAsi) 409 MI.addOperand(MCOperand::createImm(asi)); 410 411 if (!isLoad) { 412 status = DecodeRD(MI, rd, Address, Decoder); 413 if (status != MCDisassembler::Success) 414 return status; 415 } 416 return MCDisassembler::Success; 417 } 418 419 static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address, 420 const MCDisassembler *Decoder) { 421 return DecodeMem(Inst, insn, Address, Decoder, true, 422 DecodeIntRegsRegisterClass); 423 } 424 425 static DecodeStatus DecodeLoadIntPair(MCInst &Inst, unsigned insn, 426 uint64_t Address, 427 const MCDisassembler *Decoder) { 428 return DecodeMem(Inst, insn, Address, Decoder, true, 429 DecodeIntPairRegisterClass); 430 } 431 432 static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address, 433 const MCDisassembler *Decoder) { 434 return DecodeMem(Inst, insn, Address, Decoder, true, 435 DecodeFPRegsRegisterClass); 436 } 437 438 static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address, 439 const MCDisassembler *Decoder) { 440 return DecodeMem(Inst, insn, Address, Decoder, true, 441 DecodeDFPRegsRegisterClass); 442 } 443 444 static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address, 445 const MCDisassembler *Decoder) { 446 return DecodeMem(Inst, insn, Address, Decoder, true, 447 DecodeQFPRegsRegisterClass); 448 } 449 450 static DecodeStatus DecodeLoadCP(MCInst &Inst, unsigned insn, uint64_t Address, 451 const MCDisassembler *Decoder) { 452 return DecodeMem(Inst, insn, Address, Decoder, true, 453 DecodeCPRegsRegisterClass); 454 } 455 456 static DecodeStatus DecodeLoadCPPair(MCInst &Inst, unsigned insn, 457 uint64_t Address, 458 const MCDisassembler *Decoder) { 459 return DecodeMem(Inst, insn, Address, Decoder, true, 460 DecodeCPPairRegisterClass); 461 } 462 463 static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn, 464 uint64_t Address, 465 const MCDisassembler *Decoder) { 466 return DecodeMem(Inst, insn, Address, Decoder, false, 467 DecodeIntRegsRegisterClass); 468 } 469 470 static DecodeStatus DecodeStoreIntPair(MCInst &Inst, unsigned insn, 471 uint64_t Address, 472 const MCDisassembler *Decoder) { 473 return DecodeMem(Inst, insn, Address, Decoder, false, 474 DecodeIntPairRegisterClass); 475 } 476 477 static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn, uint64_t Address, 478 const MCDisassembler *Decoder) { 479 return DecodeMem(Inst, insn, Address, Decoder, false, 480 DecodeFPRegsRegisterClass); 481 } 482 483 static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn, 484 uint64_t Address, 485 const MCDisassembler *Decoder) { 486 return DecodeMem(Inst, insn, Address, Decoder, false, 487 DecodeDFPRegsRegisterClass); 488 } 489 490 static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn, 491 uint64_t Address, 492 const MCDisassembler *Decoder) { 493 return DecodeMem(Inst, insn, Address, Decoder, false, 494 DecodeQFPRegsRegisterClass); 495 } 496 497 static DecodeStatus DecodeStoreCP(MCInst &Inst, unsigned insn, uint64_t Address, 498 const MCDisassembler *Decoder) { 499 return DecodeMem(Inst, insn, Address, Decoder, false, 500 DecodeCPRegsRegisterClass); 501 } 502 503 static DecodeStatus DecodeStoreCPPair(MCInst &Inst, unsigned insn, 504 uint64_t Address, 505 const MCDisassembler *Decoder) { 506 return DecodeMem(Inst, insn, Address, Decoder, false, 507 DecodeCPPairRegisterClass); 508 } 509 510 static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch, 511 uint64_t Address, uint64_t Offset, 512 uint64_t Width, MCInst &MI, 513 const MCDisassembler *Decoder) { 514 return Decoder->tryAddingSymbolicOperand(MI, Value, Address, isBranch, Offset, 515 Width, /*InstSize=*/4); 516 } 517 518 static DecodeStatus DecodeCall(MCInst &MI, unsigned insn, uint64_t Address, 519 const MCDisassembler *Decoder) { 520 unsigned tgt = fieldFromInstruction(insn, 0, 30); 521 tgt <<= 2; 522 if (!tryAddingSymbolicOperand(tgt+Address, false, Address, 523 0, 30, MI, Decoder)) 524 MI.addOperand(MCOperand::createImm(tgt)); 525 return MCDisassembler::Success; 526 } 527 528 static DecodeStatus DecodeSIMM13(MCInst &MI, unsigned insn, uint64_t Address, 529 const MCDisassembler *Decoder) { 530 unsigned tgt = SignExtend32<13>(fieldFromInstruction(insn, 0, 13)); 531 MI.addOperand(MCOperand::createImm(tgt)); 532 return MCDisassembler::Success; 533 } 534 535 static DecodeStatus DecodeJMPL(MCInst &MI, unsigned insn, uint64_t Address, 536 const MCDisassembler *Decoder) { 537 538 unsigned rd = fieldFromInstruction(insn, 25, 5); 539 unsigned rs1 = fieldFromInstruction(insn, 14, 5); 540 unsigned isImm = fieldFromInstruction(insn, 13, 1); 541 unsigned rs2 = 0; 542 unsigned simm13 = 0; 543 if (isImm) 544 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13)); 545 else 546 rs2 = fieldFromInstruction(insn, 0, 5); 547 548 // Decode RD. 549 DecodeStatus status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder); 550 if (status != MCDisassembler::Success) 551 return status; 552 553 // Decode RS1. 554 status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); 555 if (status != MCDisassembler::Success) 556 return status; 557 558 // Decode RS1 | SIMM13. 559 if (isImm) 560 MI.addOperand(MCOperand::createImm(simm13)); 561 else { 562 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); 563 if (status != MCDisassembler::Success) 564 return status; 565 } 566 return MCDisassembler::Success; 567 } 568 569 static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address, 570 const MCDisassembler *Decoder) { 571 572 unsigned rs1 = fieldFromInstruction(insn, 14, 5); 573 unsigned isImm = fieldFromInstruction(insn, 13, 1); 574 unsigned rs2 = 0; 575 unsigned simm13 = 0; 576 if (isImm) 577 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13)); 578 else 579 rs2 = fieldFromInstruction(insn, 0, 5); 580 581 // Decode RS1. 582 DecodeStatus status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); 583 if (status != MCDisassembler::Success) 584 return status; 585 586 // Decode RS2 | SIMM13. 587 if (isImm) 588 MI.addOperand(MCOperand::createImm(simm13)); 589 else { 590 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); 591 if (status != MCDisassembler::Success) 592 return status; 593 } 594 return MCDisassembler::Success; 595 } 596 597 // This instruction does not have a working decoder, and needs to be 598 // fixed. This "fixme" function was introduced to keep the backend compiling, 599 // while making changes to tablegen code. 600 static DecodeStatus DecodeFIXMEInstruction(MCInst &Inst, unsigned Insn, 601 uint64_t Address, 602 const MCDisassembler *Decoder) { 603 return MCDisassembler::Fail; 604 } 605 606 static DecodeStatus DecodeSWAP(MCInst &MI, unsigned insn, uint64_t Address, 607 const MCDisassembler *Decoder) { 608 609 unsigned rd = fieldFromInstruction(insn, 25, 5); 610 unsigned rs1 = fieldFromInstruction(insn, 14, 5); 611 unsigned isImm = fieldFromInstruction(insn, 13, 1); 612 bool hasAsi = fieldFromInstruction(insn, 23, 1); // (in op3 field) 613 unsigned asi = fieldFromInstruction(insn, 5, 8); 614 unsigned rs2 = 0; 615 unsigned simm13 = 0; 616 if (isImm) 617 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13)); 618 else 619 rs2 = fieldFromInstruction(insn, 0, 5); 620 621 // Decode RD. 622 DecodeStatus status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder); 623 if (status != MCDisassembler::Success) 624 return status; 625 626 // Decode RS1. 627 status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); 628 if (status != MCDisassembler::Success) 629 return status; 630 631 // Decode RS1 | SIMM13. 632 if (isImm) 633 MI.addOperand(MCOperand::createImm(simm13)); 634 else { 635 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); 636 if (status != MCDisassembler::Success) 637 return status; 638 } 639 640 if (hasAsi) 641 MI.addOperand(MCOperand::createImm(asi)); 642 643 return MCDisassembler::Success; 644 } 645 646 static DecodeStatus DecodeTRAP(MCInst &MI, unsigned insn, uint64_t Address, 647 const MCDisassembler *Decoder) { 648 649 unsigned rs1 = fieldFromInstruction(insn, 14, 5); 650 unsigned isImm = fieldFromInstruction(insn, 13, 1); 651 unsigned cc =fieldFromInstruction(insn, 25, 4); 652 unsigned rs2 = 0; 653 unsigned imm7 = 0; 654 if (isImm) 655 imm7 = fieldFromInstruction(insn, 0, 7); 656 else 657 rs2 = fieldFromInstruction(insn, 0, 5); 658 659 // Decode RS1. 660 DecodeStatus status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); 661 if (status != MCDisassembler::Success) 662 return status; 663 664 // Decode RS1 | IMM7. 665 if (isImm) 666 MI.addOperand(MCOperand::createImm(imm7)); 667 else { 668 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); 669 if (status != MCDisassembler::Success) 670 return status; 671 } 672 673 // Decode CC 674 MI.addOperand(MCOperand::createImm(cc)); 675 676 return MCDisassembler::Success; 677 } 678