1 //===- SparcDisassembler.cpp - Disassembler for Sparc -----------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file is part of the Sparc Disassembler. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "MCTargetDesc/SparcMCTargetDesc.h" 14 #include "llvm/MC/MCAsmInfo.h" 15 #include "llvm/MC/MCContext.h" 16 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 17 #include "llvm/MC/MCFixedLenDisassembler.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/Support/TargetRegistry.h" 20 21 using namespace llvm; 22 23 #define DEBUG_TYPE "sparc-disassembler" 24 25 typedef MCDisassembler::DecodeStatus DecodeStatus; 26 27 namespace { 28 29 /// A disassembler class for Sparc. 30 class SparcDisassembler : public MCDisassembler { 31 public: 32 SparcDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) 33 : MCDisassembler(STI, Ctx) {} 34 virtual ~SparcDisassembler() {} 35 36 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 37 ArrayRef<uint8_t> Bytes, uint64_t Address, 38 raw_ostream &VStream, 39 raw_ostream &CStream) const override; 40 }; 41 } 42 43 namespace llvm { 44 Target &getTheSparcTarget(); 45 Target &getTheSparcV9Target(); 46 Target &getTheSparcelTarget(); 47 } 48 49 static MCDisassembler *createSparcDisassembler(const Target &T, 50 const MCSubtargetInfo &STI, 51 MCContext &Ctx) { 52 return new SparcDisassembler(STI, Ctx); 53 } 54 55 56 extern "C" void LLVMInitializeSparcDisassembler() { 57 // Register the disassembler. 58 TargetRegistry::RegisterMCDisassembler(getTheSparcTarget(), 59 createSparcDisassembler); 60 TargetRegistry::RegisterMCDisassembler(getTheSparcV9Target(), 61 createSparcDisassembler); 62 TargetRegistry::RegisterMCDisassembler(getTheSparcelTarget(), 63 createSparcDisassembler); 64 } 65 66 static const unsigned IntRegDecoderTable[] = { 67 SP::G0, SP::G1, SP::G2, SP::G3, 68 SP::G4, SP::G5, SP::G6, SP::G7, 69 SP::O0, SP::O1, SP::O2, SP::O3, 70 SP::O4, SP::O5, SP::O6, SP::O7, 71 SP::L0, SP::L1, SP::L2, SP::L3, 72 SP::L4, SP::L5, SP::L6, SP::L7, 73 SP::I0, SP::I1, SP::I2, SP::I3, 74 SP::I4, SP::I5, SP::I6, SP::I7 }; 75 76 static const unsigned FPRegDecoderTable[] = { 77 SP::F0, SP::F1, SP::F2, SP::F3, 78 SP::F4, SP::F5, SP::F6, SP::F7, 79 SP::F8, SP::F9, SP::F10, SP::F11, 80 SP::F12, SP::F13, SP::F14, SP::F15, 81 SP::F16, SP::F17, SP::F18, SP::F19, 82 SP::F20, SP::F21, SP::F22, SP::F23, 83 SP::F24, SP::F25, SP::F26, SP::F27, 84 SP::F28, SP::F29, SP::F30, SP::F31 }; 85 86 static const unsigned DFPRegDecoderTable[] = { 87 SP::D0, SP::D16, SP::D1, SP::D17, 88 SP::D2, SP::D18, SP::D3, SP::D19, 89 SP::D4, SP::D20, SP::D5, SP::D21, 90 SP::D6, SP::D22, SP::D7, SP::D23, 91 SP::D8, SP::D24, SP::D9, SP::D25, 92 SP::D10, SP::D26, SP::D11, SP::D27, 93 SP::D12, SP::D28, SP::D13, SP::D29, 94 SP::D14, SP::D30, SP::D15, SP::D31 }; 95 96 static const unsigned QFPRegDecoderTable[] = { 97 SP::Q0, SP::Q8, ~0U, ~0U, 98 SP::Q1, SP::Q9, ~0U, ~0U, 99 SP::Q2, SP::Q10, ~0U, ~0U, 100 SP::Q3, SP::Q11, ~0U, ~0U, 101 SP::Q4, SP::Q12, ~0U, ~0U, 102 SP::Q5, SP::Q13, ~0U, ~0U, 103 SP::Q6, SP::Q14, ~0U, ~0U, 104 SP::Q7, SP::Q15, ~0U, ~0U } ; 105 106 static const unsigned FCCRegDecoderTable[] = { 107 SP::FCC0, SP::FCC1, SP::FCC2, SP::FCC3 }; 108 109 static const unsigned ASRRegDecoderTable[] = { 110 SP::Y, SP::ASR1, SP::ASR2, SP::ASR3, 111 SP::ASR4, SP::ASR5, SP::ASR6, SP::ASR7, 112 SP::ASR8, SP::ASR9, SP::ASR10, SP::ASR11, 113 SP::ASR12, SP::ASR13, SP::ASR14, SP::ASR15, 114 SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19, 115 SP::ASR20, SP::ASR21, SP::ASR22, SP::ASR23, 116 SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27, 117 SP::ASR28, SP::ASR29, SP::ASR30, SP::ASR31}; 118 119 static const unsigned PRRegDecoderTable[] = { 120 SP::TPC, SP::TNPC, SP::TSTATE, SP::TT, SP::TICK, SP::TBA, SP::PSTATE, 121 SP::TL, SP::PIL, SP::CWP, SP::CANSAVE, SP::CANRESTORE, SP::CLEANWIN, 122 SP::OTHERWIN, SP::WSTATE 123 }; 124 125 static const uint16_t IntPairDecoderTable[] = { 126 SP::G0_G1, SP::G2_G3, SP::G4_G5, SP::G6_G7, 127 SP::O0_O1, SP::O2_O3, SP::O4_O5, SP::O6_O7, 128 SP::L0_L1, SP::L2_L3, SP::L4_L5, SP::L6_L7, 129 SP::I0_I1, SP::I2_I3, SP::I4_I5, SP::I6_I7, 130 }; 131 132 static const unsigned CPRegDecoderTable[] = { 133 SP::C0, SP::C1, SP::C2, SP::C3, 134 SP::C4, SP::C5, SP::C6, SP::C7, 135 SP::C8, SP::C9, SP::C10, SP::C11, 136 SP::C12, SP::C13, SP::C14, SP::C15, 137 SP::C16, SP::C17, SP::C18, SP::C19, 138 SP::C20, SP::C21, SP::C22, SP::C23, 139 SP::C24, SP::C25, SP::C26, SP::C27, 140 SP::C28, SP::C29, SP::C30, SP::C31 141 }; 142 143 144 static const uint16_t CPPairDecoderTable[] = { 145 SP::C0_C1, SP::C2_C3, SP::C4_C5, SP::C6_C7, 146 SP::C8_C9, SP::C10_C11, SP::C12_C13, SP::C14_C15, 147 SP::C16_C17, SP::C18_C19, SP::C20_C21, SP::C22_C23, 148 SP::C24_C25, SP::C26_C27, SP::C28_C29, SP::C30_C31 149 }; 150 151 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, 152 unsigned RegNo, 153 uint64_t Address, 154 const void *Decoder) { 155 if (RegNo > 31) 156 return MCDisassembler::Fail; 157 unsigned Reg = IntRegDecoderTable[RegNo]; 158 Inst.addOperand(MCOperand::createReg(Reg)); 159 return MCDisassembler::Success; 160 } 161 162 static DecodeStatus DecodeI64RegsRegisterClass(MCInst &Inst, 163 unsigned RegNo, 164 uint64_t Address, 165 const void *Decoder) { 166 if (RegNo > 31) 167 return MCDisassembler::Fail; 168 unsigned Reg = IntRegDecoderTable[RegNo]; 169 Inst.addOperand(MCOperand::createReg(Reg)); 170 return MCDisassembler::Success; 171 } 172 173 174 static DecodeStatus DecodeFPRegsRegisterClass(MCInst &Inst, 175 unsigned RegNo, 176 uint64_t Address, 177 const void *Decoder) { 178 if (RegNo > 31) 179 return MCDisassembler::Fail; 180 unsigned Reg = FPRegDecoderTable[RegNo]; 181 Inst.addOperand(MCOperand::createReg(Reg)); 182 return MCDisassembler::Success; 183 } 184 185 186 static DecodeStatus DecodeDFPRegsRegisterClass(MCInst &Inst, 187 unsigned RegNo, 188 uint64_t Address, 189 const void *Decoder) { 190 if (RegNo > 31) 191 return MCDisassembler::Fail; 192 unsigned Reg = DFPRegDecoderTable[RegNo]; 193 Inst.addOperand(MCOperand::createReg(Reg)); 194 return MCDisassembler::Success; 195 } 196 197 198 static DecodeStatus DecodeQFPRegsRegisterClass(MCInst &Inst, 199 unsigned RegNo, 200 uint64_t Address, 201 const void *Decoder) { 202 if (RegNo > 31) 203 return MCDisassembler::Fail; 204 205 unsigned Reg = QFPRegDecoderTable[RegNo]; 206 if (Reg == ~0U) 207 return MCDisassembler::Fail; 208 Inst.addOperand(MCOperand::createReg(Reg)); 209 return MCDisassembler::Success; 210 } 211 212 static DecodeStatus DecodeCPRegsRegisterClass(MCInst &Inst, 213 unsigned RegNo, 214 uint64_t Address, 215 const void *Decoder) { 216 if (RegNo > 31) 217 return MCDisassembler::Fail; 218 unsigned Reg = CPRegDecoderTable[RegNo]; 219 Inst.addOperand(MCOperand::createReg(Reg)); 220 return MCDisassembler::Success; 221 } 222 223 static DecodeStatus DecodeFCCRegsRegisterClass(MCInst &Inst, unsigned RegNo, 224 uint64_t Address, 225 const void *Decoder) { 226 if (RegNo > 3) 227 return MCDisassembler::Fail; 228 Inst.addOperand(MCOperand::createReg(FCCRegDecoderTable[RegNo])); 229 return MCDisassembler::Success; 230 } 231 232 static DecodeStatus DecodeASRRegsRegisterClass(MCInst &Inst, unsigned RegNo, 233 uint64_t Address, 234 const void *Decoder) { 235 if (RegNo > 31) 236 return MCDisassembler::Fail; 237 Inst.addOperand(MCOperand::createReg(ASRRegDecoderTable[RegNo])); 238 return MCDisassembler::Success; 239 } 240 241 static DecodeStatus DecodePRRegsRegisterClass(MCInst &Inst, unsigned RegNo, 242 uint64_t Address, 243 const void *Decoder) { 244 if (RegNo >= array_lengthof(PRRegDecoderTable)) 245 return MCDisassembler::Fail; 246 Inst.addOperand(MCOperand::createReg(PRRegDecoderTable[RegNo])); 247 return MCDisassembler::Success; 248 } 249 250 static DecodeStatus DecodeIntPairRegisterClass(MCInst &Inst, unsigned RegNo, 251 uint64_t Address, const void *Decoder) { 252 DecodeStatus S = MCDisassembler::Success; 253 254 if (RegNo > 31) 255 return MCDisassembler::Fail; 256 257 if ((RegNo & 1)) 258 S = MCDisassembler::SoftFail; 259 260 unsigned RegisterPair = IntPairDecoderTable[RegNo/2]; 261 Inst.addOperand(MCOperand::createReg(RegisterPair)); 262 return S; 263 } 264 265 static DecodeStatus DecodeCPPairRegisterClass(MCInst &Inst, unsigned RegNo, 266 uint64_t Address, const void *Decoder) { 267 if (RegNo > 31) 268 return MCDisassembler::Fail; 269 270 unsigned RegisterPair = CPPairDecoderTable[RegNo/2]; 271 Inst.addOperand(MCOperand::createReg(RegisterPair)); 272 return MCDisassembler::Success; 273 } 274 275 static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address, 276 const void *Decoder); 277 static DecodeStatus DecodeLoadIntPair(MCInst &Inst, unsigned insn, uint64_t Address, 278 const void *Decoder); 279 static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address, 280 const void *Decoder); 281 static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address, 282 const void *Decoder); 283 static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address, 284 const void *Decoder); 285 static DecodeStatus DecodeLoadCP(MCInst &Inst, unsigned insn, uint64_t Address, 286 const void *Decoder); 287 static DecodeStatus DecodeLoadCPPair(MCInst &Inst, unsigned insn, uint64_t Address, 288 const void *Decoder); 289 static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn, 290 uint64_t Address, const void *Decoder); 291 static DecodeStatus DecodeStoreIntPair(MCInst &Inst, unsigned insn, 292 uint64_t Address, const void *Decoder); 293 static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn, 294 uint64_t Address, const void *Decoder); 295 static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn, 296 uint64_t Address, const void *Decoder); 297 static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn, 298 uint64_t Address, const void *Decoder); 299 static DecodeStatus DecodeStoreCP(MCInst &Inst, unsigned insn, 300 uint64_t Address, const void *Decoder); 301 static DecodeStatus DecodeStoreCPPair(MCInst &Inst, unsigned insn, 302 uint64_t Address, const void *Decoder); 303 static DecodeStatus DecodeCall(MCInst &Inst, unsigned insn, 304 uint64_t Address, const void *Decoder); 305 static DecodeStatus DecodeSIMM13(MCInst &Inst, unsigned insn, 306 uint64_t Address, const void *Decoder); 307 static DecodeStatus DecodeJMPL(MCInst &Inst, unsigned insn, uint64_t Address, 308 const void *Decoder); 309 static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address, 310 const void *Decoder); 311 static DecodeStatus DecodeSWAP(MCInst &Inst, unsigned insn, uint64_t Address, 312 const void *Decoder); 313 static DecodeStatus DecodeTRAP(MCInst &Inst, unsigned insn, uint64_t Address, 314 const void *Decoder); 315 316 #include "SparcGenDisassemblerTables.inc" 317 318 /// Read four bytes from the ArrayRef and return 32 bit word. 319 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, 320 uint64_t &Size, uint32_t &Insn, 321 bool IsLittleEndian) { 322 // We want to read exactly 4 Bytes of data. 323 if (Bytes.size() < 4) { 324 Size = 0; 325 return MCDisassembler::Fail; 326 } 327 328 Insn = IsLittleEndian 329 ? (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | 330 (Bytes[3] << 24) 331 : (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | 332 (Bytes[0] << 24); 333 334 return MCDisassembler::Success; 335 } 336 337 DecodeStatus SparcDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, 338 ArrayRef<uint8_t> Bytes, 339 uint64_t Address, 340 raw_ostream &VStream, 341 raw_ostream &CStream) const { 342 uint32_t Insn; 343 bool isLittleEndian = getContext().getAsmInfo()->isLittleEndian(); 344 DecodeStatus Result = 345 readInstruction32(Bytes, Address, Size, Insn, isLittleEndian); 346 if (Result == MCDisassembler::Fail) 347 return MCDisassembler::Fail; 348 349 // Calling the auto-generated decoder function. 350 351 if (STI.getFeatureBits()[Sparc::FeatureV9]) 352 { 353 Result = decodeInstruction(DecoderTableSparcV932, Instr, Insn, Address, this, STI); 354 } 355 else 356 { 357 Result = decodeInstruction(DecoderTableSparcV832, Instr, Insn, Address, this, STI); 358 } 359 if (Result != MCDisassembler::Fail) 360 return Result; 361 362 Result = 363 decodeInstruction(DecoderTableSparc32, Instr, Insn, Address, this, STI); 364 365 if (Result != MCDisassembler::Fail) { 366 Size = 4; 367 return Result; 368 } 369 370 return MCDisassembler::Fail; 371 } 372 373 374 typedef DecodeStatus (*DecodeFunc)(MCInst &MI, unsigned insn, uint64_t Address, 375 const void *Decoder); 376 377 static DecodeStatus DecodeMem(MCInst &MI, unsigned insn, uint64_t Address, 378 const void *Decoder, 379 bool isLoad, DecodeFunc DecodeRD) { 380 unsigned rd = fieldFromInstruction(insn, 25, 5); 381 unsigned rs1 = fieldFromInstruction(insn, 14, 5); 382 bool isImm = fieldFromInstruction(insn, 13, 1); 383 bool hasAsi = fieldFromInstruction(insn, 23, 1); // (in op3 field) 384 unsigned asi = fieldFromInstruction(insn, 5, 8); 385 unsigned rs2 = 0; 386 unsigned simm13 = 0; 387 if (isImm) 388 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13)); 389 else 390 rs2 = fieldFromInstruction(insn, 0, 5); 391 392 DecodeStatus status; 393 if (isLoad) { 394 status = DecodeRD(MI, rd, Address, Decoder); 395 if (status != MCDisassembler::Success) 396 return status; 397 } 398 399 // Decode rs1. 400 status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); 401 if (status != MCDisassembler::Success) 402 return status; 403 404 // Decode imm|rs2. 405 if (isImm) 406 MI.addOperand(MCOperand::createImm(simm13)); 407 else { 408 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); 409 if (status != MCDisassembler::Success) 410 return status; 411 } 412 413 if (hasAsi) 414 MI.addOperand(MCOperand::createImm(asi)); 415 416 if (!isLoad) { 417 status = DecodeRD(MI, rd, Address, Decoder); 418 if (status != MCDisassembler::Success) 419 return status; 420 } 421 return MCDisassembler::Success; 422 } 423 424 static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address, 425 const void *Decoder) { 426 return DecodeMem(Inst, insn, Address, Decoder, true, 427 DecodeIntRegsRegisterClass); 428 } 429 430 static DecodeStatus DecodeLoadIntPair(MCInst &Inst, unsigned insn, uint64_t Address, 431 const void *Decoder) { 432 return DecodeMem(Inst, insn, Address, Decoder, true, 433 DecodeIntPairRegisterClass); 434 } 435 436 static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address, 437 const void *Decoder) { 438 return DecodeMem(Inst, insn, Address, Decoder, true, 439 DecodeFPRegsRegisterClass); 440 } 441 442 static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address, 443 const void *Decoder) { 444 return DecodeMem(Inst, insn, Address, Decoder, true, 445 DecodeDFPRegsRegisterClass); 446 } 447 448 static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address, 449 const void *Decoder) { 450 return DecodeMem(Inst, insn, Address, Decoder, true, 451 DecodeQFPRegsRegisterClass); 452 } 453 454 static DecodeStatus DecodeLoadCP(MCInst &Inst, unsigned insn, uint64_t Address, 455 const void *Decoder) { 456 return DecodeMem(Inst, insn, Address, Decoder, true, 457 DecodeCPRegsRegisterClass); 458 } 459 460 static DecodeStatus DecodeLoadCPPair(MCInst &Inst, unsigned insn, uint64_t Address, 461 const void *Decoder) { 462 return DecodeMem(Inst, insn, Address, Decoder, true, 463 DecodeCPPairRegisterClass); 464 } 465 466 static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn, 467 uint64_t Address, const void *Decoder) { 468 return DecodeMem(Inst, insn, Address, Decoder, false, 469 DecodeIntRegsRegisterClass); 470 } 471 472 static DecodeStatus DecodeStoreIntPair(MCInst &Inst, unsigned insn, 473 uint64_t Address, const void *Decoder) { 474 return DecodeMem(Inst, insn, Address, Decoder, false, 475 DecodeIntPairRegisterClass); 476 } 477 478 static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn, uint64_t Address, 479 const void *Decoder) { 480 return DecodeMem(Inst, insn, Address, Decoder, false, 481 DecodeFPRegsRegisterClass); 482 } 483 484 static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn, 485 uint64_t Address, const void *Decoder) { 486 return DecodeMem(Inst, insn, Address, Decoder, false, 487 DecodeDFPRegsRegisterClass); 488 } 489 490 static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn, 491 uint64_t Address, const void *Decoder) { 492 return DecodeMem(Inst, insn, Address, Decoder, false, 493 DecodeQFPRegsRegisterClass); 494 } 495 496 static DecodeStatus DecodeStoreCP(MCInst &Inst, unsigned insn, 497 uint64_t Address, const void *Decoder) { 498 return DecodeMem(Inst, insn, Address, Decoder, false, 499 DecodeCPRegsRegisterClass); 500 } 501 502 static DecodeStatus DecodeStoreCPPair(MCInst &Inst, unsigned insn, 503 uint64_t Address, const void *Decoder) { 504 return DecodeMem(Inst, insn, Address, Decoder, false, 505 DecodeCPPairRegisterClass); 506 } 507 508 static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch, 509 uint64_t Address, uint64_t Offset, 510 uint64_t Width, MCInst &MI, 511 const void *Decoder) { 512 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 513 return Dis->tryAddingSymbolicOperand(MI, Value, Address, isBranch, 514 Offset, Width); 515 } 516 517 static DecodeStatus DecodeCall(MCInst &MI, unsigned insn, 518 uint64_t Address, const void *Decoder) { 519 unsigned tgt = fieldFromInstruction(insn, 0, 30); 520 tgt <<= 2; 521 if (!tryAddingSymbolicOperand(tgt+Address, false, Address, 522 0, 30, MI, Decoder)) 523 MI.addOperand(MCOperand::createImm(tgt)); 524 return MCDisassembler::Success; 525 } 526 527 static DecodeStatus DecodeSIMM13(MCInst &MI, unsigned insn, 528 uint64_t Address, const void *Decoder) { 529 unsigned tgt = SignExtend32<13>(fieldFromInstruction(insn, 0, 13)); 530 MI.addOperand(MCOperand::createImm(tgt)); 531 return MCDisassembler::Success; 532 } 533 534 static DecodeStatus DecodeJMPL(MCInst &MI, unsigned insn, uint64_t Address, 535 const void *Decoder) { 536 537 unsigned rd = fieldFromInstruction(insn, 25, 5); 538 unsigned rs1 = fieldFromInstruction(insn, 14, 5); 539 unsigned isImm = fieldFromInstruction(insn, 13, 1); 540 unsigned rs2 = 0; 541 unsigned simm13 = 0; 542 if (isImm) 543 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13)); 544 else 545 rs2 = fieldFromInstruction(insn, 0, 5); 546 547 // Decode RD. 548 DecodeStatus status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder); 549 if (status != MCDisassembler::Success) 550 return status; 551 552 // Decode RS1. 553 status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); 554 if (status != MCDisassembler::Success) 555 return status; 556 557 // Decode RS1 | SIMM13. 558 if (isImm) 559 MI.addOperand(MCOperand::createImm(simm13)); 560 else { 561 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); 562 if (status != MCDisassembler::Success) 563 return status; 564 } 565 return MCDisassembler::Success; 566 } 567 568 static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address, 569 const void *Decoder) { 570 571 unsigned rs1 = fieldFromInstruction(insn, 14, 5); 572 unsigned isImm = fieldFromInstruction(insn, 13, 1); 573 unsigned rs2 = 0; 574 unsigned simm13 = 0; 575 if (isImm) 576 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13)); 577 else 578 rs2 = fieldFromInstruction(insn, 0, 5); 579 580 // Decode RS1. 581 DecodeStatus status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); 582 if (status != MCDisassembler::Success) 583 return status; 584 585 // Decode RS2 | SIMM13. 586 if (isImm) 587 MI.addOperand(MCOperand::createImm(simm13)); 588 else { 589 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); 590 if (status != MCDisassembler::Success) 591 return status; 592 } 593 return MCDisassembler::Success; 594 } 595 596 static DecodeStatus DecodeSWAP(MCInst &MI, unsigned insn, uint64_t Address, 597 const void *Decoder) { 598 599 unsigned rd = fieldFromInstruction(insn, 25, 5); 600 unsigned rs1 = fieldFromInstruction(insn, 14, 5); 601 unsigned isImm = fieldFromInstruction(insn, 13, 1); 602 bool hasAsi = fieldFromInstruction(insn, 23, 1); // (in op3 field) 603 unsigned asi = fieldFromInstruction(insn, 5, 8); 604 unsigned rs2 = 0; 605 unsigned simm13 = 0; 606 if (isImm) 607 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13)); 608 else 609 rs2 = fieldFromInstruction(insn, 0, 5); 610 611 // Decode RD. 612 DecodeStatus status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder); 613 if (status != MCDisassembler::Success) 614 return status; 615 616 // Decode RS1. 617 status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); 618 if (status != MCDisassembler::Success) 619 return status; 620 621 // Decode RS1 | SIMM13. 622 if (isImm) 623 MI.addOperand(MCOperand::createImm(simm13)); 624 else { 625 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); 626 if (status != MCDisassembler::Success) 627 return status; 628 } 629 630 if (hasAsi) 631 MI.addOperand(MCOperand::createImm(asi)); 632 633 return MCDisassembler::Success; 634 } 635 636 static DecodeStatus DecodeTRAP(MCInst &MI, unsigned insn, uint64_t Address, 637 const void *Decoder) { 638 639 unsigned rs1 = fieldFromInstruction(insn, 14, 5); 640 unsigned isImm = fieldFromInstruction(insn, 13, 1); 641 unsigned cc =fieldFromInstruction(insn, 25, 4); 642 unsigned rs2 = 0; 643 unsigned imm7 = 0; 644 if (isImm) 645 imm7 = fieldFromInstruction(insn, 0, 7); 646 else 647 rs2 = fieldFromInstruction(insn, 0, 5); 648 649 // Decode RS1. 650 DecodeStatus status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); 651 if (status != MCDisassembler::Success) 652 return status; 653 654 // Decode RS1 | IMM7. 655 if (isImm) 656 MI.addOperand(MCOperand::createImm(imm7)); 657 else { 658 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); 659 if (status != MCDisassembler::Success) 660 return status; 661 } 662 663 // Decode CC 664 MI.addOperand(MCOperand::createImm(cc)); 665 666 return MCDisassembler::Success; 667 } 668