1//===- RISCVScheduleV.td - RISC-V Scheduling Definitions V -*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10/// Define scheduler resources associated with def operands. 11 12// This predicate is true when the rs2 operand of vlse or vsse is x0, false 13// otherwise. 14def VLDSX0Pred : MCSchedPredicate<CheckRegOperand<3, X0>>; 15 16defvar SchedMxList = ["MF8", "MF4", "MF2", "M1", "M2", "M4", "M8"]; 17// Used for widening and narrowing instructions as it doesn't contain M8. 18defvar SchedMxListW = !listremove(SchedMxList, ["M8"]); 19// Used for widening reductions, which does contain M8. 20defvar SchedMxListWRed = SchedMxList; 21defvar SchedMxListFW = !listremove(SchedMxList, ["M8", "MF8"]); 22// Used for floating-point as it doesn't contain MF8. 23defvar SchedMxListF = !listremove(SchedMxList, ["MF8"]); 24// Used for widening floating-point Reduction as it doesn't contain MF8. 25defvar SchedMxListFWRed = SchedMxListF; 26 27class SchedSEWSet<string mx, bit isF = 0, bit isWidening = 0> { 28 assert !or(!not(isF), !ne(mx, "MF8")), "LMUL shouldn't be MF8 for floating-point"; 29 defvar t = !cond(!eq(mx, "M1"): [8, 16, 32, 64], 30 !eq(mx, "M2"): [8, 16, 32, 64], 31 !eq(mx, "M4"): [8, 16, 32, 64], 32 !eq(mx, "M8"): [8, 16, 32, 64], 33 !eq(mx, "MF2"): [8, 16, 32], 34 !eq(mx, "MF4"): [8, 16], 35 !eq(mx, "MF8"): [8]); 36 // For floating-point instructions, SEW won't be 8. 37 defvar remove8 = !if(isF, !listremove(t, [8]), t); 38 // For widening instructions, SEW will not be 64. 39 defvar remove64 = !if(isWidening, !listremove(remove8, [64]), remove8); 40 list<int> val = remove64; 41} 42 43// Helper function to get the largest LMUL from MxList 44// Precondition: MxList is sorted in ascending LMUL order. 45class LargestLMUL<list<string> MxList> { 46 // MX list is sorted from smallest to largest 47 string r = !foldl(!head(MxList), MxList, last, curr, curr); 48} 49// Helper function to get the smallest SEW that can be used with LMUL mx 50// Precondition: MxList is sorted in ascending LMUL order and SchedSEWSet<mx> 51class SmallestSEW<string mx, bit isF = 0> { 52 int r = !head(SchedSEWSet<mx, isF>.val); 53} 54 55// Creates WriteRes for (name, mx, resources) tuple 56multiclass LMULWriteResMX<string name, list<ProcResourceKind> resources, 57 string mx, bit IsWorstCase> { 58 def : WriteRes<!cast<SchedWrite>(name # "_" # mx), resources>; 59 if IsWorstCase then 60 def : WriteRes<!cast<SchedWrite>(name # "_WorstCase"), resources>; 61} 62multiclass LMULSEWWriteResMXSEW<string name, list<ProcResourceKind> resources, 63 string mx, int sew, bit IsWorstCase> { 64 def : WriteRes<!cast<SchedWrite>(name # "_" # mx # "_E" # sew), resources>; 65 if IsWorstCase then 66 def : WriteRes<!cast<SchedWrite>(name # "_WorstCase"), resources>; 67} 68 69// Define a SchedAlias for the SchedWrite associated with (name, mx) whose 70// behavior is aliased to a Variant. The Variant has Latency predLad and 71// ReleaseAtCycles predCycles if the SchedPredicate Pred is true, otherwise has 72// Latency noPredLat and ReleaseAtCycles noPredCycles. The WorstCase SchedWrite 73// is created similiarly if IsWorstCase is true. 74multiclass LMULWriteResMXVariant<string name, SchedPredicateBase Pred, 75 list<ProcResourceKind> resources, 76 int predLat, list<int> predAcquireCycles, 77 list<int> predReleaseCycles, int noPredLat, 78 list<int> noPredAcquireCycles, 79 list<int> noPredReleaseCycles, 80 string mx, bit IsWorstCase> { 81 defvar nameMX = name # "_" # mx; 82 83 // Define the different behaviors 84 def nameMX # "_Pred" : SchedWriteRes<resources>{ 85 let Latency = predLat; 86 let AcquireAtCycles = predAcquireCycles; 87 let ReleaseAtCycles = predReleaseCycles; 88 } 89 def nameMX # "_NoPred" : SchedWriteRes<resources> { 90 let Latency = noPredLat; 91 let AcquireAtCycles = noPredAcquireCycles; 92 let ReleaseAtCycles = noPredReleaseCycles; 93 } 94 95 // Define SchedVars 96 def nameMX # PredSchedVar 97 : SchedVar<Pred, [!cast<SchedWriteRes>(NAME # nameMX # "_Pred")]>; 98 def nameMX # NoPredSchedVar 99 : SchedVar<NoSchedPred, [!cast<SchedWriteRes>(NAME # nameMX #"_NoPred")]>; 100 // Allow multiclass to refer to SchedVars -- need to have NAME prefix. 101 defvar PredSchedVar = !cast<SchedVar>(NAME # nameMX # PredSchedVar); 102 defvar NoPredSchedVar = !cast<SchedVar>(NAME # nameMX # NoPredSchedVar); 103 104 // Tie behavior to predicate 105 def NAME # nameMX # "_Variant" 106 : SchedWriteVariant<[PredSchedVar, NoPredSchedVar]>; 107 def : SchedAlias< 108 !cast<SchedReadWrite>(nameMX), 109 !cast<SchedReadWrite>(NAME # nameMX # "_Variant")>; 110 111 if IsWorstCase then { 112 def NAME # name # "_WorstCase_Variant" 113 : SchedWriteVariant<[PredSchedVar, NoPredSchedVar]>; 114 def : SchedAlias< 115 !cast<SchedReadWrite>(name # "_WorstCase"), 116 !cast<SchedReadWrite>(NAME # name # "_WorstCase_Variant")>; 117 } 118} 119 120// Define multiclasses to define SchedWrite, SchedRead, WriteRes, and 121// ReadAdvance for each (name, LMUL) pair and for each LMUL in each of the 122// SchedMxList variants above. Each multiclass is responsible for defining 123// a record that represents the WorseCase behavior for name. 124multiclass LMULSchedWritesImpl<string name, list<string> MxList> { 125 def name # "_WorstCase" : SchedWrite; 126 foreach mx = MxList in { 127 def name # "_" # mx : SchedWrite; 128 } 129} 130multiclass LMULSchedReadsImpl<string name, list<string> MxList> { 131 def name # "_WorstCase" : SchedRead; 132 foreach mx = MxList in { 133 def name # "_" # mx : SchedRead; 134 } 135} 136multiclass LMULWriteResImpl<string name, list<ProcResourceKind> resources> { 137 if !exists<SchedWrite>(name # "_WorstCase") then 138 def : WriteRes<!cast<SchedWrite>(name # "_WorstCase"), resources>; 139 foreach mx = SchedMxList in { 140 if !exists<SchedWrite>(name # "_" # mx) then 141 def : WriteRes<!cast<SchedWrite>(name # "_" # mx), resources>; 142 } 143} 144multiclass LMULReadAdvanceImpl<string name, int val, 145 list<SchedWrite> writes = []> { 146 if !exists<SchedRead>(name # "_WorstCase") then 147 def : ReadAdvance<!cast<SchedRead>(name # "_WorstCase"), val, writes>; 148 foreach mx = SchedMxList in { 149 if !exists<SchedRead>(name # "_" # mx) then 150 def : ReadAdvance<!cast<SchedRead>(name # "_" # mx), val, writes>; 151 } 152} 153 154// Define multiclasses to define SchedWrite, SchedRead, WriteRes, and 155// ReadAdvance for each (name, LMUL, SEW) tuple for each LMUL in each of the 156// SchedMxList variants above. Each multiclass is responsible for defining 157// a record that represents the WorseCase behavior for name. 158multiclass LMULSEWSchedWritesImpl<string name, list<string> MxList, bit isF = 0, 159 bit isWidening = 0> { 160 def name # "_WorstCase" : SchedWrite; 161 foreach mx = MxList in { 162 foreach sew = SchedSEWSet<mx, isF, isWidening>.val in 163 def name # "_" # mx # "_E" # sew : SchedWrite; 164 } 165} 166multiclass LMULSEWSchedReadsImpl<string name, list<string> MxList, bit isF = 0, 167 bit isWidening = 0> { 168 def name # "_WorstCase" : SchedRead; 169 foreach mx = MxList in { 170 foreach sew = SchedSEWSet<mx, isF, isWidening>.val in 171 def name # "_" # mx # "_E" # sew : SchedRead; 172 } 173} 174multiclass LMULSEWWriteResImpl<string name, list<ProcResourceKind> resources, 175 list<string> MxList, bit isF = 0, 176 bit isWidening = 0> { 177 if !exists<SchedWrite>(name # "_WorstCase") then 178 def : WriteRes<!cast<SchedWrite>(name # "_WorstCase"), resources>; 179 foreach mx = MxList in { 180 foreach sew = SchedSEWSet<mx, isF, isWidening>.val in 181 if !exists<SchedWrite>(name # "_" # mx # "_E" # sew) then 182 def : WriteRes<!cast<SchedWrite>(name # "_" # mx # "_E" # sew), resources>; 183 } 184} 185multiclass LMULSEWReadAdvanceImpl<string name, int val, list<SchedWrite> writes = [], 186 list<string> MxList, bit isF = 0, 187 bit isWidening = 0> { 188 if !exists<SchedRead>(name # "_WorstCase") then 189 def : ReadAdvance<!cast<SchedRead>(name # "_WorstCase"), val, writes>; 190 foreach mx = MxList in { 191 foreach sew = SchedSEWSet<mx, isF, isWidening>.val in 192 if !exists<SchedRead>(name # "_" # mx # "_E" # sew) then 193 def : ReadAdvance<!cast<SchedRead>(name # "_" # mx # "_E" # sew), val, writes>; 194 } 195} 196// Define classes to define list containing all SchedWrites for each (name, LMUL) 197// pair for each LMUL in each of the SchedMxList variants above and name in 198// argument `names`. These classes can be used to construct a list of existing 199// definitions of writes corresponding to each (name, LMUL) pair, that are needed 200// by the ReadAdvance. For example: 201// ``` 202// defm "" : LMULReadAdvance<"ReadVIALUX", 1, 203// LMULSchedWriteList<["WriteVMovSX"]>.value>; 204// ``` 205class LMULSchedWriteListImpl<list<string> names, list<string> MxList> { 206 list<SchedWrite> value = !foldl([]<SchedWrite>, 207 !foreach(name, names, 208 !foreach(mx, MxList, !cast<SchedWrite>(name # "_" # mx))), 209 all, writes, !listconcat(all, writes)); 210} 211 212multiclass LMULSchedWrites<string name> : LMULSchedWritesImpl<name, SchedMxList>; 213multiclass LMULSchedReads<string name> : LMULSchedReadsImpl<name, SchedMxList>; 214multiclass LMULWriteRes<string name, list<ProcResourceKind> resources> 215 : LMULWriteResImpl<name, resources>; 216multiclass LMULReadAdvance<string name, int val, list<SchedWrite> writes = []> 217 : LMULReadAdvanceImpl<name, val, writes>; 218class LMULSchedWriteList<list<string> names> : LMULSchedWriteListImpl<names, SchedMxList>; 219 220multiclass LMULSEWSchedWrites<string name> : LMULSEWSchedWritesImpl<name, SchedMxList>; 221multiclass LMULSEWSchedReads<string name> : LMULSEWSchedReadsImpl<name, SchedMxList>; 222multiclass LMULSEWWriteRes<string name, list<ProcResourceKind> resources> 223 : LMULSEWWriteResImpl<name, resources, SchedMxList>; 224multiclass LMULSEWReadAdvance<string name, int val, list<SchedWrite> writes = []> 225 : LMULSEWReadAdvanceImpl<name, val, writes, SchedMxList>; 226 227multiclass LMULSEWSchedWritesWRed<string name> 228 : LMULSEWSchedWritesImpl<name, SchedMxListWRed, isWidening=1>; 229multiclass LMULSEWWriteResWRed<string name, list<ProcResourceKind> resources> 230 : LMULSEWWriteResImpl<name, resources, SchedMxListWRed, isWidening=1>; 231 232multiclass LMULSEWSchedWritesFWRed<string name> 233 : LMULSEWSchedWritesImpl<name, SchedMxListFWRed, isF=1, isWidening=1>; 234multiclass LMULSEWWriteResFWRed<string name, list<ProcResourceKind> resources> 235 : LMULSEWWriteResImpl<name, resources, SchedMxListFWRed, isF=1, isWidening=1>; 236 237multiclass LMULSEWSchedWritesF<string name> : LMULSEWSchedWritesImpl<name, SchedMxListF, isF=1>; 238multiclass LMULSEWSchedReadsF<string name> : LMULSEWSchedReadsImpl<name, SchedMxListF, isF=1>; 239multiclass LMULSEWWriteResF<string name, list<ProcResourceKind> resources> 240 : LMULSEWWriteResImpl<name, resources, SchedMxListF, isF=1>; 241multiclass LMULSEWReadAdvanceF<string name, int val, list<SchedWrite> writes = []> 242 : LMULSEWReadAdvanceImpl<name, val, writes, SchedMxListF, isF=1>; 243 244multiclass LMULSchedWritesW<string name> : LMULSchedWritesImpl<name, SchedMxListW>; 245multiclass LMULSchedReadsW<string name> : LMULSchedReadsImpl<name, SchedMxListW>; 246multiclass LMULWriteResW<string name, list<ProcResourceKind> resources> 247 : LMULWriteResImpl<name, resources>; 248multiclass LMULReadAdvanceW<string name, int val, list<SchedWrite> writes = []> 249 : LMULReadAdvanceImpl<name, val, writes>; 250class LMULSchedWriteListW<list<string> names> : LMULSchedWriteListImpl<names, SchedMxListW>; 251 252multiclass LMULSchedWritesFW<string name> : LMULSchedWritesImpl<name, SchedMxListFW>; 253multiclass LMULSchedReadsFW<string name> : LMULSchedReadsImpl<name, SchedMxListFW>; 254multiclass LMULWriteResFW<string name, list<ProcResourceKind> resources> 255 : LMULWriteResImpl<name, resources>; 256multiclass LMULReadAdvanceFW<string name, int val, list<SchedWrite> writes = []> 257 : LMULReadAdvanceImpl<name, val, writes>; 258class LMULSchedWriteListFW<list<string> names> : LMULSchedWriteListImpl<names, SchedMxListFW>; 259 260multiclass LMULSEWSchedWritesW<string name> 261 : LMULSEWSchedWritesImpl<name, SchedMxListW, isF = 0, isWidening = 1>; 262multiclass LMULSEWSchedReadsW<string name> 263 : LMULSEWSchedReadsImpl<name, SchedMxListW, isF = 0, isWidening = 1>; 264multiclass LMULSEWWriteResW<string name, list<ProcResourceKind> resources> 265 : LMULSEWWriteResImpl<name, resources, SchedMxListW, isF = 0, 266 isWidening = 1>; 267multiclass 268 LMULSEWReadAdvanceW<string name, int val, list<SchedWrite> writes = []> 269 : LMULSEWReadAdvanceImpl<name, val, writes, SchedMxListW, isF = 0, 270 isWidening = 1>; 271 272multiclass LMULSEWSchedWritesFW<string name> 273 : LMULSEWSchedWritesImpl<name, SchedMxListFW, isF = 1, isWidening = 1>; 274multiclass LMULSEWSchedReadsFW<string name> 275 : LMULSEWSchedReadsImpl<name, SchedMxListFW, isF = 1, isWidening = 1>; 276multiclass LMULSEWWriteResFW<string name, list<ProcResourceKind> resources> 277 : LMULSEWWriteResImpl<name, resources, SchedMxListFW, isF = 1, 278 isWidening = 1>; 279multiclass 280 LMULSEWReadAdvanceFW<string name, int val, list<SchedWrite> writes = []> 281 : LMULSEWReadAdvanceImpl<name, val, writes, SchedMxListFW, isF = 1, 282 isWidening = 1>; 283 284// 3.6 Vector Byte Length vlenb 285def WriteRdVLENB : SchedWrite; 286 287// 6. Configuration-Setting Instructions 288def WriteVSETVLI : SchedWrite; 289def WriteVSETIVLI : SchedWrite; 290def WriteVSETVL : SchedWrite; 291 292// 7. Vector Loads and Stores 293// 7.4. Vector Unit-Stride Instructions 294defm "" : LMULSchedWrites<"WriteVLDE">; 295defm "" : LMULSchedWrites<"WriteVSTE">; 296// 7.4.1. Vector Unit-Strided Mask 297defm "" : LMULSchedWrites<"WriteVLDM">; 298defm "" : LMULSchedWrites<"WriteVSTM">; 299// 7.5. Vector Strided Instructions 300defm "" : LMULSchedWrites<"WriteVLDS8">; 301defm "" : LMULSchedWrites<"WriteVLDS16">; 302defm "" : LMULSchedWrites<"WriteVLDS32">; 303defm "" : LMULSchedWrites<"WriteVLDS64">; 304defm "" : LMULSchedWrites<"WriteVSTS8">; 305defm "" : LMULSchedWrites<"WriteVSTS16">; 306defm "" : LMULSchedWrites<"WriteVSTS32">; 307defm "" : LMULSchedWrites<"WriteVSTS64">; 308// 7.6. Vector Indexed Instructions 309defm "" : LMULSchedWrites<"WriteVLDUX8">; 310defm "" : LMULSchedWrites<"WriteVLDUX16">; 311defm "" : LMULSchedWrites<"WriteVLDUX32">; 312defm "" : LMULSchedWrites<"WriteVLDUX64">; 313defm "" : LMULSchedWrites<"WriteVLDOX8">; 314defm "" : LMULSchedWrites<"WriteVLDOX16">; 315defm "" : LMULSchedWrites<"WriteVLDOX32">; 316defm "" : LMULSchedWrites<"WriteVLDOX64">; 317defm "" : LMULSchedWrites<"WriteVSTUX8">; 318defm "" : LMULSchedWrites<"WriteVSTUX16">; 319defm "" : LMULSchedWrites<"WriteVSTUX32">; 320defm "" : LMULSchedWrites<"WriteVSTUX64">; 321defm "" : LMULSchedWrites<"WriteVSTOX8">; 322defm "" : LMULSchedWrites<"WriteVSTOX16">; 323defm "" : LMULSchedWrites<"WriteVSTOX32">; 324defm "" : LMULSchedWrites<"WriteVSTOX64">; 325// 7.7. Vector Unit-stride Fault-Only-First Loads 326defm "" : LMULSchedWrites<"WriteVLDFF">; 327// 7.8. Vector Segment Instructions 328foreach nf=2-8 in { 329 foreach eew = [8, 16, 32, 64] in { 330 defm "" : LMULSchedWrites<"WriteVLSEG" # nf # e # eew>; 331 defm "" : LMULSchedWrites<"WriteVSSEG" # nf # e # eew>; 332 defm "" : LMULSchedWrites<"WriteVLSEGFF" # nf # e # eew>; 333 defm "" : LMULSchedWrites<"WriteVLSSEG" # nf # e # eew>; 334 defm "" : LMULSchedWrites<"WriteVSSSEG" # nf # e # eew>; 335 defm "" : LMULSchedWrites<"WriteVLUXSEG" # nf # e # eew>; 336 defm "" : LMULSchedWrites<"WriteVLOXSEG" # nf # e # eew>; 337 defm "" : LMULSchedWrites<"WriteVSUXSEG" # nf # e # eew>; 338 defm "" : LMULSchedWrites<"WriteVSOXSEG" # nf # e # eew>; 339 } 340} 341// 7.9. Vector Whole Register Instructions 342def WriteVLD1R : SchedWrite; 343def WriteVLD2R : SchedWrite; 344def WriteVLD4R : SchedWrite; 345def WriteVLD8R : SchedWrite; 346def WriteVST1R : SchedWrite; 347def WriteVST2R : SchedWrite; 348def WriteVST4R : SchedWrite; 349def WriteVST8R : SchedWrite; 350 351// 11. Vector Integer Arithmetic Instructions 352// 11.1. Vector Single-Width Integer Add and Subtract 353// 11.5. Vector Bitwise Logical Instructions 354defm "" : LMULSchedWrites<"WriteVIALUV">; 355defm "" : LMULSchedWrites<"WriteVIALUX">; 356defm "" : LMULSchedWrites<"WriteVIALUI">; 357// 11.2. Vector Widening Integer Add/Subtract 358defm "" : LMULSchedWritesW<"WriteVIWALUV">; 359defm "" : LMULSchedWritesW<"WriteVIWALUX">; 360defm "" : LMULSchedWritesW<"WriteVIWALUI">; 361// 11.3. Vector Integer Extension 362defm "" : LMULSchedWrites<"WriteVExtV">; 363// 11.4. Vector Integer Arithmetic with Carry or Borrow Instructions 364defm "" : LMULSchedWrites<"WriteVICALUV">; 365defm "" : LMULSchedWrites<"WriteVICALUX">; 366defm "" : LMULSchedWrites<"WriteVICALUI">; 367defm "" : LMULSchedWrites<"WriteVICALUMV">; 368defm "" : LMULSchedWrites<"WriteVICALUMX">; 369defm "" : LMULSchedWrites<"WriteVICALUMI">; 370// 11.6. Vector Single-Width Bit Shift Instructions 371defm "" : LMULSchedWrites<"WriteVShiftV">; 372defm "" : LMULSchedWrites<"WriteVShiftX">; 373defm "" : LMULSchedWrites<"WriteVShiftI">; 374// 11.7. Vector Narrowing Integer Right Shift Instructions 375defm "" : LMULSchedWritesW<"WriteVNShiftV">; 376defm "" : LMULSchedWritesW<"WriteVNShiftX">; 377defm "" : LMULSchedWritesW<"WriteVNShiftI">; 378// 11.8. Vector Integer Comparison Instructions 379defm "" : LMULSchedWrites<"WriteVICmpV">; 380defm "" : LMULSchedWrites<"WriteVICmpX">; 381defm "" : LMULSchedWrites<"WriteVICmpI">; 382// 11.9. Vector Integer Min/Max Instructions 383defm "" : LMULSchedWrites<"WriteVIMinMaxV">; 384defm "" : LMULSchedWrites<"WriteVIMinMaxX">; 385// 11.10. Vector Single-Width Integer Multiply Instructions 386defm "" : LMULSchedWrites<"WriteVIMulV">; 387defm "" : LMULSchedWrites<"WriteVIMulX">; 388// 11.11. Vector Integer Divide Instructions 389defm "" : LMULSEWSchedWrites<"WriteVIDivV">; 390defm "" : LMULSEWSchedWrites<"WriteVIDivX">; 391// 11.12. Vector Widening Integer Multiply Instructions 392defm "" : LMULSchedWritesW<"WriteVIWMulV">; 393defm "" : LMULSchedWritesW<"WriteVIWMulX">; 394// 11.13. Vector Single-Width Integer Multiply-Add Instructions 395defm "" : LMULSchedWrites<"WriteVIMulAddV">; 396defm "" : LMULSchedWrites<"WriteVIMulAddX">; 397// 11.14. Vector Widening Integer Multiply-Add Instructions 398defm "" : LMULSchedWritesW<"WriteVIWMulAddV">; 399defm "" : LMULSchedWritesW<"WriteVIWMulAddX">; 400// 11.15. Vector Integer Merge Instructions 401defm "" : LMULSchedWrites<"WriteVIMergeV">; 402defm "" : LMULSchedWrites<"WriteVIMergeX">; 403defm "" : LMULSchedWrites<"WriteVIMergeI">; 404// 11.16. Vector Integer Move Instructions 405defm "" : LMULSchedWrites<"WriteVIMovV">; 406defm "" : LMULSchedWrites<"WriteVIMovX">; 407defm "" : LMULSchedWrites<"WriteVIMovI">; 408 409// 12. Vector Fixed-Point Arithmetic Instructions 410// 12.1. Vector Single-Width Saturating Add and Subtract 411defm "" : LMULSchedWrites<"WriteVSALUV">; 412defm "" : LMULSchedWrites<"WriteVSALUX">; 413defm "" : LMULSchedWrites<"WriteVSALUI">; 414// 12.2. Vector Single-Width Averaging Add and Subtract 415defm "" : LMULSchedWrites<"WriteVAALUV">; 416defm "" : LMULSchedWrites<"WriteVAALUX">; 417// 12.3. Vector Single-Width Fractional Multiply with Rounding and Saturation 418defm "" : LMULSchedWrites<"WriteVSMulV">; 419defm "" : LMULSchedWrites<"WriteVSMulX">; 420// 12.4. Vector Single-Width Scaling Shift Instructions 421defm "" : LMULSchedWrites<"WriteVSShiftV">; 422defm "" : LMULSchedWrites<"WriteVSShiftX">; 423defm "" : LMULSchedWrites<"WriteVSShiftI">; 424// 12.5. Vector Narrowing Fixed-Point Clip Instructions 425defm "" : LMULSchedWritesW<"WriteVNClipV">; 426defm "" : LMULSchedWritesW<"WriteVNClipX">; 427defm "" : LMULSchedWritesW<"WriteVNClipI">; 428 429// 13. Vector Floating-Point Instructions 430// 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions 431defm "" : LMULSEWSchedWritesF<"WriteVFALUV">; 432defm "" : LMULSEWSchedWritesF<"WriteVFALUF">; 433// 13.3. Vector Widening Floating-Point Add/Subtract Instructions 434defm "" : LMULSEWSchedWritesFW<"WriteVFWALUV">; 435defm "" : LMULSEWSchedWritesFW<"WriteVFWALUF">; 436// 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions 437defm "" : LMULSEWSchedWritesF<"WriteVFMulV">; 438defm "" : LMULSEWSchedWritesF<"WriteVFMulF">; 439defm "" : LMULSEWSchedWritesF<"WriteVFDivV">; 440defm "" : LMULSEWSchedWritesF<"WriteVFDivF">; 441// 13.5. Vector Widening Floating-Point Multiply 442defm "" : LMULSEWSchedWritesFW<"WriteVFWMulV">; 443defm "" : LMULSEWSchedWritesFW<"WriteVFWMulF">; 444// 13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions 445defm "" : LMULSEWSchedWritesF<"WriteVFMulAddV">; 446defm "" : LMULSEWSchedWritesF<"WriteVFMulAddF">; 447// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions 448defm "" : LMULSEWSchedWritesFW<"WriteVFWMulAddV">; 449defm "" : LMULSEWSchedWritesFW<"WriteVFWMulAddF">; 450// 13.8. Vector Floating-Point Square-Root Instruction 451defm "" : LMULSEWSchedWritesF<"WriteVFSqrtV">; 452// 13.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction 453// 13.10. Vector Floating-Point Reciprocal Estimate Instruction 454defm "" : LMULSEWSchedWritesF<"WriteVFRecpV">; 455// 13.11. Vector Floating-Point MIN/MAX Instructions 456defm "" : LMULSEWSchedWritesF<"WriteVFMinMaxV">; 457defm "" : LMULSEWSchedWritesF<"WriteVFMinMaxF">; 458// 13.12. Vector Floating-Point Sign-Injection Instructions 459defm "" : LMULSEWSchedWritesF<"WriteVFSgnjV">; 460defm "" : LMULSEWSchedWritesF<"WriteVFSgnjF">; 461// 13.13. Vector Floating-Point Compare Instructions 462defm "" : LMULSchedWrites<"WriteVFCmpV">; 463defm "" : LMULSchedWrites<"WriteVFCmpF">; 464// 13.14. Vector Floating-Point Classify Instruction 465defm "" : LMULSchedWrites<"WriteVFClassV">; 466// 13.15. Vector Floating-Point Merge Instruction 467defm "" : LMULSchedWrites<"WriteVFMergeV">; 468// 13.16. Vector Floating-Point Move Instruction 469defm "" : LMULSchedWrites<"WriteVFMovV">; 470// 13.17. Single-Width Floating-Point/Integer Type-Convert Instructions 471defm "" : LMULSEWSchedWritesF<"WriteVFCvtIToFV">; 472defm "" : LMULSchedWrites<"WriteVFCvtFToIV">; 473// 13.18. Widening Floating-Point/Integer Type-Convert Instructions 474defm "" : LMULSEWSchedWritesW<"WriteVFWCvtIToFV">; 475defm "" : LMULSchedWritesFW<"WriteVFWCvtFToIV">; 476defm "" : LMULSEWSchedWritesFW<"WriteVFWCvtFToFV">; 477// 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions 478defm "" : LMULSEWSchedWritesFW<"WriteVFNCvtIToFV">; 479defm "" : LMULSchedWritesW<"WriteVFNCvtFToIV">; 480defm "" : LMULSEWSchedWritesFW<"WriteVFNCvtFToFV">; 481 482// 14. Vector Reduction Operations 483// The latency of reduction is determined by the size of the read resource. 484// The LMUL range of read resource(VS2) for reduction operantion is between 485// MF8 and M8. Use the _From suffix to indicate the number of the 486// LMUL from VS2. 487// 14.1. Vector Single-Width Integer Reduction Instructions 488defm "" : LMULSEWSchedWrites<"WriteVIRedV_From">; 489defm "" : LMULSEWSchedWrites<"WriteVIRedMinMaxV_From">; 490// 14.2. Vector Widening Integer Reduction Instructions 491defm "" : LMULSEWSchedWritesWRed<"WriteVIWRedV_From">; 492// 14.3. Vector Single-Width Floating-Point Reduction Instructions 493defm "" : LMULSEWSchedWritesF<"WriteVFRedV_From">; 494defm "" : LMULSEWSchedWritesF<"WriteVFRedOV_From">; 495defm "" : LMULSEWSchedWritesF<"WriteVFRedMinMaxV_From">; 496// 14.4. Vector Widening Floating-Point Reduction Instructions 497defm "" : LMULSEWSchedWritesFWRed<"WriteVFWRedV_From">; 498defm "" : LMULSEWSchedWritesFWRed<"WriteVFWRedOV_From">; 499 500// 15. Vector Mask Instructions 501// 15.1. Vector Mask-Register Logical Instructions 502defm "" : LMULSchedWrites<"WriteVMALUV">; 503// 15.2. Vector Mask Population Count 504defm "" : LMULSchedWrites<"WriteVMPopV">; 505// 15.3. Vector Find-First-Set Mask Bit 506defm "" : LMULSchedWrites<"WriteVMFFSV">; 507// 15.4. Vector Set-Before-First Mask Bit 508// 15.5. Vector Set-Including-First Mask Bit 509// 15.6. Vector Set-only-First Mask Bit 510defm "" : LMULSchedWrites<"WriteVMSFSV">; 511// 15.8. Vector Iota Instruction 512defm "" : LMULSchedWrites<"WriteVIotaV">; 513// 15.9. Vector Element Index Instruction 514defm "" : LMULSchedWrites<"WriteVIdxV">; 515 516// 16. Vector Permutation Instructions 517// 16.1. Integer Scalar Move Instructions 518def WriteVMovSX : SchedWrite; 519def WriteVMovXS : SchedWrite; 520// 16.2. Floating-Point Scalar Move Instructions 521def WriteVMovSF : SchedWrite; 522def WriteVMovFS : SchedWrite; 523// 16.3. Vector Slide Instructions 524defm "" : LMULSchedWrites<"WriteVSlideUpX">; 525defm "" : LMULSchedWrites<"WriteVSlideDownX">; 526defm "" : LMULSchedWrites<"WriteVSlideI">; 527defm "" : LMULSchedWrites<"WriteVISlide1X">; 528defm "" : LMULSchedWrites<"WriteVFSlide1F">; 529// 16.4. Vector Register Gather Instructions 530defm "" : LMULSEWSchedWrites<"WriteVRGatherVV">; 531defm "" : LMULSEWSchedWrites<"WriteVRGatherEI16VV">; 532defm "" : LMULSchedWrites<"WriteVRGatherVX">; 533defm "" : LMULSchedWrites<"WriteVRGatherVI">; 534// 16.5. Vector Compress Instruction 535defm "" : LMULSEWSchedWrites<"WriteVCompressV">; 536// 16.6. Whole Vector Register Move 537// These are already LMUL aware 538def WriteVMov1V : SchedWrite; 539def WriteVMov2V : SchedWrite; 540def WriteVMov4V : SchedWrite; 541def WriteVMov8V : SchedWrite; 542 543//===----------------------------------------------------------------------===// 544/// Define scheduler resources associated with use operands. 545 546// 6. Configuration-Setting Instructions 547def ReadVSETVLI : SchedRead; 548def ReadVSETVL : SchedRead; 549 550// 7. Vector Loads and Stores 551def ReadVLDX : SchedRead; 552def ReadVSTX : SchedRead; 553// 7.4. Vector Unit-Stride Instructions 554defm "" : LMULSchedReads<"ReadVSTEV">; 555// 7.4.1. Vector Unit-Strided Mask 556defm "" : LMULSchedReads<"ReadVSTM">; 557// 7.5. Vector Strided Instructions 558def ReadVLDSX : SchedRead; 559def ReadVSTSX : SchedRead; 560defm "" : LMULSchedReads<"ReadVSTS8V">; 561defm "" : LMULSchedReads<"ReadVSTS16V">; 562defm "" : LMULSchedReads<"ReadVSTS32V">; 563defm "" : LMULSchedReads<"ReadVSTS64V">; 564// 7.6. Vector Indexed Instructions 565defm "" : LMULSchedReads<"ReadVLDUXV">; 566defm "" : LMULSchedReads<"ReadVLDOXV">; 567defm "" : LMULSchedReads<"ReadVSTUX8">; 568defm "" : LMULSchedReads<"ReadVSTUX16">; 569defm "" : LMULSchedReads<"ReadVSTUX32">; 570defm "" : LMULSchedReads<"ReadVSTUX64">; 571defm "" : LMULSchedReads<"ReadVSTUXV">; 572defm "" : LMULSchedReads<"ReadVSTUX8V">; 573defm "" : LMULSchedReads<"ReadVSTUX16V">; 574defm "" : LMULSchedReads<"ReadVSTUX32V">; 575defm "" : LMULSchedReads<"ReadVSTUX64V">; 576defm "" : LMULSchedReads<"ReadVSTOX8">; 577defm "" : LMULSchedReads<"ReadVSTOX16">; 578defm "" : LMULSchedReads<"ReadVSTOX32">; 579defm "" : LMULSchedReads<"ReadVSTOX64">; 580defm "" : LMULSchedReads<"ReadVSTOXV">; 581defm "" : LMULSchedReads<"ReadVSTOX8V">; 582defm "" : LMULSchedReads<"ReadVSTOX16V">; 583defm "" : LMULSchedReads<"ReadVSTOX32V">; 584defm "" : LMULSchedReads<"ReadVSTOX64V">; 585// 7.9. Vector Whole Register Instructions 586// These are already LMUL aware 587def ReadVST1R : SchedRead; 588def ReadVST2R : SchedRead; 589def ReadVST4R : SchedRead; 590def ReadVST8R : SchedRead; 591 592// 11. Vector Integer Arithmetic Instructions 593// 11.1. Vector Single-Width Integer Add and Subtract 594// 11.5. Vector Bitwise Logical Instructions 595defm "" : LMULSchedReads<"ReadVIALUV">; 596defm "" : LMULSchedReads<"ReadVIALUX">; 597// 11.2. Vector Widening Integer Add/Subtract 598defm "" : LMULSchedReadsW<"ReadVIWALUV">; 599defm "" : LMULSchedReadsW<"ReadVIWALUX">; 600// 11.3. Vector Integer Extension 601defm "" : LMULSchedReads<"ReadVExtV">; 602// 11.4. Vector Integer Arithmetic with Carry or Borrow Instructions 603defm "" : LMULSchedReads<"ReadVICALUV">; 604defm "" : LMULSchedReads<"ReadVICALUX">; 605// 11.6. Vector Single-Width Bit Shift Instructions 606defm "" : LMULSchedReads<"ReadVShiftV">; 607defm "" : LMULSchedReads<"ReadVShiftX">; 608// 11.7. Vector Narrowing Integer Right Shift Instructions 609defm "" : LMULSchedReadsW<"ReadVNShiftV">; 610defm "" : LMULSchedReadsW<"ReadVNShiftX">; 611// 11.8. Vector Integer Comparison Instructions 612defm "" : LMULSchedReads<"ReadVICmpV">; 613defm "" : LMULSchedReads<"ReadVICmpX">; 614// 11.9. Vector Integer Min/Max Instructions 615defm "" : LMULSchedReads<"ReadVIMinMaxV">; 616defm "" : LMULSchedReads<"ReadVIMinMaxX">; 617// 11.10. Vector Single-Width Integer Multiply Instructions 618defm "" : LMULSchedReads<"ReadVIMulV">; 619defm "" : LMULSchedReads<"ReadVIMulX">; 620// 11.11. Vector Integer Divide Instructions 621defm "" : LMULSEWSchedReads<"ReadVIDivV">; 622defm "" : LMULSEWSchedReads<"ReadVIDivX">; 623// 11.12. Vector Widening Integer Multiply Instructions 624defm "" : LMULSchedReadsW<"ReadVIWMulV">; 625defm "" : LMULSchedReadsW<"ReadVIWMulX">; 626// 11.13. Vector Single-Width Integer Multiply-Add Instructions 627defm "" : LMULSchedReads<"ReadVIMulAddV">; 628defm "" : LMULSchedReads<"ReadVIMulAddX">; 629// 11.14. Vector Widening Integer Multiply-Add Instructions 630defm "" : LMULSchedReadsW<"ReadVIWMulAddV">; 631defm "" : LMULSchedReadsW<"ReadVIWMulAddX">; 632// 11.15. Vector Integer Merge Instructions 633defm "" : LMULSchedReads<"ReadVIMergeV">; 634defm "" : LMULSchedReads<"ReadVIMergeX">; 635// 11.16. Vector Integer Move Instructions 636defm "" : LMULSchedReads<"ReadVIMovV">; 637defm "" : LMULSchedReads<"ReadVIMovX">; 638 639// 12. Vector Fixed-Point Arithmetic Instructions 640// 12.1. Vector Single-Width Saturating Add and Subtract 641defm "" : LMULSchedReads<"ReadVSALUV">; 642defm "" : LMULSchedReads<"ReadVSALUX">; 643// 12.2. Vector Single-Width Averaging Add and Subtract 644defm "" : LMULSchedReads<"ReadVAALUV">; 645defm "" : LMULSchedReads<"ReadVAALUX">; 646// 12.3. Vector Single-Width Fractional Multiply with Rounding and Saturation 647defm "" : LMULSchedReads<"ReadVSMulV">; 648defm "" : LMULSchedReads<"ReadVSMulX">; 649// 12.4. Vector Single-Width Scaling Shift Instructions 650defm "" : LMULSchedReads<"ReadVSShiftV">; 651defm "" : LMULSchedReads<"ReadVSShiftX">; 652// 12.5. Vector Narrowing Fixed-Point Clip Instructions 653defm "" : LMULSchedReadsW<"ReadVNClipV">; 654defm "" : LMULSchedReadsW<"ReadVNClipX">; 655 656// 13. Vector Floating-Point Instructions 657// 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions 658defm "" : LMULSEWSchedReadsF<"ReadVFALUV">; 659defm "" : LMULSEWSchedReadsF<"ReadVFALUF">; 660// 13.3. Vector Widening Floating-Point Add/Subtract Instructions 661defm "" : LMULSEWSchedReadsFW<"ReadVFWALUV">; 662defm "" : LMULSEWSchedReadsFW<"ReadVFWALUF">; 663// 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions 664defm "" : LMULSEWSchedReadsF<"ReadVFMulV">; 665defm "" : LMULSEWSchedReadsF<"ReadVFMulF">; 666defm "" : LMULSEWSchedReadsF<"ReadVFDivV">; 667defm "" : LMULSEWSchedReadsF<"ReadVFDivF">; 668// 13.5. Vector Widening Floating-Point Multiply 669defm "" : LMULSEWSchedReadsFW<"ReadVFWMulV">; 670defm "" : LMULSEWSchedReadsFW<"ReadVFWMulF">; 671// 13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions 672defm "" : LMULSEWSchedReadsF<"ReadVFMulAddV">; 673defm "" : LMULSEWSchedReadsF<"ReadVFMulAddF">; 674// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions 675defm "" : LMULSEWSchedReadsFW<"ReadVFWMulAddV">; 676defm "" : LMULSEWSchedReadsFW<"ReadVFWMulAddF">; 677// 13.8. Vector Floating-Point Square-Root Instruction 678defm "" : LMULSEWSchedReadsF<"ReadVFSqrtV">; 679// 13.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction 680// 13.10. Vector Floating-Point Reciprocal Estimate Instruction 681defm "" : LMULSEWSchedReadsF<"ReadVFRecpV">; 682// 13.11. Vector Floating-Point MIN/MAX Instructions 683defm "" : LMULSEWSchedReadsF<"ReadVFMinMaxV">; 684defm "" : LMULSEWSchedReadsF<"ReadVFMinMaxF">; 685// 13.12. Vector Floating-Point Sign-Injection Instructions 686defm "" : LMULSEWSchedReadsF<"ReadVFSgnjV">; 687defm "" : LMULSEWSchedReadsF<"ReadVFSgnjF">; 688// 13.13. Vector Floating-Point Compare Instructions 689defm "" : LMULSchedReads<"ReadVFCmpV">; 690defm "" : LMULSchedReads<"ReadVFCmpF">; 691// 13.14. Vector Floating-Point Classify Instruction 692defm "" : LMULSchedReads<"ReadVFClassV">; 693// 13.15. Vector Floating-Point Merge Instruction 694defm "" : LMULSchedReads<"ReadVFMergeV">; 695defm "" : LMULSchedReads<"ReadVFMergeF">; 696// 13.16. Vector Floating-Point Move Instruction 697defm "" : LMULSchedReads<"ReadVFMovF">; 698// 13.17. Single-Width Floating-Point/Integer Type-Convert Instructions 699defm "" : LMULSEWSchedReadsF<"ReadVFCvtIToFV">; 700defm "" : LMULSchedReads<"ReadVFCvtFToIV">; 701// 13.18. Widening Floating-Point/Integer Type-Convert Instructions 702defm "" : LMULSEWSchedReadsW<"ReadVFWCvtIToFV">; 703defm "" : LMULSchedReadsFW<"ReadVFWCvtFToIV">; 704defm "" : LMULSEWSchedReadsFW<"ReadVFWCvtFToFV">; 705// 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions 706defm "" : LMULSEWSchedReadsFW<"ReadVFNCvtIToFV">; 707defm "" : LMULSchedReadsW<"ReadVFNCvtFToIV">; 708defm "" : LMULSEWSchedReadsFW<"ReadVFNCvtFToFV">; 709 710// 14. Vector Reduction Operations 711// 14.1. Vector Single-Width Integer Reduction Instructions 712def ReadVIRedV : SchedRead; 713def ReadVIRedV0 : SchedRead; 714// 14.2. Vector Widening Integer Reduction Instructions 715def ReadVIWRedV : SchedRead; 716def ReadVIWRedV0 : SchedRead; 717// 14.3. Vector Single-Width Floating-Point Reduction Instructions 718def ReadVFRedV : SchedRead; 719def ReadVFRedV0 : SchedRead; 720def ReadVFRedOV : SchedRead; 721def ReadVFRedOV0 : SchedRead; 722def ReadVFRedMinMaxV : SchedRead; 723// 14.4. Vector Widening Floating-Point Reduction Instructions 724def ReadVFWRedV : SchedRead; 725def ReadVFWRedV0 : SchedRead; 726def ReadVFWRedOV : SchedRead; 727def ReadVFWRedOV0 : SchedRead; 728 729// 15. Vector Mask Instructions 730// 15.1. Vector Mask-Register Logical Instructions 731defm "" : LMULSchedReads<"ReadVMALUV">; 732// 15.2. Vector Mask Population Count 733defm "" : LMULSchedReads<"ReadVMPopV">; 734// 15.3. Vector Find-First-Set Mask Bit 735defm "" : LMULSchedReads<"ReadVMFFSV">; 736// 15.4. Vector Set-Before-First Mask Bit 737// 15.5. Vector Set-Including-First Mask Bit 738// 15.6. Vector Set-only-First Mask Bit 739defm "" : LMULSchedReads<"ReadVMSFSV">; 740// 15.8. Vector Iota Instruction 741defm "" : LMULSchedReads<"ReadVIotaV">; 742 743// 16. Vector Permutation Instructions 744// 16.1. Integer Scalar Move Instructions 745def ReadVMovXS : SchedRead; 746def ReadVMovSX_V : SchedRead; 747def ReadVMovSX_X : SchedRead; 748// 16.2. Floating-Point Scalar Move Instructions 749def ReadVMovFS : SchedRead; 750def ReadVMovSF_V : SchedRead; 751def ReadVMovSF_F : SchedRead; 752// 16.3. Vector Slide Instructions 753defm "" : LMULSchedReads<"ReadVISlideV">; 754defm "" : LMULSchedReads<"ReadVISlideX">; 755defm "" : LMULSchedReads<"ReadVFSlideV">; 756defm "" : LMULSchedReads<"ReadVFSlideF">; 757// 16.4. Vector Register Gather Instructions 758defm "" : LMULSEWSchedReads<"ReadVRGatherVV_data">; 759defm "" : LMULSEWSchedReads<"ReadVRGatherVV_index">; 760defm "" : LMULSEWSchedReads<"ReadVRGatherEI16VV_data">; 761defm "" : LMULSEWSchedReads<"ReadVRGatherEI16VV_index">; 762defm "" : LMULSchedReads<"ReadVRGatherVX_data">; 763defm "" : LMULSchedReads<"ReadVRGatherVX_index">; 764defm "" : LMULSchedReads<"ReadVRGatherVI_data">; 765// 16.5. Vector Compress Instruction 766defm "" : LMULSEWSchedReads<"ReadVCompressV">; 767// 16.6. Whole Vector Register Move 768// These are already LMUL aware 769def ReadVMov1V : SchedRead; 770def ReadVMov2V : SchedRead; 771def ReadVMov4V : SchedRead; 772def ReadVMov8V : SchedRead; 773 774// Others 775def ReadVMask : SchedRead; 776def ReadVPassthru_WorstCase : SchedRead; 777foreach mx = SchedMxList in { 778 def ReadVPassthru_ # mx : SchedRead; 779 foreach sew = SchedSEWSet<mx>.val in 780 def ReadVPassthru_ # mx # "_E" # sew : SchedRead; 781} 782 783//===----------------------------------------------------------------------===// 784/// Define default scheduler resources for V. 785 786multiclass UnsupportedSchedV { 787let Unsupported = true in { 788 789// 3.6 Vector Byte Length vlenb 790def : WriteRes<WriteRdVLENB, []>; 791 792// 6. Configuration-Setting Instructions 793def : WriteRes<WriteVSETVLI, []>; 794def : WriteRes<WriteVSETIVLI, []>; 795def : WriteRes<WriteVSETVL, []>; 796 797// 7. Vector Loads and Stores 798defm "" : LMULWriteRes<"WriteVLDE", []>; 799defm "" : LMULWriteRes<"WriteVSTE", []>; 800defm "" : LMULWriteRes<"WriteVLDM", []>; 801defm "" : LMULWriteRes<"WriteVSTM", []>; 802defm "" : LMULWriteRes<"WriteVLDS8", []>; 803defm "" : LMULWriteRes<"WriteVLDS16", []>; 804defm "" : LMULWriteRes<"WriteVLDS32", []>; 805defm "" : LMULWriteRes<"WriteVLDS64", []>; 806defm "" : LMULWriteRes<"WriteVSTS8", []>; 807defm "" : LMULWriteRes<"WriteVSTS16", []>; 808defm "" : LMULWriteRes<"WriteVSTS32", []>; 809defm "" : LMULWriteRes<"WriteVSTS64", []>; 810defm "" : LMULWriteRes<"WriteVLDUX8", []>; 811defm "" : LMULWriteRes<"WriteVLDUX16", []>; 812defm "" : LMULWriteRes<"WriteVLDUX32", []>; 813defm "" : LMULWriteRes<"WriteVLDUX64", []>; 814defm "" : LMULWriteRes<"WriteVLDOX8", []>; 815defm "" : LMULWriteRes<"WriteVLDOX16", []>; 816defm "" : LMULWriteRes<"WriteVLDOX32", []>; 817defm "" : LMULWriteRes<"WriteVLDOX64", []>; 818defm "" : LMULWriteRes<"WriteVSTUX8", []>; 819defm "" : LMULWriteRes<"WriteVSTUX16", []>; 820defm "" : LMULWriteRes<"WriteVSTUX32", []>; 821defm "" : LMULWriteRes<"WriteVSTUX64", []>; 822defm "" : LMULWriteRes<"WriteVSTOX8", []>; 823defm "" : LMULWriteRes<"WriteVSTOX16", []>; 824defm "" : LMULWriteRes<"WriteVSTOX32", []>; 825defm "" : LMULWriteRes<"WriteVSTOX64", []>; 826defm "" : LMULWriteRes<"WriteVLDFF", []>; 827// These are already LMUL aware 828def : WriteRes<WriteVLD1R, []>; 829def : WriteRes<WriteVLD2R, []>; 830def : WriteRes<WriteVLD4R, []>; 831def : WriteRes<WriteVLD8R, []>; 832def : WriteRes<WriteVST1R, []>; 833def : WriteRes<WriteVST2R, []>; 834def : WriteRes<WriteVST4R, []>; 835def : WriteRes<WriteVST8R, []>; 836// Vector Segment Loads and Stores 837foreach nf=2-8 in { 838 foreach eew = [8, 16, 32, 64] in { 839 defm "" : LMULWriteRes <"WriteVLSEG" # nf # "e" # eew, []>; 840 defm "" : LMULWriteRes <"WriteVLSEGFF" # nf # "e" # eew, []>; 841 defm "" : LMULWriteRes <"WriteVSSEG" # nf # "e" # eew, []>; 842 defm "" : LMULWriteRes <"WriteVLSSEG" # nf # "e" # eew, []>; 843 defm "" : LMULWriteRes <"WriteVSSSEG" # nf # "e" # eew, []>; 844 defm "" : LMULWriteRes <"WriteVLUXSEG" # nf # "e" # eew, []>; 845 defm "" : LMULWriteRes <"WriteVLOXSEG" # nf # "e" # eew, []>; 846 defm "" : LMULWriteRes <"WriteVSUXSEG" # nf # "e" # eew, []>; 847 defm "" : LMULWriteRes <"WriteVSOXSEG" # nf # "e" # eew, []>; 848 } 849} 850 851// 11. Vector Integer Arithmetic Instructions 852defm "" : LMULWriteRes<"WriteVIALUV", []>; 853defm "" : LMULWriteRes<"WriteVIALUX", []>; 854defm "" : LMULWriteRes<"WriteVIALUI", []>; 855defm "" : LMULWriteResW<"WriteVIWALUV", []>; 856defm "" : LMULWriteResW<"WriteVIWALUX", []>; 857defm "" : LMULWriteResW<"WriteVIWALUI", []>; 858defm "" : LMULWriteRes<"WriteVExtV", []>; 859defm "" : LMULWriteRes<"WriteVICALUV", []>; 860defm "" : LMULWriteRes<"WriteVICALUX", []>; 861defm "" : LMULWriteRes<"WriteVICALUI", []>; 862defm "" : LMULWriteRes<"WriteVICALUMV", []>; 863defm "" : LMULWriteRes<"WriteVICALUMX", []>; 864defm "" : LMULWriteRes<"WriteVICALUMI", []>; 865defm "" : LMULWriteRes<"WriteVShiftV", []>; 866defm "" : LMULWriteRes<"WriteVShiftX", []>; 867defm "" : LMULWriteRes<"WriteVShiftI", []>; 868defm "" : LMULWriteResW<"WriteVNShiftV", []>; 869defm "" : LMULWriteResW<"WriteVNShiftX", []>; 870defm "" : LMULWriteResW<"WriteVNShiftI", []>; 871defm "" : LMULWriteRes<"WriteVICmpV", []>; 872defm "" : LMULWriteRes<"WriteVICmpX", []>; 873defm "" : LMULWriteRes<"WriteVICmpI", []>; 874defm "" : LMULWriteRes<"WriteVIMinMaxV", []>; 875defm "" : LMULWriteRes<"WriteVIMinMaxX", []>; 876defm "" : LMULWriteRes<"WriteVIMulV", []>; 877defm "" : LMULWriteRes<"WriteVIMulX", []>; 878defm "" : LMULSEWWriteRes<"WriteVIDivV", []>; 879defm "" : LMULSEWWriteRes<"WriteVIDivX", []>; 880defm "" : LMULWriteResW<"WriteVIWMulV", []>; 881defm "" : LMULWriteResW<"WriteVIWMulX", []>; 882defm "" : LMULWriteRes<"WriteVIMulAddV", []>; 883defm "" : LMULWriteRes<"WriteVIMulAddX", []>; 884defm "" : LMULWriteResW<"WriteVIWMulAddV", []>; 885defm "" : LMULWriteResW<"WriteVIWMulAddX", []>; 886defm "" : LMULWriteRes<"WriteVIMergeV", []>; 887defm "" : LMULWriteRes<"WriteVIMergeX", []>; 888defm "" : LMULWriteRes<"WriteVIMergeI", []>; 889defm "" : LMULWriteRes<"WriteVIMovV", []>; 890defm "" : LMULWriteRes<"WriteVIMovX", []>; 891defm "" : LMULWriteRes<"WriteVIMovI", []>; 892 893// 12. Vector Fixed-Point Arithmetic Instructions 894defm "" : LMULWriteRes<"WriteVSALUV", []>; 895defm "" : LMULWriteRes<"WriteVSALUX", []>; 896defm "" : LMULWriteRes<"WriteVSALUI", []>; 897defm "" : LMULWriteRes<"WriteVAALUV", []>; 898defm "" : LMULWriteRes<"WriteVAALUX", []>; 899defm "" : LMULWriteRes<"WriteVSMulV", []>; 900defm "" : LMULWriteRes<"WriteVSMulX", []>; 901defm "" : LMULWriteRes<"WriteVSShiftV", []>; 902defm "" : LMULWriteRes<"WriteVSShiftX", []>; 903defm "" : LMULWriteRes<"WriteVSShiftI", []>; 904defm "" : LMULWriteResW<"WriteVNClipV", []>; 905defm "" : LMULWriteResW<"WriteVNClipX", []>; 906defm "" : LMULWriteResW<"WriteVNClipI", []>; 907 908// 13. Vector Floating-Point Instructions 909defm "" : LMULSEWWriteResF<"WriteVFALUV", []>; 910defm "" : LMULSEWWriteResF<"WriteVFALUF", []>; 911defm "" : LMULSEWWriteResFW<"WriteVFWALUV", []>; 912defm "" : LMULSEWWriteResFW<"WriteVFWALUF", []>; 913defm "" : LMULSEWWriteResF<"WriteVFMulV", []>; 914defm "" : LMULSEWWriteResF<"WriteVFMulF", []>; 915defm "" : LMULSEWWriteResF<"WriteVFDivV", []>; 916defm "" : LMULSEWWriteResF<"WriteVFDivF", []>; 917defm "" : LMULSEWWriteResFW<"WriteVFWMulV", []>; 918defm "" : LMULSEWWriteResFW<"WriteVFWMulF", []>; 919defm "" : LMULSEWWriteResF<"WriteVFMulAddV", []>; 920defm "" : LMULSEWWriteResF<"WriteVFMulAddF", []>; 921defm "" : LMULSEWWriteResFW<"WriteVFWMulAddV", []>; 922defm "" : LMULSEWWriteResFW<"WriteVFWMulAddF", []>; 923defm "" : LMULSEWWriteResF<"WriteVFSqrtV", []>; 924defm "" : LMULSEWWriteResF<"WriteVFRecpV", []>; 925defm "" : LMULSEWWriteResF<"WriteVFMinMaxV", []>; 926defm "" : LMULSEWWriteResF<"WriteVFMinMaxF", []>; 927defm "" : LMULSEWWriteResF<"WriteVFSgnjV", []>; 928defm "" : LMULSEWWriteResF<"WriteVFSgnjF", []>; 929defm "" : LMULWriteRes<"WriteVFCmpV", []>; 930defm "" : LMULWriteRes<"WriteVFCmpF", []>; 931defm "" : LMULWriteRes<"WriteVFClassV", []>; 932defm "" : LMULWriteRes<"WriteVFMergeV", []>; 933defm "" : LMULWriteRes<"WriteVFMovV", []>; 934defm "" : LMULSEWWriteResF<"WriteVFCvtIToFV", []>; 935defm "" : LMULWriteRes<"WriteVFCvtFToIV", []>; 936defm "" : LMULSEWWriteResW<"WriteVFWCvtIToFV", []>; 937defm "" : LMULWriteResFW<"WriteVFWCvtFToIV", []>; 938defm "" : LMULSEWWriteResFW<"WriteVFWCvtFToFV", []>; 939defm "" : LMULSEWWriteResFW<"WriteVFNCvtIToFV", []>; 940defm "" : LMULWriteResW<"WriteVFNCvtFToIV", []>; 941defm "" : LMULSEWWriteResFW<"WriteVFNCvtFToFV", []>; 942 943// 14. Vector Reduction Operations 944defm "" : LMULSEWWriteRes<"WriteVIRedV_From", []>; 945defm "" : LMULSEWWriteRes<"WriteVIRedMinMaxV_From", []>; 946defm "" : LMULSEWWriteResWRed<"WriteVIWRedV_From", []>; 947defm "" : LMULSEWWriteResF<"WriteVFRedV_From", []>; 948defm "" : LMULSEWWriteResF<"WriteVFRedOV_From", []>; 949defm "" : LMULSEWWriteResF<"WriteVFRedMinMaxV_From", []>; 950defm "" : LMULSEWWriteResFWRed<"WriteVFWRedV_From", []>; 951defm "" : LMULSEWWriteResFWRed<"WriteVFWRedOV_From", []>; 952 953// 15. Vector Mask Instructions 954defm "" : LMULWriteRes<"WriteVMALUV", []>; 955defm "" : LMULWriteRes<"WriteVMPopV", []>; 956defm "" : LMULWriteRes<"WriteVMFFSV", []>; 957defm "" : LMULWriteRes<"WriteVMSFSV", []>; 958defm "" : LMULWriteRes<"WriteVIotaV", []>; 959defm "" : LMULWriteRes<"WriteVIdxV", []>; 960 961// 16. Vector Permutation Instructions 962def : WriteRes<WriteVMovSX, []>; 963def : WriteRes<WriteVMovXS, []>; 964def : WriteRes<WriteVMovSF, []>; 965def : WriteRes<WriteVMovFS, []>; 966defm "" : LMULWriteRes<"WriteVSlideUpX", []>; 967defm "" : LMULWriteRes<"WriteVSlideDownX", []>; 968defm "" : LMULWriteRes<"WriteVSlideI", []>; 969defm "" : LMULWriteRes<"WriteVISlide1X", []>; 970defm "" : LMULWriteRes<"WriteVFSlide1F", []>; 971defm "" : LMULSEWWriteRes<"WriteVRGatherVV", []>; 972defm "" : LMULSEWWriteRes<"WriteVRGatherEI16VV", []>; 973defm "" : LMULWriteRes<"WriteVRGatherVX", []>; 974defm "" : LMULWriteRes<"WriteVRGatherVI", []>; 975defm "" : LMULSEWWriteRes<"WriteVCompressV", []>; 976// These are already LMUL aware 977def : WriteRes<WriteVMov1V, []>; 978def : WriteRes<WriteVMov2V, []>; 979def : WriteRes<WriteVMov4V, []>; 980def : WriteRes<WriteVMov8V, []>; 981 982// 6. Configuration-Setting Instructions 983def : ReadAdvance<ReadVSETVLI, 0>; 984def : ReadAdvance<ReadVSETVL, 0>; 985 986// 7. Vector Loads and Stores 987def : ReadAdvance<ReadVLDX, 0>; 988def : ReadAdvance<ReadVSTX, 0>; 989defm "" : LMULReadAdvance<"ReadVSTEV", 0>; 990defm "" : LMULReadAdvance<"ReadVSTM", 0>; 991def : ReadAdvance<ReadVLDSX, 0>; 992def : ReadAdvance<ReadVSTSX, 0>; 993defm "" : LMULReadAdvance<"ReadVSTS8V", 0>; 994defm "" : LMULReadAdvance<"ReadVSTS16V", 0>; 995defm "" : LMULReadAdvance<"ReadVSTS32V", 0>; 996defm "" : LMULReadAdvance<"ReadVSTS64V", 0>; 997defm "" : LMULReadAdvance<"ReadVLDUXV", 0>; 998defm "" : LMULReadAdvance<"ReadVLDOXV", 0>; 999defm "" : LMULReadAdvance<"ReadVSTUXV", 0>; 1000defm "" : LMULReadAdvance<"ReadVSTUX8", 0>; 1001defm "" : LMULReadAdvance<"ReadVSTUX16", 0>; 1002defm "" : LMULReadAdvance<"ReadVSTUX32", 0>; 1003defm "" : LMULReadAdvance<"ReadVSTUX64", 0>; 1004defm "" : LMULReadAdvance<"ReadVSTUX8V", 0>; 1005defm "" : LMULReadAdvance<"ReadVSTUX16V", 0>; 1006defm "" : LMULReadAdvance<"ReadVSTUX32V", 0>; 1007defm "" : LMULReadAdvance<"ReadVSTUX64V", 0>; 1008defm "" : LMULReadAdvance<"ReadVSTOX8", 0>; 1009defm "" : LMULReadAdvance<"ReadVSTOX16", 0>; 1010defm "" : LMULReadAdvance<"ReadVSTOX32", 0>; 1011defm "" : LMULReadAdvance<"ReadVSTOX64", 0>; 1012defm "" : LMULReadAdvance<"ReadVSTOXV", 0>; 1013defm "" : LMULReadAdvance<"ReadVSTOX8V", 0>; 1014defm "" : LMULReadAdvance<"ReadVSTOX16V", 0>; 1015defm "" : LMULReadAdvance<"ReadVSTOX32V", 0>; 1016defm "" : LMULReadAdvance<"ReadVSTOX64V", 0>; 1017// These are already LMUL aware 1018def : ReadAdvance<ReadVST1R, 0>; 1019def : ReadAdvance<ReadVST2R, 0>; 1020def : ReadAdvance<ReadVST4R, 0>; 1021def : ReadAdvance<ReadVST8R, 0>; 1022 1023// 11. Vector Integer Arithmetic Instructions 1024defm "" : LMULReadAdvance<"ReadVIALUV", 0>; 1025defm "" : LMULReadAdvance<"ReadVIALUX", 0>; 1026defm "" : LMULReadAdvanceW<"ReadVIWALUV", 0>; 1027defm "" : LMULReadAdvanceW<"ReadVIWALUX", 0>; 1028defm "" : LMULReadAdvance<"ReadVExtV", 0>; 1029defm "" : LMULReadAdvance<"ReadVICALUV", 0>; 1030defm "" : LMULReadAdvance<"ReadVICALUX", 0>; 1031defm "" : LMULReadAdvance<"ReadVShiftV", 0>; 1032defm "" : LMULReadAdvance<"ReadVShiftX", 0>; 1033defm "" : LMULReadAdvanceW<"ReadVNShiftV", 0>; 1034defm "" : LMULReadAdvanceW<"ReadVNShiftX", 0>; 1035defm "" : LMULReadAdvance<"ReadVICmpV", 0>; 1036defm "" : LMULReadAdvance<"ReadVICmpX", 0>; 1037defm "" : LMULReadAdvance<"ReadVIMinMaxV", 0>; 1038defm "" : LMULReadAdvance<"ReadVIMinMaxX", 0>; 1039defm "" : LMULReadAdvance<"ReadVIMulV", 0>; 1040defm "" : LMULReadAdvance<"ReadVIMulX", 0>; 1041defm "" : LMULSEWReadAdvance<"ReadVIDivV", 0>; 1042defm "" : LMULSEWReadAdvance<"ReadVIDivX", 0>; 1043defm "" : LMULReadAdvanceW<"ReadVIWMulV", 0>; 1044defm "" : LMULReadAdvanceW<"ReadVIWMulX", 0>; 1045defm "" : LMULReadAdvance<"ReadVIMulAddV", 0>; 1046defm "" : LMULReadAdvance<"ReadVIMulAddX", 0>; 1047defm "" : LMULReadAdvanceW<"ReadVIWMulAddV", 0>; 1048defm "" : LMULReadAdvanceW<"ReadVIWMulAddX", 0>; 1049defm "" : LMULReadAdvance<"ReadVIMergeV", 0>; 1050defm "" : LMULReadAdvance<"ReadVIMergeX", 0>; 1051defm "" : LMULReadAdvance<"ReadVIMovV", 0>; 1052defm "" : LMULReadAdvance<"ReadVIMovX", 0>; 1053 1054// 12. Vector Fixed-Point Arithmetic Instructions 1055defm "" : LMULReadAdvance<"ReadVSALUV", 0>; 1056defm "" : LMULReadAdvance<"ReadVSALUX", 0>; 1057defm "" : LMULReadAdvance<"ReadVAALUV", 0>; 1058defm "" : LMULReadAdvance<"ReadVAALUX", 0>; 1059defm "" : LMULReadAdvance<"ReadVSMulV", 0>; 1060defm "" : LMULReadAdvance<"ReadVSMulX", 0>; 1061defm "" : LMULReadAdvance<"ReadVSShiftV", 0>; 1062defm "" : LMULReadAdvance<"ReadVSShiftX", 0>; 1063defm "" : LMULReadAdvanceW<"ReadVNClipV", 0>; 1064defm "" : LMULReadAdvanceW<"ReadVNClipX", 0>; 1065 1066// 13. Vector Floating-Point Instructions 1067defm "" : LMULSEWReadAdvanceF<"ReadVFALUV", 0>; 1068defm "" : LMULSEWReadAdvanceF<"ReadVFALUF", 0>; 1069defm "" : LMULSEWReadAdvanceFW<"ReadVFWALUV", 0>; 1070defm "" : LMULSEWReadAdvanceFW<"ReadVFWALUF", 0>; 1071defm "" : LMULSEWReadAdvanceF<"ReadVFMulV", 0>; 1072defm "" : LMULSEWReadAdvanceF<"ReadVFMulF", 0>; 1073defm "" : LMULSEWReadAdvanceF<"ReadVFDivV", 0>; 1074defm "" : LMULSEWReadAdvanceF<"ReadVFDivF", 0>; 1075defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulV", 0>; 1076defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulF", 0>; 1077defm "" : LMULSEWReadAdvanceF<"ReadVFMulAddV", 0>; 1078defm "" : LMULSEWReadAdvanceF<"ReadVFMulAddF", 0>; 1079defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulAddV", 0>; 1080defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulAddF", 0>; 1081defm "" : LMULSEWReadAdvanceF<"ReadVFSqrtV", 0>; 1082defm "" : LMULSEWReadAdvanceF<"ReadVFRecpV", 0>; 1083defm "" : LMULSEWReadAdvanceF<"ReadVFMinMaxV", 0>; 1084defm "" : LMULSEWReadAdvanceF<"ReadVFMinMaxF", 0>; 1085defm "" : LMULSEWReadAdvanceF<"ReadVFSgnjV", 0>; 1086defm "" : LMULSEWReadAdvanceF<"ReadVFSgnjF", 0>; 1087defm "" : LMULReadAdvance<"ReadVFCmpV", 0>; 1088defm "" : LMULReadAdvance<"ReadVFCmpF", 0>; 1089defm "" : LMULReadAdvance<"ReadVFClassV", 0>; 1090defm "" : LMULReadAdvance<"ReadVFMergeV", 0>; 1091defm "" : LMULReadAdvance<"ReadVFMergeF", 0>; 1092defm "" : LMULReadAdvance<"ReadVFMovF", 0>; 1093defm "" : LMULSEWReadAdvanceF<"ReadVFCvtIToFV", 0>; 1094defm "" : LMULReadAdvance<"ReadVFCvtFToIV", 0>; 1095defm "" : LMULSEWReadAdvanceW<"ReadVFWCvtIToFV", 0>; 1096defm "" : LMULReadAdvanceFW<"ReadVFWCvtFToIV", 0>; 1097defm "" : LMULSEWReadAdvanceFW<"ReadVFWCvtFToFV", 0>; 1098defm "" : LMULSEWReadAdvanceFW<"ReadVFNCvtIToFV", 0>; 1099defm "" : LMULReadAdvanceW<"ReadVFNCvtFToIV", 0>; 1100defm "" : LMULSEWReadAdvanceFW<"ReadVFNCvtFToFV", 0>; 1101 1102// 14. Vector Reduction Operations 1103def : ReadAdvance<ReadVIRedV, 0>; 1104def : ReadAdvance<ReadVIRedV0, 0>; 1105def : ReadAdvance<ReadVIWRedV, 0>; 1106def : ReadAdvance<ReadVIWRedV0, 0>; 1107def : ReadAdvance<ReadVFRedV, 0>; 1108def : ReadAdvance<ReadVFRedV0, 0>; 1109def : ReadAdvance<ReadVFRedOV, 0>; 1110def : ReadAdvance<ReadVFRedOV0, 0>; 1111def : ReadAdvance<ReadVFRedMinMaxV, 0>; 1112def : ReadAdvance<ReadVFWRedV, 0>; 1113def : ReadAdvance<ReadVFWRedV0, 0>; 1114def : ReadAdvance<ReadVFWRedOV, 0>; 1115def : ReadAdvance<ReadVFWRedOV0, 0>; 1116 1117// 15. Vector Mask Instructions 1118defm "" : LMULReadAdvance<"ReadVMALUV", 0>; 1119defm "" : LMULReadAdvance<"ReadVMPopV", 0>; 1120defm "" : LMULReadAdvance<"ReadVMFFSV", 0>; 1121defm "" : LMULReadAdvance<"ReadVMSFSV", 0>; 1122defm "" : LMULReadAdvance<"ReadVIotaV", 0>; 1123 1124// 16. Vector Permutation Instructions 1125def : ReadAdvance<ReadVMovXS, 0>; 1126def : ReadAdvance<ReadVMovSX_V, 0>; 1127def : ReadAdvance<ReadVMovSX_X, 0>; 1128def : ReadAdvance<ReadVMovFS, 0>; 1129def : ReadAdvance<ReadVMovSF_V, 0>; 1130def : ReadAdvance<ReadVMovSF_F, 0>; 1131defm "" : LMULReadAdvance<"ReadVISlideV", 0>; 1132defm "" : LMULReadAdvance<"ReadVISlideX", 0>; 1133defm "" : LMULReadAdvance<"ReadVFSlideV", 0>; 1134defm "" : LMULReadAdvance<"ReadVFSlideF", 0>; 1135defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_data", 0>; 1136defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_index", 0>; 1137defm "" : LMULSEWReadAdvance<"ReadVRGatherEI16VV_data", 0>; 1138defm "" : LMULSEWReadAdvance<"ReadVRGatherEI16VV_index", 0>; 1139defm "" : LMULReadAdvance<"ReadVRGatherVX_data", 0>; 1140defm "" : LMULReadAdvance<"ReadVRGatherVX_index", 0>; 1141defm "" : LMULReadAdvance<"ReadVRGatherVI_data", 0>; 1142defm "" : LMULReadAdvance<"ReadVGatherV", 0>; 1143defm "" : LMULSEWReadAdvance<"ReadVCompressV", 0>; 1144// These are already LMUL aware 1145def : ReadAdvance<ReadVMov1V, 0>; 1146def : ReadAdvance<ReadVMov2V, 0>; 1147def : ReadAdvance<ReadVMov4V, 0>; 1148def : ReadAdvance<ReadVMov8V, 0>; 1149 1150// Others 1151def : ReadAdvance<ReadVMask, 0>; 1152def : ReadAdvance<ReadVPassthru_WorstCase, 0>; 1153foreach mx = SchedMxList in { 1154 def : ReadAdvance<!cast<SchedRead>("ReadVPassthru_" # mx), 0>; 1155 foreach sew = SchedSEWSet<mx>.val in 1156 def : ReadAdvance<!cast<SchedRead>("ReadVPassthru_" # mx # "_E" # sew), 0>; 1157} 1158 1159} // Unsupported 1160} // UnsupportedSchedV 1161