1//===-- RISCVProcessors.td - RISC-V Processors -------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// RISC-V processors supported. 11//===----------------------------------------------------------------------===// 12 13// Predefined scheduling direction. 14defvar TopDown = [{ MISched::TopDown }]; 15defvar BottomUp = [{ MISched::BottomUp }]; 16defvar Bidirectional = [{ MISched::Bidirectional }]; 17 18class RISCVTuneInfo { 19 bits<8> PrefFunctionAlignment = 1; 20 bits<8> PrefLoopAlignment = 1; 21 22 // Information needed by LoopDataPrefetch. 23 bits<16> CacheLineSize = 0; 24 bits<16> PrefetchDistance = 0; 25 bits<16> MinPrefetchStride = 1; 26 bits<32> MaxPrefetchIterationsAhead = -1; 27 28 bits<32> MinimumJumpTableEntries = 5; 29 30 // Tail duplication threshold at -O3. 31 bits<32> TailDupAggressiveThreshold = 6; 32 33 bits<32> MaxStoresPerMemsetOptSize = 4; 34 bits<32> MaxStoresPerMemset = 8; 35 36 bits<32> MaxGluedStoresPerMemcpy = 0; 37 bits<32> MaxStoresPerMemcpyOptSize = 4; 38 bits<32> MaxStoresPerMemcpy = 8; 39 40 bits<32> MaxStoresPerMemmoveOptSize = 4; 41 bits<32> MaxStoresPerMemmove = 8; 42 43 bits<32> MaxLoadsPerMemcmpOptSize = 4; 44 bits<32> MaxLoadsPerMemcmp = 8; 45 46 // The direction of PostRA scheduling. 47 code PostRASchedDirection = TopDown; 48} 49 50def RISCVTuneInfoTable : GenericTable { 51 let FilterClass = "RISCVTuneInfo"; 52 let CppTypeName = "RISCVTuneInfo"; 53 let Fields = ["Name", "PrefFunctionAlignment", "PrefLoopAlignment", 54 "CacheLineSize", "PrefetchDistance", "MinPrefetchStride", 55 "MaxPrefetchIterationsAhead", "MinimumJumpTableEntries", 56 "TailDupAggressiveThreshold", "MaxStoresPerMemsetOptSize", 57 "MaxStoresPerMemset", "MaxGluedStoresPerMemcpy", 58 "MaxStoresPerMemcpyOptSize", "MaxStoresPerMemcpy", 59 "MaxStoresPerMemmoveOptSize", "MaxStoresPerMemmove", 60 "MaxLoadsPerMemcmpOptSize", "MaxLoadsPerMemcmp", 61 "PostRASchedDirection"]; 62} 63 64def getRISCVTuneInfo : SearchIndex { 65 let Table = RISCVTuneInfoTable; 66 let Key = ["Name"]; 67} 68 69class GenericTuneInfo: RISCVTuneInfo; 70 71class RISCVProcessorModel<string n, 72 SchedMachineModel m, 73 list<SubtargetFeature> f, 74 list<SubtargetFeature> tunef = [], 75 string default_march = ""> 76 : ProcessorModel<n, m, f, tunef> { 77 string DefaultMarch = default_march; 78 int MVendorID = 0; 79 int MArchID = 0; 80 int MImpID = 0; 81} 82 83class RISCVTuneProcessorModel<string n, 84 SchedMachineModel m, 85 list<SubtargetFeature> tunef = [], 86 list<SubtargetFeature> f = []> 87 : ProcessorModel<n, m, f,tunef>; 88 89defvar GenericTuneFeatures = [TuneOptimizedNF2SegmentLoadStore]; 90 91def GENERIC_RV32 : RISCVProcessorModel<"generic-rv32", 92 NoSchedModel, 93 [Feature32Bit, 94 FeatureStdExtI], 95 GenericTuneFeatures>, 96 GenericTuneInfo; 97def GENERIC_RV64 : RISCVProcessorModel<"generic-rv64", 98 NoSchedModel, 99 [Feature64Bit, 100 FeatureStdExtI], 101 GenericTuneFeatures>, 102 GenericTuneInfo; 103// Support generic for compatibility with other targets. The triple will be used 104// to change to the appropriate rv32/rv64 version. 105def GENERIC : RISCVTuneProcessorModel<"generic", NoSchedModel>, GenericTuneInfo; 106 107def MIPS_P8700 : RISCVProcessorModel<"mips-p8700", 108 MIPSP8700Model, 109 [Feature64Bit, 110 FeatureStdExtI, 111 FeatureStdExtM, 112 FeatureStdExtA, 113 FeatureStdExtF, 114 FeatureStdExtD, 115 FeatureStdExtC, 116 FeatureStdExtZba, 117 FeatureStdExtZbb, 118 FeatureStdExtZifencei, 119 FeatureStdExtZicsr, 120 FeatureVendorXMIPSCMove, 121 FeatureVendorXMIPSLSP], 122 [TuneMIPSP8700]>; 123 124def ROCKET_RV32 : RISCVProcessorModel<"rocket-rv32", 125 RocketModel, 126 [Feature32Bit, 127 FeatureStdExtI, 128 FeatureStdExtZifencei, 129 FeatureStdExtZicsr]>; 130def ROCKET_RV64 : RISCVProcessorModel<"rocket-rv64", 131 RocketModel, 132 [Feature64Bit, 133 FeatureStdExtI, 134 FeatureStdExtZifencei, 135 FeatureStdExtZicsr]>; 136def ROCKET : RISCVTuneProcessorModel<"rocket", 137 RocketModel>; 138 139defvar SiFive7TuneFeatures = [TuneSiFive7, TuneNoDefaultUnroll, 140 TuneShortForwardBranchOpt, 141 TunePostRAScheduler]; 142def SIFIVE_7 : RISCVTuneProcessorModel<"sifive-7-series", 143 SiFive7Model, SiFive7TuneFeatures>; 144 145def SIFIVE_E20 : RISCVProcessorModel<"sifive-e20", 146 RocketModel, 147 [Feature32Bit, 148 FeatureStdExtI, 149 FeatureStdExtZicsr, 150 FeatureStdExtZifencei, 151 FeatureStdExtM, 152 FeatureStdExtC]>; 153 154def SIFIVE_E21 : RISCVProcessorModel<"sifive-e21", 155 RocketModel, 156 [Feature32Bit, 157 FeatureStdExtI, 158 FeatureStdExtZicsr, 159 FeatureStdExtZifencei, 160 FeatureStdExtM, 161 FeatureStdExtA, 162 FeatureStdExtC]>; 163 164def SIFIVE_E24 : RISCVProcessorModel<"sifive-e24", 165 RocketModel, 166 [Feature32Bit, 167 FeatureStdExtI, 168 FeatureStdExtZifencei, 169 FeatureStdExtM, 170 FeatureStdExtA, 171 FeatureStdExtF, 172 FeatureStdExtC]>; 173 174def SIFIVE_E31 : RISCVProcessorModel<"sifive-e31", 175 RocketModel, 176 [Feature32Bit, 177 FeatureStdExtI, 178 FeatureStdExtZifencei, 179 FeatureStdExtZicsr, 180 FeatureStdExtM, 181 FeatureStdExtA, 182 FeatureStdExtC]>; 183 184def SIFIVE_E34 : RISCVProcessorModel<"sifive-e34", 185 RocketModel, 186 [Feature32Bit, 187 FeatureStdExtI, 188 FeatureStdExtZifencei, 189 FeatureStdExtM, 190 FeatureStdExtA, 191 FeatureStdExtF, 192 FeatureStdExtC]>; 193 194def SIFIVE_E76 : RISCVProcessorModel<"sifive-e76", 195 SiFive7Model, 196 [Feature32Bit, 197 FeatureStdExtI, 198 FeatureStdExtZifencei, 199 FeatureStdExtM, 200 FeatureStdExtA, 201 FeatureStdExtF, 202 FeatureStdExtC], 203 SiFive7TuneFeatures>; 204 205def SIFIVE_S21 : RISCVProcessorModel<"sifive-s21", 206 RocketModel, 207 [Feature64Bit, 208 FeatureStdExtI, 209 FeatureStdExtZicsr, 210 FeatureStdExtZifencei, 211 FeatureStdExtM, 212 FeatureStdExtA, 213 FeatureStdExtC]>; 214 215def SIFIVE_S51 : RISCVProcessorModel<"sifive-s51", 216 RocketModel, 217 [Feature64Bit, 218 FeatureStdExtI, 219 FeatureStdExtZicsr, 220 FeatureStdExtZifencei, 221 FeatureStdExtM, 222 FeatureStdExtA, 223 FeatureStdExtC]>; 224 225def SIFIVE_S54 : RISCVProcessorModel<"sifive-s54", 226 RocketModel, 227 [Feature64Bit, 228 FeatureStdExtI, 229 FeatureStdExtZifencei, 230 FeatureStdExtM, 231 FeatureStdExtA, 232 FeatureStdExtF, 233 FeatureStdExtD, 234 FeatureStdExtC]>; 235 236def SIFIVE_S76 : RISCVProcessorModel<"sifive-s76", 237 SiFive7Model, 238 [Feature64Bit, 239 FeatureStdExtI, 240 FeatureStdExtZifencei, 241 FeatureStdExtM, 242 FeatureStdExtA, 243 FeatureStdExtF, 244 FeatureStdExtD, 245 FeatureStdExtC, 246 FeatureStdExtZihintpause], 247 SiFive7TuneFeatures>; 248 249def SIFIVE_U54 : RISCVProcessorModel<"sifive-u54", 250 RocketModel, 251 [Feature64Bit, 252 FeatureStdExtI, 253 FeatureStdExtZifencei, 254 FeatureStdExtM, 255 FeatureStdExtA, 256 FeatureStdExtF, 257 FeatureStdExtD, 258 FeatureStdExtC]>; 259 260def SIFIVE_U74 : RISCVProcessorModel<"sifive-u74", 261 SiFive7Model, 262 [Feature64Bit, 263 FeatureStdExtI, 264 FeatureStdExtZifencei, 265 FeatureStdExtM, 266 FeatureStdExtA, 267 FeatureStdExtF, 268 FeatureStdExtD, 269 FeatureStdExtC], 270 SiFive7TuneFeatures>; 271 272defvar SiFiveX280TuneFeatures = !listconcat(SiFive7TuneFeatures, 273 [TuneDLenFactor2, 274 TuneOptimizedZeroStrideLoad, 275 TuneOptimizedNF2SegmentLoadStore]); 276def SIFIVE_X280 : RISCVProcessorModel<"sifive-x280", SiFive7Model, 277 [Feature64Bit, 278 FeatureStdExtI, 279 FeatureStdExtZifencei, 280 FeatureStdExtM, 281 FeatureStdExtA, 282 FeatureStdExtF, 283 FeatureStdExtD, 284 FeatureStdExtC, 285 FeatureStdExtV, 286 FeatureStdExtZvl512b, 287 FeatureStdExtZfh, 288 FeatureStdExtZvfh, 289 FeatureStdExtZba, 290 FeatureStdExtZbb], 291 SiFiveX280TuneFeatures>; 292 293defvar SiFiveP400TuneFeatures = [TuneNoDefaultUnroll, 294 TuneConditionalCompressedMoveFusion, 295 TuneLUIADDIFusion, 296 TuneAUIPCADDIFusion, 297 TunePostRAScheduler]; 298 299def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", SiFiveP400Model, 300 !listconcat(RVA22U64Features, 301 [FeatureStdExtZifencei, 302 FeatureStdExtZihintntl, 303 FeatureUnalignedScalarMem, 304 FeatureUnalignedVectorMem]), 305 SiFiveP400TuneFeatures>; 306 307def SIFIVE_P470 : RISCVProcessorModel<"sifive-p470", SiFiveP400Model, 308 !listconcat(RVA22U64Features, 309 [FeatureStdExtV, 310 FeatureStdExtZifencei, 311 FeatureStdExtZihintntl, 312 FeatureStdExtZvl128b, 313 FeatureStdExtZvbb, 314 FeatureStdExtZvknc, 315 FeatureStdExtZvkng, 316 FeatureStdExtZvksc, 317 FeatureStdExtZvksg, 318 FeatureVendorXSiFivecdiscarddlone, 319 FeatureVendorXSiFivecflushdlone, 320 FeatureUnalignedScalarMem, 321 FeatureUnalignedVectorMem]), 322 !listconcat(SiFiveP400TuneFeatures, 323 [TuneNoSinkSplatOperands, 324 TuneVXRMPipelineFlush])>; 325 326defvar SiFiveP500TuneFeatures = [TuneNoDefaultUnroll, 327 TuneConditionalCompressedMoveFusion, 328 TuneLUIADDIFusion, 329 TuneAUIPCADDIFusion, 330 TunePostRAScheduler]; 331 332def SIFIVE_P550 : RISCVProcessorModel<"sifive-p550", SiFiveP500Model, 333 [Feature64Bit, 334 FeatureStdExtI, 335 FeatureStdExtZifencei, 336 FeatureStdExtM, 337 FeatureStdExtA, 338 FeatureStdExtF, 339 FeatureStdExtD, 340 FeatureStdExtC, 341 FeatureStdExtZba, 342 FeatureStdExtZbb], 343 SiFiveP500TuneFeatures>; 344 345def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", SiFiveP600Model, 346 !listconcat(RVA22U64Features, 347 [FeatureStdExtV, 348 FeatureStdExtZifencei, 349 FeatureStdExtZihintntl, 350 FeatureStdExtZvl128b, 351 FeatureStdExtZvbb, 352 FeatureStdExtZvknc, 353 FeatureStdExtZvkng, 354 FeatureStdExtZvksc, 355 FeatureStdExtZvksg, 356 FeatureUnalignedScalarMem, 357 FeatureUnalignedVectorMem]), 358 [TuneNoDefaultUnroll, 359 TuneConditionalCompressedMoveFusion, 360 TuneLUIADDIFusion, 361 TuneAUIPCADDIFusion, 362 TuneNoSinkSplatOperands, 363 TuneVXRMPipelineFlush, 364 TunePostRAScheduler]>; 365 366def SYNTACORE_SCR1_BASE : RISCVProcessorModel<"syntacore-scr1-base", 367 SyntacoreSCR1Model, 368 [Feature32Bit, 369 FeatureStdExtI, 370 FeatureStdExtZicsr, 371 FeatureStdExtZifencei, 372 FeatureStdExtC], 373 [TuneNoDefaultUnroll]>; 374 375def SYNTACORE_SCR1_MAX : RISCVProcessorModel<"syntacore-scr1-max", 376 SyntacoreSCR1Model, 377 [Feature32Bit, 378 FeatureStdExtI, 379 FeatureStdExtZicsr, 380 FeatureStdExtZifencei, 381 FeatureStdExtM, 382 FeatureStdExtC], 383 [TuneNoDefaultUnroll]>; 384 385def SYNTACORE_SCR3_RV32 : RISCVProcessorModel<"syntacore-scr3-rv32", 386 SyntacoreSCR3RV32Model, 387 [Feature32Bit, 388 FeatureStdExtI, 389 FeatureStdExtZicsr, 390 FeatureStdExtZifencei, 391 FeatureStdExtM, 392 FeatureStdExtC], 393 [TuneNoDefaultUnroll, TunePostRAScheduler]>; 394 395def SYNTACORE_SCR3_RV64 : RISCVProcessorModel<"syntacore-scr3-rv64", 396 SyntacoreSCR3RV64Model, 397 [Feature64Bit, 398 FeatureStdExtI, 399 FeatureStdExtZicsr, 400 FeatureStdExtZifencei, 401 FeatureStdExtM, 402 FeatureStdExtA, 403 FeatureStdExtC], 404 [TuneNoDefaultUnroll, TunePostRAScheduler]>; 405 406def SYNTACORE_SCR4_RV32 : RISCVProcessorModel<"syntacore-scr4-rv32", 407 SyntacoreSCR4RV32Model, 408 [Feature32Bit, 409 FeatureStdExtI, 410 FeatureStdExtZicsr, 411 FeatureStdExtZifencei, 412 FeatureStdExtM, 413 FeatureStdExtF, 414 FeatureStdExtD, 415 FeatureStdExtC], 416 [TuneNoDefaultUnroll, TunePostRAScheduler]>; 417 418def SYNTACORE_SCR4_RV64 : RISCVProcessorModel<"syntacore-scr4-rv64", 419 SyntacoreSCR4RV64Model, 420 [Feature64Bit, 421 FeatureStdExtI, 422 FeatureStdExtZicsr, 423 FeatureStdExtZifencei, 424 FeatureStdExtM, 425 FeatureStdExtA, 426 FeatureStdExtF, 427 FeatureStdExtD, 428 FeatureStdExtC], 429 [TuneNoDefaultUnroll, TunePostRAScheduler]>; 430 431def SYNTACORE_SCR5_RV32 : RISCVProcessorModel<"syntacore-scr5-rv32", 432 SyntacoreSCR5RV32Model, 433 [Feature32Bit, 434 FeatureStdExtI, 435 FeatureStdExtZicsr, 436 FeatureStdExtZifencei, 437 FeatureStdExtM, 438 FeatureStdExtA, 439 FeatureStdExtF, 440 FeatureStdExtD, 441 FeatureStdExtC], 442 [TuneNoDefaultUnroll, TunePostRAScheduler]>; 443 444def SYNTACORE_SCR5_RV64 : RISCVProcessorModel<"syntacore-scr5-rv64", 445 SyntacoreSCR5RV64Model, 446 [Feature64Bit, 447 FeatureStdExtI, 448 FeatureStdExtZicsr, 449 FeatureStdExtZifencei, 450 FeatureStdExtM, 451 FeatureStdExtA, 452 FeatureStdExtF, 453 FeatureStdExtD, 454 FeatureStdExtC], 455 [TuneNoDefaultUnroll, TunePostRAScheduler]>; 456 457def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7", 458 SyntacoreSCR7Model, 459 [Feature64Bit, 460 FeatureStdExtI, 461 FeatureStdExtZicsr, 462 FeatureStdExtZifencei, 463 FeatureStdExtM, 464 FeatureStdExtA, 465 FeatureStdExtF, 466 FeatureStdExtD, 467 FeatureStdExtC, 468 FeatureStdExtV, 469 FeatureStdExtZba, 470 FeatureStdExtZbb, 471 FeatureStdExtZbc, 472 FeatureStdExtZbs, 473 FeatureStdExtZkn], 474 [TuneNoDefaultUnroll, TunePostRAScheduler]>; 475 476def TENSTORRENT_ASCALON_D8 : RISCVProcessorModel<"tt-ascalon-d8", 477 TTAscalonD8Model, 478 !listconcat(RVA23S64Features, 479 [FeatureStdExtSmaia, 480 FeatureStdExtSsaia, 481 FeatureStdExtSscofpmf, 482 FeatureStdExtSsstrict, 483 FeatureStdExtZfbfmin, 484 FeatureStdExtZfh, 485 FeatureStdExtZicsr, 486 FeatureStdExtZvbc, 487 FeatureStdExtZvfbfmin, 488 FeatureStdExtZvfbfwma, 489 FeatureStdExtZvfh, 490 FeatureStdExtZvkng, 491 FeatureStdExtZvl256b, 492 FeatureUnalignedScalarMem, 493 FeatureUnalignedVectorMem]), 494 [TuneNoDefaultUnroll, 495 TuneOptimizedZeroStrideLoad, 496 TunePostRAScheduler]>; 497 498def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1", 499 NoSchedModel, 500 [Feature64Bit, 501 FeatureStdExtI, 502 FeatureStdExtZifencei, 503 FeatureStdExtZicsr, 504 FeatureStdExtZicntr, 505 FeatureStdExtZihpm, 506 FeatureStdExtZihintpause, 507 FeatureStdExtM, 508 FeatureStdExtA, 509 FeatureStdExtF, 510 FeatureStdExtD, 511 FeatureStdExtC, 512 FeatureStdExtZba, 513 FeatureStdExtZbb, 514 FeatureStdExtZbc, 515 FeatureStdExtZbs, 516 FeatureStdExtZicbom, 517 FeatureStdExtZicbop, 518 FeatureStdExtZicboz, 519 FeatureVendorXVentanaCondOps], 520 [TuneVentanaVeyron, 521 TuneLUIADDIFusion, 522 TuneAUIPCADDIFusion, 523 TuneZExtHFusion, 524 TuneZExtWFusion, 525 TuneShiftedZExtWFusion, 526 TuneLDADDFusion]> { 527 let MVendorID = 0x61f; 528 let MArchID = 0x8000000000010000; 529 let MImpID = 0x111; 530} 531 532def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu", 533 XiangShanNanHuModel, 534 [Feature64Bit, 535 FeatureStdExtI, 536 FeatureStdExtZicsr, 537 FeatureStdExtZifencei, 538 FeatureStdExtM, 539 FeatureStdExtA, 540 FeatureStdExtF, 541 FeatureStdExtD, 542 FeatureStdExtC, 543 FeatureStdExtZba, 544 FeatureStdExtZbb, 545 FeatureStdExtZbc, 546 FeatureStdExtZbs, 547 FeatureStdExtZkn, 548 FeatureStdExtZksed, 549 FeatureStdExtZksh, 550 FeatureStdExtSvinval, 551 FeatureStdExtZicbom, 552 FeatureStdExtZicboz], 553 [TuneNoDefaultUnroll, 554 TuneZExtHFusion, 555 TuneZExtWFusion, 556 TuneShiftedZExtWFusion]>; 557 558def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60", 559 NoSchedModel, 560 !listconcat(RVA22S64Features, 561 [FeatureStdExtV, 562 FeatureStdExtSscofpmf, 563 FeatureStdExtSstc, 564 FeatureStdExtSvnapot, 565 FeatureStdExtZbc, 566 FeatureStdExtZbkc, 567 FeatureStdExtZfh, 568 FeatureStdExtZicond, 569 FeatureStdExtZvfh, 570 FeatureStdExtZvkt, 571 FeatureStdExtZvl256b, 572 FeatureUnalignedScalarMem]), 573 [TuneDLenFactor2, 574 TuneOptimizedNF2SegmentLoadStore, 575 TuneOptimizedNF3SegmentLoadStore, 576 TuneOptimizedNF4SegmentLoadStore, 577 TuneVXRMPipelineFlush]> { 578 let MVendorID = 0x710; 579 let MArchID = 0x8000000058000001; 580 let MImpID = 0x1000000049772200; 581} 582 583def RP2350_HAZARD3 : RISCVProcessorModel<"rp2350-hazard3", 584 NoSchedModel, 585 [Feature32Bit, 586 FeatureStdExtI, 587 FeatureStdExtM, 588 FeatureStdExtA, 589 FeatureStdExtC, 590 FeatureStdExtZicsr, 591 FeatureStdExtZifencei, 592 FeatureStdExtZba, 593 FeatureStdExtZbb, 594 FeatureStdExtZbs, 595 FeatureStdExtZbkb, 596 FeatureStdExtZcb, 597 FeatureStdExtZcmp]>; 598