1//===-- RISCVInstrInfoZfh.td - RISC-V 'Zfh' instructions ---*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the RISC-V instructions from the standard 'Zfh' 10// half-precision floating-point extension, version 1.0. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// RISC-V specific DAG Nodes. 16//===----------------------------------------------------------------------===// 17 18def SDT_RISCVFMV_H_X 19 : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, XLenVT>]>; 20def SDT_RISCVFMV_X_EXTH 21 : SDTypeProfile<1, 1, [SDTCisVT<0, XLenVT>, SDTCisFP<1>]>; 22 23def riscv_fmv_h_x 24 : SDNode<"RISCVISD::FMV_H_X", SDT_RISCVFMV_H_X>; 25def riscv_fmv_x_anyexth 26 : SDNode<"RISCVISD::FMV_X_ANYEXTH", SDT_RISCVFMV_X_EXTH>; 27def riscv_fmv_x_signexth 28 : SDNode<"RISCVISD::FMV_X_SIGNEXTH", SDT_RISCVFMV_X_EXTH>; 29 30//===----------------------------------------------------------------------===// 31// Operand and SDNode transformation definitions. 32//===----------------------------------------------------------------------===// 33 34// Zhinxmin and Zhinx 35 36def GPRAsFPR16 : AsmOperandClass { 37 let Name = "GPRAsFPR16"; 38 let ParserMethod = "parseGPRAsFPR"; 39 let RenderMethod = "addRegOperands"; 40} 41 42def FPR16INX : RegisterOperand<GPRF16> { 43 let ParserMatchClass = GPRAsFPR16; 44} 45 46def ZfhExt : ExtInfo<"", "", [HasStdExtZfh], 47 f16, FPR16, FPR32, ?, FPR16>; 48def ZfhminExt : ExtInfo<"", "", [HasStdExtZfhmin], 49 f16, FPR16, FPR32, ?, FPR16>; 50def ZfhDExt : ExtInfo<"", "", [HasStdExtZfh, HasStdExtD], 51 ?, ?, FPR32, FPR64, FPR16>; 52def ZfhminDExt : ExtInfo<"", "", [HasStdExtZfhmin, HasStdExtD], 53 ?, ?, FPR32, FPR64, FPR16>; 54 55def ZhinxExt : ExtInfo<"_INX", "RVZfinx", 56 [HasStdExtZhinx], 57 f16, FPR16INX, FPR32INX, ?, FPR16INX>; 58def ZhinxminExt : ExtInfo<"_INX", "RVZfinx", 59 [HasStdExtZhinxmin], 60 f16, FPR16INX, FPR32INX, ?, FPR16INX>; 61def ZhinxZdinxExt : ExtInfo<"_INX", "RVZfinx", 62 [HasStdExtZhinx, HasStdExtZdinx, IsRV64], 63 ?, ?, FPR32INX, FPR64INX, FPR16INX>; 64def ZhinxminZdinxExt : ExtInfo<"_INX", "RVZfinx", 65 [HasStdExtZhinxmin, HasStdExtZdinx, IsRV64], 66 ?, ?, FPR32INX, FPR64INX, FPR16INX>; 67def ZhinxZdinx32Ext : ExtInfo<"_IN32X", "RV32Zdinx", 68 [HasStdExtZhinx, HasStdExtZdinx, IsRV32], 69 ?, ?, FPR32INX, FPR64IN32X, FPR16INX >; 70def ZhinxminZdinx32Ext : ExtInfo<"_IN32X", "RV32Zdinx", 71 [HasStdExtZhinxmin, HasStdExtZdinx, IsRV32], 72 ?, ?, FPR32INX, FPR64IN32X, FPR16INX>; 73 74defvar ZfhExts = [ZfhExt, ZhinxExt]; 75defvar ZfhminExts = [ZfhminExt, ZhinxminExt]; 76defvar ZfhDExts = [ZfhDExt, ZhinxZdinxExt, ZhinxZdinx32Ext]; 77defvar ZfhminDExts = [ZfhminDExt, ZhinxminZdinxExt, ZhinxminZdinx32Ext]; 78 79//===----------------------------------------------------------------------===// 80// Instructions 81//===----------------------------------------------------------------------===// 82 83let Predicates = [HasHalfFPLoadStoreMove] in { 84def FLH : FPLoad_r<0b001, "flh", FPR16, WriteFLD16>; 85 86// Operands for stores are in the order srcreg, base, offset rather than 87// reflecting the order these fields are specified in the instruction 88// encoding. 89def FSH : FPStore_r<0b001, "fsh", FPR16, WriteFST16>; 90} // Predicates = [HasHalfFPLoadStoreMove] 91 92let Predicates = [HasStdExtZhinxmin], isCodeGenOnly = 1 in { 93def LH_INX : Load_ri<0b001, "lh", GPRF16>, Sched<[WriteLDH, ReadMemBase]>; 94def SH_INX : Store_rri<0b001, "sh", GPRF16>, 95 Sched<[WriteSTH, ReadStoreData, ReadMemBase]>; 96 97// ADDI with GPRF16 register class to use for copy. This should not be used as 98// general ADDI, so the immediate should always be zero. 99let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveReg = 1, 100 hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 101def PseudoMV_FPR16INX : Pseudo<(outs GPRF16:$rd), (ins GPRF16:$rs), []>, 102 Sched<[WriteIALU, ReadIALU]>; 103} 104 105foreach Ext = ZfhExts in { 106 let SchedRW = [WriteFMA16, ReadFMA16, ReadFMA16, ReadFMA16Addend] in { 107 defm FMADD_H : FPFMA_rrr_frm_m<OPC_MADD, 0b10, "fmadd.h", Ext>; 108 defm FMSUB_H : FPFMA_rrr_frm_m<OPC_MSUB, 0b10, "fmsub.h", Ext>; 109 defm FNMSUB_H : FPFMA_rrr_frm_m<OPC_NMSUB, 0b10, "fnmsub.h", Ext>; 110 defm FNMADD_H : FPFMA_rrr_frm_m<OPC_NMADD, 0b10, "fnmadd.h", Ext>; 111 } 112 113 let SchedRW = [WriteFAdd16, ReadFAdd16, ReadFAdd16] in { 114 defm FADD_H : FPALU_rr_frm_m<0b0000010, "fadd.h", Ext, Commutable=1>; 115 defm FSUB_H : FPALU_rr_frm_m<0b0000110, "fsub.h", Ext>; 116 } 117 let SchedRW = [WriteFMul16, ReadFMul16, ReadFMul16] in 118 defm FMUL_H : FPALU_rr_frm_m<0b0001010, "fmul.h", Ext, Commutable=1>; 119 120 let SchedRW = [WriteFDiv16, ReadFDiv16, ReadFDiv16] in 121 defm FDIV_H : FPALU_rr_frm_m<0b0001110, "fdiv.h", Ext>; 122 123 defm FSQRT_H : FPUnaryOp_r_frm_m<0b0101110, 0b00000, Ext, Ext.PrimaryTy, 124 Ext.PrimaryTy, "fsqrt.h">, 125 Sched<[WriteFSqrt16, ReadFSqrt16]>; 126 127 let SchedRW = [WriteFSGNJ16, ReadFSGNJ16, ReadFSGNJ16], 128 mayRaiseFPException = 0 in { 129 defm FSGNJ_H : FPALU_rr_m<0b0010010, 0b000, "fsgnj.h", Ext>; 130 defm FSGNJN_H : FPALU_rr_m<0b0010010, 0b001, "fsgnjn.h", Ext>; 131 defm FSGNJX_H : FPALU_rr_m<0b0010010, 0b010, "fsgnjx.h", Ext>; 132 } 133 134 let SchedRW = [WriteFMinMax16, ReadFMinMax16, ReadFMinMax16] in { 135 defm FMIN_H : FPALU_rr_m<0b0010110, 0b000, "fmin.h", Ext, Commutable=1>; 136 defm FMAX_H : FPALU_rr_m<0b0010110, 0b001, "fmax.h", Ext, Commutable=1>; 137 } 138 139 let IsSignExtendingOpW = 1 in 140 defm FCVT_W_H : FPUnaryOp_r_frm_m<0b1100010, 0b00000, Ext, GPR, Ext.PrimaryTy, 141 "fcvt.w.h">, 142 Sched<[WriteFCvtF16ToI32, ReadFCvtF16ToI32]>; 143 144 let IsSignExtendingOpW = 1 in 145 defm FCVT_WU_H : FPUnaryOp_r_frm_m<0b1100010, 0b00001, Ext, GPR, Ext.PrimaryTy, 146 "fcvt.wu.h">, 147 Sched<[WriteFCvtF16ToI32, ReadFCvtF16ToI32]>; 148 149 defm FCVT_H_W : FPUnaryOp_r_frm_m<0b1101010, 0b00000, Ext, Ext.PrimaryTy, GPR, 150 "fcvt.h.w">, 151 Sched<[WriteFCvtI32ToF16, ReadFCvtI32ToF16]>; 152 153 defm FCVT_H_WU : FPUnaryOp_r_frm_m<0b1101010, 0b00001, Ext, Ext.PrimaryTy, GPR, 154 "fcvt.h.wu">, 155 Sched<[WriteFCvtI32ToF16, ReadFCvtI32ToF16]>; 156} // foreach Ext = ZfhExts 157 158foreach Ext = ZfhminExts in { 159 defm FCVT_H_S : FPUnaryOp_r_frm_m<0b0100010, 0b00000, Ext, Ext.PrimaryTy, 160 Ext.F32Ty, "fcvt.h.s">, 161 Sched<[WriteFCvtF32ToF16, ReadFCvtF32ToF16]>; 162 163 defm FCVT_S_H : FPUnaryOp_r_frmlegacy_m<0b0100000, 0b00010,Ext, Ext.F32Ty, 164 Ext.PrimaryTy, "fcvt.s.h">, 165 Sched<[WriteFCvtF16ToF32, ReadFCvtF16ToF32]>; 166} // foreach Ext = ZfhminExts 167 168let Predicates = [HasHalfFPLoadStoreMove] in { 169let mayRaiseFPException = 0, IsSignExtendingOpW = 1 in 170def FMV_X_H : FPUnaryOp_r<0b1110010, 0b00000, 0b000, GPR, FPR16, "fmv.x.h">, 171 Sched<[WriteFMovF16ToI16, ReadFMovF16ToI16]>; 172 173let mayRaiseFPException = 0 in 174def FMV_H_X : FPUnaryOp_r<0b1111010, 0b00000, 0b000, FPR16, GPR, "fmv.h.x">, 175 Sched<[WriteFMovI16ToF16, ReadFMovI16ToF16]>; 176} // Predicates = [HasHalfFPLoadStoreMove] 177 178foreach Ext = ZfhExts in { 179 let SchedRW = [WriteFCmp16, ReadFCmp16, ReadFCmp16] in { 180 defm FEQ_H : FPCmp_rr_m<0b1010010, 0b010, "feq.h", Ext, Commutable=1>; 181 defm FLT_H : FPCmp_rr_m<0b1010010, 0b001, "flt.h", Ext>; 182 defm FLE_H : FPCmp_rr_m<0b1010010, 0b000, "fle.h", Ext>; 183 } 184 185 let mayRaiseFPException = 0 in 186 defm FCLASS_H : FPUnaryOp_r_m<0b1110010, 0b00000, 0b001, Ext, GPR, Ext.PrimaryTy, 187 "fclass.h">, 188 Sched<[WriteFClass16, ReadFClass16]>; 189 190 defm FCVT_L_H : FPUnaryOp_r_frm_m<0b1100010, 0b00010, Ext, GPR, Ext.PrimaryTy, 191 "fcvt.l.h", [IsRV64]>, 192 Sched<[WriteFCvtF16ToI64, ReadFCvtF16ToI64]>; 193 194 defm FCVT_LU_H : FPUnaryOp_r_frm_m<0b1100010, 0b00011, Ext, GPR, Ext.PrimaryTy, 195 "fcvt.lu.h", [IsRV64]>, 196 Sched<[WriteFCvtF16ToI64, ReadFCvtF16ToI64]>; 197 198 defm FCVT_H_L : FPUnaryOp_r_frm_m<0b1101010, 0b00010, Ext, Ext.PrimaryTy, GPR, 199 "fcvt.h.l", [IsRV64]>, 200 Sched<[WriteFCvtI64ToF16, ReadFCvtI64ToF16]>; 201 202 defm FCVT_H_LU : FPUnaryOp_r_frm_m<0b1101010, 0b00011, Ext, Ext.PrimaryTy, GPR, 203 "fcvt.h.lu", [IsRV64]>, 204 Sched<[WriteFCvtI64ToF16, ReadFCvtI64ToF16]>; 205} // foreach Ext = ZfhExts 206 207foreach Ext = ZfhminDExts in { 208 defm FCVT_H_D : FPUnaryOp_r_frm_m<0b0100010, 0b00001, Ext, Ext.F16Ty, 209 Ext.F64Ty, "fcvt.h.d">, 210 Sched<[WriteFCvtF64ToF16, ReadFCvtF64ToF16]>; 211 212 defm FCVT_D_H : FPUnaryOp_r_frmlegacy_m<0b0100001, 0b00010, Ext, Ext.F64Ty, 213 Ext.F16Ty, "fcvt.d.h">, 214 Sched<[WriteFCvtF16ToF64, ReadFCvtF16ToF64]>; 215} // foreach Ext = ZfhminDExts 216 217//===----------------------------------------------------------------------===// 218// Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20) 219//===----------------------------------------------------------------------===// 220 221let Predicates = [HasStdExtZfhmin] in { 222def : InstAlias<"flh $rd, (${rs1})", (FLH FPR16:$rd, GPR:$rs1, 0), 0>; 223def : InstAlias<"fsh $rs2, (${rs1})", (FSH FPR16:$rs2, GPR:$rs1, 0), 0>; 224} // Predicates = [HasStdExtZfhmin] 225 226let Predicates = [HasStdExtZfh] in { 227def : InstAlias<"fmv.h $rd, $rs", (FSGNJ_H FPR16:$rd, FPR16:$rs, FPR16:$rs)>; 228def : InstAlias<"fabs.h $rd, $rs", (FSGNJX_H FPR16:$rd, FPR16:$rs, FPR16:$rs)>; 229def : InstAlias<"fneg.h $rd, $rs", (FSGNJN_H FPR16:$rd, FPR16:$rs, FPR16:$rs)>; 230 231// fgt.h/fge.h are recognised by the GNU assembler but the canonical 232// flt.h/fle.h forms will always be printed. Therefore, set a zero weight. 233def : InstAlias<"fgt.h $rd, $rs, $rt", 234 (FLT_H GPR:$rd, FPR16:$rt, FPR16:$rs), 0>; 235def : InstAlias<"fge.h $rd, $rs, $rt", 236 (FLE_H GPR:$rd, FPR16:$rt, FPR16:$rs), 0>; 237 238let usesCustomInserter = 1 in { 239def PseudoQuietFLE_H : PseudoQuietFCMP<FPR16>; 240def PseudoQuietFLT_H : PseudoQuietFCMP<FPR16>; 241} 242} // Predicates = [HasStdExtZfh] 243 244let Predicates = [HasStdExtZfhmin] in { 245def PseudoFLH : PseudoFloatLoad<"flh", FPR16>; 246def PseudoFSH : PseudoStore<"fsh", FPR16>; 247} // Predicates = [HasStdExtZfhmin] 248 249let Predicates = [HasStdExtZhinx] in { 250def : InstAlias<"fmv.h $rd, $rs", (FSGNJ_H_INX FPR16INX:$rd, FPR16INX:$rs, FPR16INX:$rs)>; 251def : InstAlias<"fabs.h $rd, $rs", (FSGNJX_H_INX FPR16INX:$rd, FPR16INX:$rs, FPR16INX:$rs)>; 252def : InstAlias<"fneg.h $rd, $rs", (FSGNJN_H_INX FPR16INX:$rd, FPR16INX:$rs, FPR16INX:$rs)>; 253 254def : InstAlias<"fgt.h $rd, $rs, $rt", 255 (FLT_H_INX GPR:$rd, FPR16INX:$rt, FPR16INX:$rs), 0>; 256def : InstAlias<"fge.h $rd, $rs, $rt", 257 (FLE_H_INX GPR:$rd, FPR16INX:$rt, FPR16INX:$rs), 0>; 258 259let usesCustomInserter = 1 in { 260def PseudoQuietFLE_H_INX : PseudoQuietFCMP<FPR16INX>; 261def PseudoQuietFLT_H_INX : PseudoQuietFCMP<FPR16INX>; 262} 263} // Predicates = [HasStdExtZhinxmin] 264 265//===----------------------------------------------------------------------===// 266// Pseudo-instructions and codegen patterns 267//===----------------------------------------------------------------------===// 268 269 270/// Float conversion operations 271 272// [u]int32<->float conversion patterns must be gated on IsRV32 or IsRV64, so 273// are defined later. 274 275/// Float arithmetic operations 276 277foreach Ext = ZfhExts in { 278 defm : PatFprFprDynFrm_m<any_fadd, FADD_H, Ext>; 279 defm : PatFprFprDynFrm_m<any_fsub, FSUB_H, Ext>; 280 defm : PatFprFprDynFrm_m<any_fmul, FMUL_H, Ext>; 281 defm : PatFprFprDynFrm_m<any_fdiv, FDIV_H, Ext>; 282} 283 284let Predicates = [HasStdExtZfh] in { 285def : Pat<(f16 (any_fsqrt FPR16:$rs1)), (FSQRT_H FPR16:$rs1, FRM_DYN)>; 286 287def : Pat<(f16 (fneg FPR16:$rs1)), (FSGNJN_H $rs1, $rs1)>; 288def : Pat<(f16 (fabs FPR16:$rs1)), (FSGNJX_H $rs1, $rs1)>; 289 290def : Pat<(riscv_fclass (f16 FPR16:$rs1)), (FCLASS_H $rs1)>; 291 292def : PatFprFpr<fcopysign, FSGNJ_H, FPR16, f16>; 293def : PatFprFpr<riscv_fsgnjx, FSGNJX_H, FPR16, f16>; 294def : Pat<(f16 (fcopysign FPR16:$rs1, (f16 (fneg FPR16:$rs2)))), 295 (FSGNJN_H FPR16:$rs1, FPR16:$rs2)>; 296def : Pat<(f16 (fcopysign FPR16:$rs1, FPR32:$rs2)), 297 (FSGNJ_H $rs1, (f16 (FCVT_H_S $rs2, FRM_DYN)))>; 298 299// fmadd: rs1 * rs2 + rs3 300def : Pat<(f16 (any_fma FPR16:$rs1, FPR16:$rs2, FPR16:$rs3)), 301 (FMADD_H $rs1, $rs2, $rs3, FRM_DYN)>; 302 303// fmsub: rs1 * rs2 - rs3 304def : Pat<(f16 (any_fma FPR16:$rs1, FPR16:$rs2, (fneg FPR16:$rs3))), 305 (FMSUB_H FPR16:$rs1, FPR16:$rs2, FPR16:$rs3, FRM_DYN)>; 306 307// fnmsub: -rs1 * rs2 + rs3 308def : Pat<(f16 (any_fma (fneg FPR16:$rs1), FPR16:$rs2, FPR16:$rs3)), 309 (FNMSUB_H FPR16:$rs1, FPR16:$rs2, FPR16:$rs3, FRM_DYN)>; 310 311// fnmadd: -rs1 * rs2 - rs3 312def : Pat<(f16 (any_fma (fneg FPR16:$rs1), FPR16:$rs2, (fneg FPR16:$rs3))), 313 (FNMADD_H FPR16:$rs1, FPR16:$rs2, FPR16:$rs3, FRM_DYN)>; 314 315// fnmadd: -(rs1 * rs2 + rs3) (the nsz flag on the FMA) 316def : Pat<(f16 (fneg (any_fma_nsz FPR16:$rs1, FPR16:$rs2, FPR16:$rs3))), 317 (FNMADD_H FPR16:$rs1, FPR16:$rs2, FPR16:$rs3, FRM_DYN)>; 318} // Predicates = [HasStdExtZfh] 319 320let Predicates = [HasStdExtZhinx] in { 321 322/// Float conversion operations 323 324// [u]int32<->float conversion patterns must be gated on IsRV32 or IsRV64, so 325// are defined later. 326 327/// Float arithmetic operations 328 329def : Pat<(any_fsqrt FPR16INX:$rs1), (FSQRT_H_INX FPR16INX:$rs1, FRM_DYN)>; 330 331def : Pat<(fneg FPR16INX:$rs1), (FSGNJN_H_INX $rs1, $rs1)>; 332def : Pat<(fabs FPR16INX:$rs1), (FSGNJX_H_INX $rs1, $rs1)>; 333 334def : Pat<(riscv_fclass FPR16INX:$rs1), (FCLASS_H_INX $rs1)>; 335 336def : PatFprFpr<fcopysign, FSGNJ_H_INX, FPR16INX, f16>; 337def : PatFprFpr<riscv_fsgnjx, FSGNJX_H_INX, FPR16INX, f16>; 338def : Pat<(fcopysign FPR16INX:$rs1, (fneg FPR16INX:$rs2)), 339 (FSGNJN_H_INX FPR16INX:$rs1, FPR16INX:$rs2)>; 340def : Pat<(fcopysign FPR16INX:$rs1, FPR32INX:$rs2), 341 (FSGNJ_H_INX $rs1, (FCVT_H_S_INX $rs2, FRM_DYN))>; 342 343// fmadd: rs1 * rs2 + rs3 344def : Pat<(any_fma FPR16INX:$rs1, FPR16INX:$rs2, FPR16INX:$rs3), 345 (FMADD_H_INX $rs1, $rs2, $rs3, FRM_DYN)>; 346 347// fmsub: rs1 * rs2 - rs3 348def : Pat<(any_fma FPR16INX:$rs1, FPR16INX:$rs2, (fneg FPR16INX:$rs3)), 349 (FMSUB_H_INX FPR16INX:$rs1, FPR16INX:$rs2, FPR16INX:$rs3, FRM_DYN)>; 350 351// fnmsub: -rs1 * rs2 + rs3 352def : Pat<(any_fma (fneg FPR16INX:$rs1), FPR16INX:$rs2, FPR16INX:$rs3), 353 (FNMSUB_H_INX FPR16INX:$rs1, FPR16INX:$rs2, FPR16INX:$rs3, FRM_DYN)>; 354 355// fnmadd: -rs1 * rs2 - rs3 356def : Pat<(any_fma (fneg FPR16INX:$rs1), FPR16INX:$rs2, (fneg FPR16INX:$rs3)), 357 (FNMADD_H_INX FPR16INX:$rs1, FPR16INX:$rs2, FPR16INX:$rs3, FRM_DYN)>; 358 359// fnmadd: -(rs1 * rs2 + rs3) (the nsz flag on the FMA) 360def : Pat<(fneg (any_fma_nsz FPR16INX:$rs1, FPR16INX:$rs2, FPR16INX:$rs3)), 361 (FNMADD_H_INX FPR16INX:$rs1, FPR16INX:$rs2, FPR16INX:$rs3, FRM_DYN)>; 362} // Predicates = [HasStdExtZhinx] 363 364// The ratified 20191213 ISA spec defines fmin and fmax in a way that matches 365// LLVM's fminnum and fmaxnum 366// <https://github.com/riscv/riscv-isa-manual/commit/cd20cee7efd9bac7c5aa127ec3b451749d2b3cce>. 367foreach Ext = ZfhExts in { 368 defm : PatFprFpr_m<fminnum, FMIN_H, Ext>; 369 defm : PatFprFpr_m<fmaxnum, FMAX_H, Ext>; 370 defm : PatFprFpr_m<fminimumnum, FMIN_H, Ext>; 371 defm : PatFprFpr_m<fmaximumnum, FMAX_H, Ext>; 372 defm : PatFprFpr_m<riscv_fmin, FMIN_H, Ext>; 373 defm : PatFprFpr_m<riscv_fmax, FMAX_H, Ext>; 374 def : Pat<(f16 (fcanonicalize FPR16:$rs1)), (FMIN_H $rs1, $rs1)>; 375} 376 377/// Setcc 378// FIXME: SETEQ/SETLT/SETLE imply nonans, can we pick better instructions for 379// strict versions of those. 380 381// Match non-signaling FEQ_D 382foreach Ext = ZfhExts in { 383 defm : PatSetCC_m<any_fsetcc, SETEQ, FEQ_H, Ext>; 384 defm : PatSetCC_m<any_fsetcc, SETOEQ, FEQ_H, Ext>; 385 defm : PatSetCC_m<strict_fsetcc, SETLT, PseudoQuietFLT_H, Ext>; 386 defm : PatSetCC_m<strict_fsetcc, SETOLT, PseudoQuietFLT_H, Ext>; 387 defm : PatSetCC_m<strict_fsetcc, SETLE, PseudoQuietFLE_H, Ext>; 388 defm : PatSetCC_m<strict_fsetcc, SETOLE, PseudoQuietFLE_H, Ext>; 389} 390 391let Predicates = [HasStdExtZfh] in { 392// Match signaling FEQ_H 393def : Pat<(XLenVT (strict_fsetccs (f16 FPR16:$rs1), FPR16:$rs2, SETEQ)), 394 (AND (XLenVT (FLE_H $rs1, $rs2)), 395 (XLenVT (FLE_H $rs2, $rs1)))>; 396def : Pat<(XLenVT (strict_fsetccs (f16 FPR16:$rs1), FPR16:$rs2, SETOEQ)), 397 (AND (XLenVT (FLE_H $rs1, $rs2)), 398 (XLenVT (FLE_H $rs2, $rs1)))>; 399// If both operands are the same, use a single FLE. 400def : Pat<(XLenVT (strict_fsetccs (f16 FPR16:$rs1), (f16 FPR16:$rs1), SETEQ)), 401 (FLE_H $rs1, $rs1)>; 402def : Pat<(XLenVT (strict_fsetccs (f16 FPR16:$rs1), (f16 FPR16:$rs1), SETOEQ)), 403 (FLE_H $rs1, $rs1)>; 404} // Predicates = [HasStdExtZfh] 405 406let Predicates = [HasStdExtZhinx] in { 407// Match signaling FEQ_H 408def : Pat<(XLenVT (strict_fsetccs FPR16INX:$rs1, FPR16INX:$rs2, SETEQ)), 409 (AND (XLenVT (FLE_H_INX $rs1, $rs2)), 410 (XLenVT (FLE_H_INX $rs2, $rs1)))>; 411def : Pat<(XLenVT (strict_fsetccs FPR16INX:$rs1, FPR16INX:$rs2, SETOEQ)), 412 (AND (XLenVT (FLE_H_INX $rs1, $rs2)), 413 (XLenVT (FLE_H_INX $rs2, $rs1)))>; 414// If both operands are the same, use a single FLE. 415def : Pat<(XLenVT (strict_fsetccs FPR16INX:$rs1, FPR16INX:$rs1, SETEQ)), 416 (FLE_H_INX $rs1, $rs1)>; 417def : Pat<(XLenVT (strict_fsetccs FPR16INX:$rs1, FPR16INX:$rs1, SETOEQ)), 418 (FLE_H_INX $rs1, $rs1)>; 419} // Predicates = [HasStdExtZhinx] 420 421foreach Ext = ZfhExts in { 422 defm : PatSetCC_m<any_fsetccs, SETLT, FLT_H, Ext>; 423 defm : PatSetCC_m<any_fsetccs, SETOLT, FLT_H, Ext>; 424 defm : PatSetCC_m<any_fsetccs, SETLE, FLE_H, Ext>; 425 defm : PatSetCC_m<any_fsetccs, SETOLE, FLE_H, Ext>; 426} 427 428let Predicates = [HasStdExtZfh] in { 429def PseudoFROUND_H : PseudoFROUND<FPR16, f16>; 430} // Predicates = [HasStdExtZfh] 431 432let Predicates = [HasStdExtZhinx] in { 433def PseudoFROUND_H_INX : PseudoFROUND<FPR16INX, f16>; 434} // Predicates = [HasStdExtZhinx] 435 436let Predicates = [HasStdExtZfhmin] in { 437defm Select_FPR16 : SelectCC_GPR_rrirr<FPR16, f16>; 438 439/// Loads 440def : LdPat<load, FLH, f16>; 441 442/// Stores 443def : StPat<store, FSH, FPR16, f16>; 444} // Predicates = [HasStdExtZfhmin] 445 446let Predicates = [HasStdExtZhinxmin] in { 447defm Select_FPR16INX : SelectCC_GPR_rrirr<FPR16INX, f16>; 448 449/// Loads 450def : LdPat<load, LH_INX, f16>; 451 452/// Stores 453def : StPat<store, SH_INX, GPRF16, f16>; 454} // Predicates = [HasStdExtZhinxmin] 455 456let Predicates = [HasStdExtZfhmin] in { 457/// Float conversion operations 458 459// f32 -> f16, f16 -> f32 460def : Pat<(f16 (any_fpround FPR32:$rs1)), (FCVT_H_S FPR32:$rs1, FRM_DYN)>; 461def : Pat<(any_fpextend (f16 FPR16:$rs1)), (FCVT_S_H FPR16:$rs1, FRM_RNE)>; 462 463// Moves (no conversion) 464def : Pat<(f16 (riscv_fmv_h_x GPR:$src)), (FMV_H_X GPR:$src)>; 465def : Pat<(riscv_fmv_x_anyexth (f16 FPR16:$src)), (FMV_X_H FPR16:$src)>; 466def : Pat<(riscv_fmv_x_signexth (f16 FPR16:$src)), (FMV_X_H FPR16:$src)>; 467 468def : Pat<(fcopysign FPR32:$rs1, (f16 FPR16:$rs2)), (FSGNJ_S $rs1, (FCVT_S_H $rs2, FRM_RNE))>; 469} // Predicates = [HasStdExtZfhmin] 470 471let Predicates = [HasStdExtZhinxmin] in { 472/// Float conversion operations 473 474// f32 -> f16, f16 -> f32 475def : Pat<(any_fpround FPR32INX:$rs1), (FCVT_H_S_INX FPR32INX:$rs1, FRM_DYN)>; 476def : Pat<(any_fpextend FPR16INX:$rs1), (FCVT_S_H_INX FPR16INX:$rs1, FRM_RNE)>; 477 478// Moves (no conversion) 479def : Pat<(f16 (riscv_fmv_h_x GPR:$src)), (EXTRACT_SUBREG GPR:$src, sub_16)>; 480def : Pat<(riscv_fmv_x_anyexth FPR16INX:$src), (INSERT_SUBREG (XLenVT (IMPLICIT_DEF)), FPR16INX:$src, sub_16)>; 481 482def : Pat<(fcopysign FPR32INX:$rs1, FPR16INX:$rs2), (FSGNJ_S_INX $rs1, (FCVT_S_H_INX $rs2, FRM_RNE))>; 483} // Predicates = [HasStdExtZhinxmin] 484 485let Predicates = [HasStdExtZfh, IsRV32] in { 486// half->[u]int. Round-to-zero must be used. 487def : Pat<(i32 (any_fp_to_sint (f16 FPR16:$rs1))), (FCVT_W_H $rs1, 0b001)>; 488def : Pat<(i32 (any_fp_to_uint (f16 FPR16:$rs1))), (FCVT_WU_H $rs1, 0b001)>; 489 490// Saturating half->[u]int32. 491def : Pat<(i32 (riscv_fcvt_x (f16 FPR16:$rs1), timm:$frm)), (FCVT_W_H $rs1, timm:$frm)>; 492def : Pat<(i32 (riscv_fcvt_xu (f16 FPR16:$rs1), timm:$frm)), (FCVT_WU_H $rs1, timm:$frm)>; 493 494// half->int32 with current rounding mode. 495def : Pat<(i32 (any_lrint (f16 FPR16:$rs1))), (FCVT_W_H $rs1, FRM_DYN)>; 496 497// half->int32 rounded to nearest with ties rounded away from zero. 498def : Pat<(i32 (any_lround (f16 FPR16:$rs1))), (FCVT_W_H $rs1, FRM_RMM)>; 499 500// [u]int->half. Match GCC and default to using dynamic rounding mode. 501def : Pat<(f16 (any_sint_to_fp (i32 GPR:$rs1))), (FCVT_H_W $rs1, FRM_DYN)>; 502def : Pat<(f16 (any_uint_to_fp (i32 GPR:$rs1))), (FCVT_H_WU $rs1, FRM_DYN)>; 503} // Predicates = [HasStdExtZfh] 504 505let Predicates = [HasStdExtZhinx, IsRV32] in { 506// half->[u]int. Round-to-zero must be used. 507def : Pat<(i32 (any_fp_to_sint FPR16INX:$rs1)), (FCVT_W_H_INX $rs1, 0b001)>; 508def : Pat<(i32 (any_fp_to_uint FPR16INX:$rs1)), (FCVT_WU_H_INX $rs1, 0b001)>; 509 510// Saturating float->[u]int32. 511def : Pat<(i32 (riscv_fcvt_x FPR16INX:$rs1, timm:$frm)), (FCVT_W_H_INX $rs1, timm:$frm)>; 512def : Pat<(i32 (riscv_fcvt_xu FPR16INX:$rs1, timm:$frm)), (FCVT_WU_H_INX $rs1, timm:$frm)>; 513 514// half->int32 with current rounding mode. 515def : Pat<(i32 (any_lrint FPR16INX:$rs1)), (FCVT_W_H_INX $rs1, FRM_DYN)>; 516 517// half->int32 rounded to nearest with ties rounded away from zero. 518def : Pat<(i32 (any_lround FPR16INX:$rs1)), (FCVT_W_H_INX $rs1, FRM_RMM)>; 519 520// [u]int->half. Match GCC and default to using dynamic rounding mode. 521def : Pat<(any_sint_to_fp (i32 GPR:$rs1)), (FCVT_H_W_INX $rs1, FRM_DYN)>; 522def : Pat<(any_uint_to_fp (i32 GPR:$rs1)), (FCVT_H_WU_INX $rs1, FRM_DYN)>; 523} // Predicates = [HasStdExtZhinx, IsRV32] 524 525let Predicates = [HasStdExtZfh, IsRV64] in { 526// Use target specific isd nodes to help us remember the result is sign 527// extended. Matching sext_inreg+fptoui/fptosi may cause the conversion to be 528// duplicated if it has another user that didn't need the sign_extend. 529def : Pat<(riscv_any_fcvt_w_rv64 (f16 FPR16:$rs1), timm:$frm), (FCVT_W_H $rs1, timm:$frm)>; 530def : Pat<(riscv_any_fcvt_wu_rv64 (f16 FPR16:$rs1), timm:$frm), (FCVT_WU_H $rs1, timm:$frm)>; 531 532// half->[u]int64. Round-to-zero must be used. 533def : Pat<(i64 (any_fp_to_sint (f16 FPR16:$rs1))), (FCVT_L_H $rs1, 0b001)>; 534def : Pat<(i64 (any_fp_to_uint (f16 FPR16:$rs1))), (FCVT_LU_H $rs1, 0b001)>; 535 536// Saturating half->[u]int64. 537def : Pat<(i64 (riscv_fcvt_x (f16 FPR16:$rs1), timm:$frm)), (FCVT_L_H $rs1, timm:$frm)>; 538def : Pat<(i64 (riscv_fcvt_xu (f16 FPR16:$rs1), timm:$frm)), (FCVT_LU_H $rs1, timm:$frm)>; 539 540// half->int64 with current rounding mode. 541def : Pat<(i64 (any_lrint (f16 FPR16:$rs1))), (FCVT_L_H $rs1, FRM_DYN)>; 542def : Pat<(i64 (any_llrint (f16 FPR16:$rs1))), (FCVT_L_H $rs1, FRM_DYN)>; 543 544// half->int64 rounded to nearest with ties rounded away from zero. 545def : Pat<(i64 (any_lround (f16 FPR16:$rs1))), (FCVT_L_H $rs1, FRM_RMM)>; 546def : Pat<(i64 (any_llround (f16 FPR16:$rs1))), (FCVT_L_H $rs1, FRM_RMM)>; 547 548// [u]int->fp. Match GCC and default to using dynamic rounding mode. 549def : Pat<(f16 (any_sint_to_fp (i64 (sexti32 (i64 GPR:$rs1))))), (FCVT_H_W $rs1, FRM_DYN)>; 550def : Pat<(f16 (any_uint_to_fp (i64 (zexti32 (i64 GPR:$rs1))))), (FCVT_H_WU $rs1, FRM_DYN)>; 551def : Pat<(f16 (any_sint_to_fp (i64 GPR:$rs1))), (FCVT_H_L $rs1, FRM_DYN)>; 552def : Pat<(f16 (any_uint_to_fp (i64 GPR:$rs1))), (FCVT_H_LU $rs1, FRM_DYN)>; 553} // Predicates = [HasStdExtZfh, IsRV64] 554 555let Predicates = [HasStdExtZhinx, IsRV64] in { 556// Use target specific isd nodes to help us remember the result is sign 557// extended. Matching sext_inreg+fptoui/fptosi may cause the conversion to be 558// duplicated if it has another user that didn't need the sign_extend. 559def : Pat<(riscv_any_fcvt_w_rv64 FPR16INX:$rs1, timm:$frm), (FCVT_W_H_INX $rs1, timm:$frm)>; 560def : Pat<(riscv_any_fcvt_wu_rv64 FPR16INX:$rs1, timm:$frm), (FCVT_WU_H_INX $rs1, timm:$frm)>; 561 562// half->[u]int64. Round-to-zero must be used. 563def : Pat<(i64 (any_fp_to_sint FPR16INX:$rs1)), (FCVT_L_H_INX $rs1, 0b001)>; 564def : Pat<(i64 (any_fp_to_uint FPR16INX:$rs1)), (FCVT_LU_H_INX $rs1, 0b001)>; 565 566// Saturating float->[u]int64. 567def : Pat<(i64 (riscv_fcvt_x FPR16INX:$rs1, timm:$frm)), (FCVT_L_H_INX $rs1, timm:$frm)>; 568def : Pat<(i64 (riscv_fcvt_xu FPR16INX:$rs1, timm:$frm)), (FCVT_LU_H_INX $rs1, timm:$frm)>; 569 570// half->int64 with current rounding mode. 571def : Pat<(i64 (any_lrint FPR16INX:$rs1)), (FCVT_L_H_INX $rs1, FRM_DYN)>; 572def : Pat<(i64 (any_llrint FPR16INX:$rs1)), (FCVT_L_H_INX $rs1, FRM_DYN)>; 573 574// half->int64 rounded to nearest with ties rounded away from zero. 575def : Pat<(i64 (any_lround FPR16INX:$rs1)), (FCVT_L_H_INX $rs1, FRM_RMM)>; 576def : Pat<(i64 (any_llround FPR16INX:$rs1)), (FCVT_L_H_INX $rs1, FRM_RMM)>; 577 578// [u]int->fp. Match GCC and default to using dynamic rounding mode. 579def : Pat<(any_sint_to_fp (i64 (sexti32 (i64 GPR:$rs1)))), (FCVT_H_W_INX $rs1, FRM_DYN)>; 580def : Pat<(any_uint_to_fp (i64 (zexti32 (i64 GPR:$rs1)))), (FCVT_H_WU_INX $rs1, FRM_DYN)>; 581def : Pat<(any_sint_to_fp (i64 GPR:$rs1)), (FCVT_H_L_INX $rs1, FRM_DYN)>; 582def : Pat<(any_uint_to_fp (i64 GPR:$rs1)), (FCVT_H_LU_INX $rs1, FRM_DYN)>; 583} // Predicates = [HasStdExtZhinx, IsRV64] 584 585let Predicates = [HasStdExtZfhmin, HasStdExtD] in { 586/// Float conversion operations 587// f64 -> f16, f16 -> f64 588def : Pat<(f16 (any_fpround FPR64:$rs1)), (FCVT_H_D FPR64:$rs1, FRM_DYN)>; 589def : Pat<(any_fpextend (f16 FPR16:$rs1)), (FCVT_D_H FPR16:$rs1, FRM_RNE)>; 590 591/// Float arithmetic operations 592def : Pat<(f16 (fcopysign FPR16:$rs1, FPR64:$rs2)), 593 (FSGNJ_H $rs1, (f16 (FCVT_H_D $rs2, FRM_DYN)))>; 594def : Pat<(fcopysign FPR64:$rs1, (f16 FPR16:$rs2)), (FSGNJ_D $rs1, (FCVT_D_H $rs2, FRM_RNE))>; 595} // Predicates = [HasStdExtZfhmin, HasStdExtD] 596 597let Predicates = [HasStdExtZhinxmin, HasStdExtZdinx, IsRV32] in { 598/// Float conversion operations 599// f64 -> f16, f16 -> f64 600def : Pat<(any_fpround FPR64IN32X:$rs1), (FCVT_H_D_IN32X FPR64IN32X:$rs1, FRM_DYN)>; 601def : Pat<(any_fpextend FPR16INX:$rs1), (FCVT_D_H_IN32X FPR16INX:$rs1, FRM_RNE)>; 602 603/// Float arithmetic operations 604def : Pat<(fcopysign FPR16INX:$rs1, FPR64IN32X:$rs2), 605 (FSGNJ_H_INX $rs1, (FCVT_H_D_IN32X $rs2, 0b111))>; 606def : Pat<(fcopysign FPR64IN32X:$rs1, FPR16INX:$rs2), (FSGNJ_D_IN32X $rs1, (FCVT_D_H_IN32X $rs2, FRM_RNE))>; 607} // Predicates = [HasStdExtZhinxmin, HasStdExtZdinx, IsRV32] 608 609let Predicates = [HasStdExtZhinxmin, HasStdExtZdinx, IsRV64] in { 610/// Float conversion operations 611// f64 -> f16, f16 -> f64 612def : Pat<(any_fpround FPR64INX:$rs1), (FCVT_H_D_INX FPR64INX:$rs1, FRM_DYN)>; 613def : Pat<(any_fpextend FPR16INX:$rs1), (FCVT_D_H_INX FPR16INX:$rs1, FRM_RNE)>; 614 615/// Float arithmetic operations 616def : Pat<(fcopysign FPR16INX:$rs1, FPR64INX:$rs2), 617 (FSGNJ_H_INX $rs1, (FCVT_H_D_INX $rs2, 0b111))>; 618def : Pat<(fcopysign FPR64INX:$rs1, FPR16INX:$rs2), (FSGNJ_D_INX $rs1, (f64 (FCVT_D_H_INX $rs2, FRM_RNE)))>; 619} // Predicates = [HasStdExtZhinxmin, HasStdExtZdinx, IsRV64] 620