1//===---------------- RISCVInstrInfoXQci.td ----------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the vendor extensions defined by QUALCOMM. 10// 11//===----------------------------------------------------------------------===// 12 13//===----------------------------------------------------------------------===// 14// Operand and SDNode transformation definitions. 15//===----------------------------------------------------------------------===// 16 17def uimm5nonzero : RISCVOp<XLenVT>, 18 ImmLeaf<XLenVT, [{return (Imm != 0) && isUInt<5>(Imm);}]> { 19 let ParserMatchClass = UImmAsmOperand<5, "NonZero">; 20 let DecoderMethod = "decodeUImmNonZeroOperand<5>"; 21 let OperandType = "OPERAND_UIMM5_NONZERO"; 22} 23 24def uimm5gt3 : RISCVOp<XLenVT>, ImmLeaf<XLenVT, 25 [{return (Imm > 3) && isUInt<5>(Imm);}]> { 26 let ParserMatchClass = UImmAsmOperand<5, "GT3">; 27 let DecoderMethod = "decodeUImmOperand<5>"; 28 let OperandType = "OPERAND_UIMM5_GT3"; 29} 30 31def uimm10 : RISCVUImmLeafOp<10>; 32 33def uimm11 : RISCVUImmLeafOp<11>; 34 35def simm26 : RISCVSImmLeafOp<26>; 36 37//===----------------------------------------------------------------------===// 38// Instruction Formats 39//===----------------------------------------------------------------------===// 40 41//===----------------------------------------------------------------------===// 42// Instruction Class Templates 43//===----------------------------------------------------------------------===// 44 45let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in { 46class QCILoad_ScaleIdx<bits<4> funct4, string opcodestr> 47 : RVInstRBase<0b111, OPC_CUSTOM_0, 48 (outs GPR:$rd), (ins GPRMem:$rs1, GPRNoX0:$rs2, uimm3:$shamt), 49 opcodestr, "$rd, $rs1, $rs2, $shamt"> { 50 bits<3> shamt; 51 let Inst{31-28} = funct4; 52 let Inst{27-25} = shamt; 53} 54} 55 56let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in { 57// rd corresponds to the source for the store 'rs3' described in the spec. 58class QCIStore_ScaleIdx<bits<4> funct4, string opcodestr> 59 : RVInstRBase<0b110, OPC_CUSTOM_1, (outs), 60 (ins GPR:$rd, GPRMem:$rs1, GPRNoX0:$rs2, uimm3:$shamt), 61 opcodestr, "$rd, $rs1, $rs2, $shamt"> { 62 bits<3> shamt; 63 let Inst{31-28} = funct4; 64 let Inst{27-25} = shamt; 65} 66} 67 68class QCIRVInstR<bits<4> funct4, string opcodestr> 69 : RVInstR<{0b000, funct4}, 0b011, OPC_CUSTOM_0, (outs GPRNoX0:$rd), 70 (ins GPRNoX0:$rs1), opcodestr, "$rd, $rs1"> { 71 let rs2 = 0; 72} 73 74class QCIRVInstRR<bits<5> funct5, DAGOperand InTyRs1, string opcodestr> 75 : RVInstR<{0b00, funct5}, 0b011, OPC_CUSTOM_0, (outs GPRNoX0:$rd), 76 (ins InTyRs1:$rs1, GPRNoX0:$rs2), opcodestr, "$rd, $rs1, $rs2">; 77 78let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 79class QCISELECTIICC<bits<3> funct3, string opcodestr> 80 : RVInstR4<0b00, funct3, OPC_CUSTOM_2, (outs GPRNoX0:$rd_wb), 81 (ins GPRNoX0:$rd, GPRNoX0:$rs1, simm5:$simm1, simm5:$simm2), 82 opcodestr, "$rd, $rs1, $simm1, $simm2"> { 83 let Constraints = "$rd = $rd_wb"; 84 bits<5> simm1; 85 bits<5> simm2; 86 87 let rs3 = simm2; 88 let rs2 = simm1; 89} 90 91let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 92class QCISELECTICC<bits<3> funct3, string opcodestr> 93 : RVInstR4<0b01, funct3, OPC_CUSTOM_2, (outs GPRNoX0:$rd_wb), 94 (ins GPRNoX0:$rd, GPRNoX0:$rs1, GPRNoX0:$rs2, simm5:$simm2), 95 opcodestr, "$rd, $rs1, $rs2, $simm2"> { 96 let Constraints = "$rd = $rd_wb"; 97 bits<5> simm2; 98 99 let rs3 = simm2; 100} 101 102let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 103class QCISELECTCCI<bits<3> funct3, string opcodestr> 104 : RVInstR4<0b10, funct3, OPC_CUSTOM_2, (outs GPRNoX0:$rd_wb), 105 (ins GPRNoX0:$rd, simm5:$imm, GPRNoX0:$rs2, GPRNoX0:$rs3), 106 opcodestr, "$rd, $imm, $rs2, $rs3"> { 107 let Constraints = "$rd = $rd_wb"; 108 bits<5> imm; 109 110 let rs1 = imm; 111} 112 113let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 114class QCISELECTICCI<bits<3> funct3, string opcodestr> 115 : RVInstR4<0b11, funct3, OPC_CUSTOM_2, (outs GPRNoX0:$rd_wb), 116 (ins GPRNoX0:$rd, simm5:$imm, GPRNoX0:$rs2, simm5:$simm2), 117 opcodestr, "$rd, $imm, $rs2, $simm2"> { 118 let Constraints = "$rd = $rd_wb"; 119 bits<5> imm; 120 bits<5> simm2; 121 122 let rs3 = simm2; 123 let rs1 = imm; 124} 125 126let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in 127class QCILoadMultiple<bits<2> funct2, DAGOperand InTyRs2, string opcodestr> 128 : RVInstRBase<0b111, OPC_CUSTOM_0, (outs GPRNoX0:$rd), 129 (ins GPR:$rs1, InTyRs2:$rs2, uimm7_lsb00:$imm), 130 opcodestr, "$rd, $rs2, ${imm}(${rs1})"> { 131 bits<7> imm; 132 let Inst{31-25} = {funct2, imm{6-2}}; 133} 134 135 136// rd corresponds to the source for the store 'rs3' described in the spec. 137let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in 138class QCIStoreMultiple<bits<2> funct2, DAGOperand InTyRs2, string opcodestr> 139 : RVInstRBase<0b111, OPC_CUSTOM_1, (outs), 140 (ins GPR:$rd, GPR:$rs1, InTyRs2:$rs2, uimm7_lsb00:$imm), 141 opcodestr, "$rd, $rs2, ${imm}(${rs1})"> { 142 bits<7> imm; 143 let Inst{31-25} = {funct2, imm{6-2}}; 144} 145 146let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 147class QCILICC<bits<3> funct3, bits<2> funct2, DAGOperand InTyRs2, string opcodestr> 148 : RVInstRBase<funct3, OPC_CUSTOM_2, (outs GPRNoX0:$rd_wb), 149 (ins GPRNoX0:$rd, GPRNoX0:$rs1, InTyRs2:$rs2, simm5:$simm), 150 opcodestr, "$rd, $rs1, $rs2, $simm"> { 151 let Constraints = "$rd = $rd_wb"; 152 bits<5> simm; 153 154 let Inst{31-25} = {simm, funct2}; 155} 156 157let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 158class QCIMVCC<bits<3> funct3, string opcodestr> 159 : RVInstR4<0b00, funct3, OPC_CUSTOM_2, (outs GPRNoX0:$rd), 160 (ins GPRNoX0:$rs1, GPRNoX0:$rs2, GPRNoX0:$rs3), 161 opcodestr, "$rd, $rs1, $rs2, $rs3">; 162 163let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 164class QCIMVCCI<bits<3> funct3, string opcodestr, DAGOperand immType> 165 : RVInstR4<0b10, funct3, OPC_CUSTOM_2, (outs GPRNoX0:$rd), 166 (ins GPRNoX0:$rs1, immType:$imm, GPRNoX0:$rs3), 167 opcodestr, "$rd, $rs1, $imm, $rs3"> { 168 bits<5> imm; 169 170 let rs2 = imm; 171} 172 173let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in 174class QCIRVInst16CI_RS1<bits<5> funct5, string OpcodeStr> 175 : RVInst16CI<0b000, 0b10, (outs), (ins GPRNoX0:$rs1), OpcodeStr, "$rs1"> { 176 bits<5> rs1; 177 178 let Inst{12} = 0b1; 179 let Inst{11-7} = rs1; 180 let Inst{6-2} = funct5{4-0}; 181} 182 183let hasSideEffects = 1 in 184class QCIRVInst16CI_NONE<bits<5> funct5, string OpcodeStr> 185 : RVInst16CI<0b000, 0b10, (outs), (ins), OpcodeStr, ""> { 186 let Inst{12} = 0b1; 187 let Inst{11-7} = funct5; 188 let Inst{6-2} = 0b00100; 189} 190 191let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in 192class QCIInt_IMM<bits<1> funct1, string opcodestr> 193 : RVInstIBase<0b000, OPC_SYSTEM, (outs), (ins uimm10:$imm10), opcodestr, 194 "$imm10"> { 195 bits<10> imm10; 196 197 let rd = 0; 198 let rs1 = imm10{4-0}; 199 let Inst{31-25} = {0b110011, funct1}; 200 let Inst{24-20} = imm10{9-5}; 201} 202 203class QCIRVInstEIBase<bits<3> funct3, bits<2> funct2, dag outs, 204 dag ins, string opcodestr, string argstr> 205 : RVInst48<outs, ins, opcodestr, argstr, [], InstFormatOther> { 206 bits<5> rd; 207 bits<5> rs1; 208 bits<26> imm; 209 210 let Inst{47-32} = imm{25-10}; 211 let Inst{31-30} = funct2; 212 let Inst{29-20} = imm{9-0}; 213 let Inst{19-15} = rs1; 214 let Inst{14-12} = funct3; 215 let Inst{11-7} = rd; 216 let Inst{6-0} = 0b0011111; 217} 218 219let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in 220class QCIRVInstEILoad<bits<3> funct3, bits<2> funct2, string opcodestr> 221 : QCIRVInstEIBase<funct3, funct2, (outs GPR:$rd), 222 (ins GPRMem:$rs1, simm26:$imm), opcodestr, 223 "$rd, ${imm}(${rs1})">; 224 225class QCIRVInstESBase<bits<3> funct3, bits<2> funct2, dag outs, 226 dag ins, string opcodestr, string argstr> 227 : RVInst48<outs, ins, opcodestr, argstr, [], InstFormatOther> { 228 bits<5> rs1; 229 bits<5> rs2; 230 bits<26> imm; 231 232 let Inst{47-32} = imm{25-10}; 233 let Inst{31-30} = funct2; 234 let Inst{29-25} = imm{9-5}; 235 let Inst{24-20} = rs2; 236 let Inst{19-15} = rs1; 237 let Inst{14-12} = funct3; 238 let Inst{11-7} = imm{4-0}; 239 let Inst{6-0} = 0b0011111; 240} 241 242let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in 243class QCIRVInstESStore<bits<3> funct3, bits<2> funct2, string opcodestr> 244 : QCIRVInstESBase<funct3, funct2, (outs), 245 (ins GPRMem:$rs2, GPR:$rs1, simm26:$imm), 246 opcodestr, "$rs2, ${imm}(${rs1})">; 247 248//===----------------------------------------------------------------------===// 249// Instructions 250//===----------------------------------------------------------------------===// 251 252let Predicates = [HasVendorXqcicsr, IsRV32], DecoderNamespace = "Xqcicsr" in { 253let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in { 254 def QC_CSRRWR : RVInstR<0b1000110, 0b000, OPC_SYSTEM, (outs GPR:$rd), 255 (ins GPR:$rs1, GPRNoX0:$rs2), "qc.csrrwr", 256 "$rd, $rs1, $rs2">; 257 258 def QC_CSRRWRI : RVInstR<0b1000111, 0b000, OPC_SYSTEM, (outs GPR:$rd), 259 (ins uimm5:$rs1, GPRNoX0:$rs2), "qc.csrrwri", 260 "$rd, $rs1, $rs2">; 261} // hasSideEffects = 1, mayLoad = 0, mayStore = 0 262} // Predicates = [HasVendorXqcicsr, IsRV32], DecoderNamespace = "Xqcicsr" 263 264let Predicates = [HasVendorXqcisls, IsRV32], DecoderNamespace = "Xqcisls" in { 265 def QC_LRB : QCILoad_ScaleIdx<0b1000, "qc.lrb">; 266 def QC_LRH : QCILoad_ScaleIdx<0b1001, "qc.lrh">; 267 def QC_LRW : QCILoad_ScaleIdx<0b1010, "qc.lrw">; 268 def QC_LRBU : QCILoad_ScaleIdx<0b1011, "qc.lrbu">; 269 def QC_LRHU : QCILoad_ScaleIdx<0b1100, "qc.lrhu">; 270 271 def QC_SRB : QCIStore_ScaleIdx<0b1101, "qc.srb">; 272 def QC_SRH : QCIStore_ScaleIdx<0b1110, "qc.srh">; 273 def QC_SRW : QCIStore_ScaleIdx<0b1111, "qc.srw">; 274} // Predicates = [HasVendorXqcisls, IsRV32], DecoderNamespace = "Xqcisls" 275 276let Predicates = [HasVendorXqcia, IsRV32], DecoderNamespace = "Xqcia" in { 277let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { 278 def QC_SLASAT : QCIRVInstRR<0b01010, GPRNoX0, "qc.slasat">; 279 def QC_SLLSAT : QCIRVInstRR<0b01100, GPRNoX0, "qc.sllsat">; 280 def QC_ADDSAT : QCIRVInstRR<0b01110, GPRNoX0, "qc.addsat">; 281 def QC_ADDUSAT : QCIRVInstRR<0b01111, GPRNoX0, "qc.addusat">; 282 def QC_SUBSAT : QCIRVInstRR<0b10000, GPRNoX0, "qc.subsat">; 283 def QC_SUBUSAT : QCIRVInstRR<0b10001, GPRNoX0, "qc.subusat">; 284 285 def QC_WRAP : QCIRVInstRR<0b10010, GPR, "qc.wrap">; 286 def QC_WRAPI : RVInstI<0b000, OPC_CUSTOM_0, (outs GPRNoX0:$rd), 287 (ins GPRNoX0:$rs1, uimm11:$imm11), "qc.wrapi", 288 "$rd, $rs1, $imm11"> { 289 bits<11> imm11; 290 291 let imm12 = {0b0, imm11}; 292 } 293 294 def QC_NORM : QCIRVInstR<0b0111, "qc.norm">; 295 def QC_NORMU : QCIRVInstR<0b1000, "qc.normu">; 296 def QC_NORMEU : QCIRVInstR<0b1001, "qc.normeu">; 297} // hasSideEffects = 0, mayLoad = 0, mayStore = 0 298} // Predicates = [HasVendorXqcia, IsRV32], DecoderNamespace = "Xqcia" 299 300let Predicates = [HasVendorXqciac, IsRV32], DecoderNamespace = "Xqciac" in { 301let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { 302 def QC_C_MULIADD : RVInst16CL<0b001, 0b10, (outs GPRC:$rd_wb), 303 (ins GPRC:$rd, GPRC:$rs1, uimm5:$uimm), 304 "qc.c.muliadd", "$rd, $rs1, $uimm"> { 305 let Constraints = "$rd = $rd_wb"; 306 bits<5> uimm; 307 308 let Inst{12-10} = uimm{3-1}; 309 let Inst{6} = uimm{0}; 310 let Inst{5} = uimm{4}; 311 } 312 313 def QC_MULIADD : RVInstI<0b110, OPC_CUSTOM_0, (outs GPRNoX0:$rd_wb), 314 (ins GPRNoX0:$rd, GPRNoX0:$rs1, simm12:$imm12), 315 "qc.muliadd", "$rd, $rs1, $imm12"> { 316 let Constraints = "$rd = $rd_wb"; 317 } 318 319 def QC_SHLADD : RVInstRBase<0b011, OPC_CUSTOM_0, (outs GPRNoX0:$rd), 320 (ins GPRNoX0:$rs1, GPRNoX0:$rs2, uimm5gt3:$shamt), 321 "qc.shladd", "$rd, $rs1, $rs2, $shamt"> { 322 bits<5> shamt; 323 324 let Inst{31-30} = 0b01; 325 let Inst{29-25} = shamt; 326 } 327 328} // hasSideEffects = 0, mayLoad = 0, mayStore = 0 329} // Predicates = [HasVendorXqciac, IsRV32], DecoderNamespace = "Xqciac" 330 331let Predicates = [HasVendorXqcics, IsRV32], DecoderNamespace = "Xqcics" in { 332 def QC_SELECTIIEQ : QCISELECTIICC <0b010, "qc.selectiieq">; 333 def QC_SELECTIINE : QCISELECTIICC <0b011, "qc.selectiine">; 334 def QC_SELECTIEQ : QCISELECTICC <0b010, "qc.selectieq">; 335 def QC_SELECTINE : QCISELECTICC <0b011, "qc.selectine">; 336 def QC_SELECTEQI : QCISELECTCCI <0b010, "qc.selecteqi">; 337 def QC_SELECTNEI : QCISELECTCCI <0b011, "qc.selectnei">; 338 def QC_SELECTIEQI : QCISELECTICCI <0b010, "qc.selectieqi">; 339 def QC_SELECTINEI : QCISELECTICCI <0b011, "qc.selectinei">; 340} // Predicates = [HasVendorXqcics, IsRV32], DecoderNamespace = "Xqcics" 341 342let Predicates = [HasVendorXqcilsm, IsRV32], DecoderNamespace = "Xqcilsm" in { 343 def QC_SWM : QCIStoreMultiple<0b00, GPRNoX0, "qc.swm">; 344 def QC_SWMI : QCIStoreMultiple<0b01, uimm5nonzero, "qc.swmi">; 345 def QC_SETWM : QCIStoreMultiple<0b10, GPRNoX0, "qc.setwm">; 346 def QC_SETWMI : QCIStoreMultiple<0b11, uimm5nonzero, "qc.setwmi">; 347 348 def QC_LWM : QCILoadMultiple<0b00, GPRNoX0, "qc.lwm">; 349 def QC_LWMI : QCILoadMultiple<0b01, uimm5nonzero, "qc.lwmi">; 350} // Predicates = [HasVendorXqcilsm, IsRV32], DecoderNamespace = "Xqcilsm" 351 352let Predicates = [HasVendorXqcicli, IsRV32], DecoderNamespace = "Xqcicli" in { 353 def QC_LIEQ : QCILICC<0b000, 0b01, GPRNoX0, "qc.lieq">; 354 def QC_LINE : QCILICC<0b001, 0b01, GPRNoX0, "qc.line">; 355 def QC_LILT : QCILICC<0b100, 0b01, GPRNoX0, "qc.lilt">; 356 def QC_LIGE : QCILICC<0b101, 0b01, GPRNoX0, "qc.lige">; 357 def QC_LILTU : QCILICC<0b110, 0b01, GPRNoX0, "qc.liltu">; 358 def QC_LIGEU : QCILICC<0b111, 0b01, GPRNoX0, "qc.ligeu">; 359 360 def QC_LIEQI : QCILICC<0b000, 0b11, simm5, "qc.lieqi">; 361 def QC_LINEI : QCILICC<0b001, 0b11, simm5, "qc.linei">; 362 def QC_LILTI : QCILICC<0b100, 0b11, simm5, "qc.lilti">; 363 def QC_LIGEI : QCILICC<0b101, 0b11, simm5, "qc.ligei">; 364 def QC_LILTUI : QCILICC<0b110, 0b11, uimm5, "qc.liltui">; 365 def QC_LIGEUI : QCILICC<0b111, 0b11, uimm5, "qc.ligeui">; 366} // Predicates = [HasVendorXqcicli, IsRV32], DecoderNamespace = "Xqcicli" 367 368let Predicates = [HasVendorXqcicm, IsRV32], DecoderNamespace = "Xqcicm" in { 369let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 370 def QC_C_MVEQZ : RVInst16CL<0b101, 0b10, (outs GPRC:$rd_wb), 371 (ins GPRC:$rd, GPRC:$rs1), 372 "qc.c.mveqz", "$rd, $rs1"> { 373 let Constraints = "$rd = $rd_wb"; 374 375 let Inst{12-10} = 0b011; 376 let Inst{6-5} = 0b00; 377 } 378 379 def QC_MVEQ : QCIMVCC<0b000, "qc.mveq">; 380 def QC_MVNE : QCIMVCC<0b001, "qc.mvne">; 381 def QC_MVLT : QCIMVCC<0b100, "qc.mvlt">; 382 def QC_MVGE : QCIMVCC<0b101, "qc.mvge">; 383 def QC_MVLTU : QCIMVCC<0b110, "qc.mvltu">; 384 def QC_MVGEU : QCIMVCC<0b111, "qc.mvgeu">; 385 386 def QC_MVEQI : QCIMVCCI<0b000, "qc.mveqi", simm5>; 387 def QC_MVNEI : QCIMVCCI<0b001, "qc.mvnei", simm5>; 388 def QC_MVLTI : QCIMVCCI<0b100, "qc.mvlti", simm5>; 389 def QC_MVGEI : QCIMVCCI<0b101, "qc.mvgei", simm5>; 390 def QC_MVLTUI : QCIMVCCI<0b110, "qc.mvltui", uimm5>; 391 def QC_MVGEUI : QCIMVCCI<0b111, "qc.mvgeui", uimm5>; 392} // Predicates = [HasVendorXqcicm, IsRV32], DecoderNamespace = "Xqcicm" 393 394let Predicates = [HasVendorXqciint, IsRV32], DecoderNamespace = "Xqciint" in { 395 let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in 396 def QC_C_DIR : RVInst16CI<0b000, 0b10, (outs GPRNoX0:$rd), (ins), 397 "qc.c.dir", "$rd"> { 398 bits<5> rd; 399 400 let Inst{12} = 0b1; 401 let Inst{11-7} = rd; 402 let Inst{6-2} = 0b00000; 403 } 404 405 def QC_SETINTI : QCIInt_IMM<0b0, "qc.setinti">; 406 def QC_CLRINTI : QCIInt_IMM<0b1, "qc.clrinti">; 407 408 def QC_C_EIR : QCIRVInst16CI_RS1<0b00001, "qc.c.eir">; 409 def QC_C_SETINT : QCIRVInst16CI_RS1<0b00010, "qc.c.setint">; 410 def QC_C_CLRINT : QCIRVInst16CI_RS1<0b00011, "qc.c.clrint">; 411 412 let mayLoad = 0, mayStore = 0 in { 413 def QC_C_DI : QCIRVInst16CI_NONE<0b10110, "qc.c.di">; 414 def QC_C_EI : QCIRVInst16CI_NONE<0b10111, "qc.c.ei">; 415 } // mayLoad =0, mayStore = 0 416 417 let mayLoad = 1, mayStore = 1 in { 418 def QC_C_MIENTER : QCIRVInst16CI_NONE<0b10000, "qc.c.mienter">; 419 def QC_C_MIENTER_NEST : QCIRVInst16CI_NONE<0b10001, "qc.c.mienter.nest">; 420 } // mayLoad = 1, mayStore = 1 421 422 let mayLoad = 1, mayStore = 1, isReturn = 1, isTerminator = 1 in 423 def QC_C_MILEAVERET : QCIRVInst16CI_NONE<0b10100, "qc.c.mileaveret">; 424} // Predicates = [HasVendorXqciint, IsRV32], DecoderNamespace = "Xqciint" 425 426let Predicates = [HasVendorXqcilo, IsRV32], DecoderNamespace = "Xqcilo" in { 427 def QC_E_LB : QCIRVInstEILoad<0b101, 0b00, "qc.e.lb">; 428 def QC_E_LBU : QCIRVInstEILoad<0b101, 0b01, "qc.e.lbu">; 429 def QC_E_LH : QCIRVInstEILoad<0b101, 0b10, "qc.e.lh">; 430 def QC_E_LHU : QCIRVInstEILoad<0b101, 0b11, "qc.e.lhu">; 431 def QC_E_LW : QCIRVInstEILoad<0b110, 0b00, "qc.e.lw">; 432 433 def QC_E_SB : QCIRVInstESStore<0b110, 0b01, "qc.e.sb">; 434 def QC_E_SH : QCIRVInstESStore<0b110, 0b10, "qc.e.sh">; 435 def QC_E_SW : QCIRVInstESStore<0b110, 0b11, "qc.e.sw">; 436} // Predicates = [HasVendorXqcilo, IsRV32], DecoderNamespace = "Xqcilo" 437 438//===----------------------------------------------------------------------===// 439// Aliases 440//===----------------------------------------------------------------------===// 441 442let Predicates = [HasVendorXqcilsm, IsRV32] in { 443let EmitPriority = 0 in { 444 def : InstAlias<"qc.swm $rs3, $rs2, (${rs1})", 445 (QC_SWM GPR:$rs3, GPR:$rs1, GPRNoX0:$rs2, 0)>; 446 def : InstAlias<"qc.swmi $rs3, $length, (${rs1})", 447 (QC_SWMI GPR:$rs3, GPR:$rs1, uimm5nonzero:$length, 0)>; 448 def : InstAlias<"qc.setwm $rs3, $rs2, (${rs1})", 449 (QC_SETWM GPR:$rs3, GPR:$rs1, GPRNoX0:$rs2, 0)>; 450 def : InstAlias<"qc.setwmi $rs3, $length, (${rs1})", 451 (QC_SETWMI GPR:$rs3, GPR:$rs1, uimm5nonzero:$length, 0)>; 452 def : InstAlias<"qc.lwm $rd, $rs2, (${rs1})", 453 (QC_LWM GPRNoX0:$rd, GPR:$rs1, GPRNoX0:$rs2, 0)>; 454 def : InstAlias<"qc.lwmi $rd, $length, (${rs1})", 455 (QC_LWMI GPRNoX0:$rd, GPR:$rs1, uimm5nonzero:$length, 0)>; 456} // EmitPriority = 0 457} // Predicates = [HasVendorXqcilsm, IsRV32] 458 459let Predicates = [HasVendorXqcilo, IsRV32] in { 460let EmitPriority = 0 in { 461 def : InstAlias<"qc.e.lb $rd, (${rs1})", 462 (QC_E_LB GPR:$rd, GPR:$rs1, 0)>; 463 def : InstAlias<"qc.e.lbu $rd, (${rs1})", 464 (QC_E_LBU GPR:$rd, GPR:$rs1, 0)>; 465 def : InstAlias<"qc.e.lh $rd, (${rs1})", 466 (QC_E_LH GPR:$rd, GPR:$rs1, 0)>; 467 def : InstAlias<"qc.e.lhu $rd, (${rs1})", 468 (QC_E_LHU GPR:$rd, GPR:$rs1, 0)>; 469 def : InstAlias<"qc.e.lw $rd, (${rs1})", 470 (QC_E_LW GPR:$rd, GPR:$rs1, 0)>; 471 def : InstAlias<"qc.e.sb $rs2, (${rs1})", 472 (QC_E_SB GPR:$rs2, GPR:$rs1, 0)>; 473 def : InstAlias<"qc.e.sh $rs2, (${rs1})", 474 (QC_E_SH GPR:$rs2, GPR:$rs1, 0)>; 475 def : InstAlias<"qc.e.sw $rs2, (${rs1})", 476 (QC_E_SW GPR:$rs2, GPR:$rs1, 0)>; 477} // EmitPriority = 0 478} // Predicates = [HasVendorXqcilo, IsRV32] 479