1//===-- RISCVInstrInfoD.td - RISC-V 'D' instructions -------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the RISC-V instructions from the standard 'D', 10// Double-Precision Floating-Point instruction set extension. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// RISC-V specific DAG Nodes. 16//===----------------------------------------------------------------------===// 17 18def SDT_RISCVBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, 19 SDTCisVT<1, i32>, 20 SDTCisSameAs<1, 2>]>; 21def SDT_RISCVSplitF64 : SDTypeProfile<2, 1, [SDTCisVT<0, i32>, 22 SDTCisVT<1, i32>, 23 SDTCisVT<2, f64>]>; 24 25def RISCVBuildPairF64 : SDNode<"RISCVISD::BuildPairF64", SDT_RISCVBuildPairF64>; 26def : GINodeEquiv<G_MERGE_VALUES, RISCVBuildPairF64>; 27def RISCVSplitF64 : SDNode<"RISCVISD::SplitF64", SDT_RISCVSplitF64>; 28def : GINodeEquiv<G_UNMERGE_VALUES, RISCVSplitF64>; 29 30def AddrRegImmINX : ComplexPattern<iPTR, 2, "SelectAddrRegImmRV32Zdinx">; 31 32//===----------------------------------------------------------------------===// 33// Operand and SDNode transformation definitions. 34//===----------------------------------------------------------------------===// 35 36// Zdinx 37 38def GPRPairAsFPR : AsmOperandClass { 39 let Name = "GPRPairAsFPR"; 40 let ParserMethod = "parseGPRPairAsFPR64"; 41 let PredicateMethod = "isGPRPairAsFPR64"; 42 let RenderMethod = "addRegOperands"; 43} 44 45def GPRF64AsFPR : AsmOperandClass { 46 let Name = "GPRF64AsFPR"; 47 let PredicateMethod = "isGPRAsFPR"; 48 let ParserMethod = "parseGPRAsFPR64"; 49 let RenderMethod = "addRegOperands"; 50} 51 52def FPR64INX : RegisterOperand<GPR> { 53 let ParserMatchClass = GPRF64AsFPR; 54 let DecoderMethod = "DecodeGPRRegisterClass"; 55} 56 57def FPR64IN32X : RegisterOperand<GPRPair> { 58 let ParserMatchClass = GPRPairAsFPR; 59} 60 61def DExt : ExtInfo<"", "", [HasStdExtD], f64, FPR64, FPR32, FPR64, ?>; 62 63def ZdinxExt : ExtInfo<"_INX", "RVZfinx", [HasStdExtZdinx, IsRV64], 64 f64, FPR64INX, FPR32INX, FPR64INX, ?>; 65def Zdinx32Ext : ExtInfo<"_IN32X", "RV32Zdinx", [HasStdExtZdinx, IsRV32], 66 f64, FPR64IN32X, FPR32INX, FPR64IN32X, ?>; 67 68defvar DExts = [DExt, ZdinxExt, Zdinx32Ext]; 69defvar DExtsRV64 = [DExt, ZdinxExt]; 70 71//===----------------------------------------------------------------------===// 72// Instructions 73//===----------------------------------------------------------------------===// 74 75let Predicates = [HasStdExtD] in { 76def FLD : FPLoad_r<0b011, "fld", FPR64, WriteFLD64>; 77 78// Operands for stores are in the order srcreg, base, offset rather than 79// reflecting the order these fields are specified in the instruction 80// encoding. 81def FSD : FPStore_r<0b011, "fsd", FPR64, WriteFST64>; 82} // Predicates = [HasStdExtD] 83 84foreach Ext = DExts in { 85 let SchedRW = [WriteFMA64, ReadFMA64, ReadFMA64, ReadFMA64Addend] in { 86 defm FMADD_D : FPFMA_rrr_frm_m<OPC_MADD, 0b01, "fmadd.d", Ext>; 87 defm FMSUB_D : FPFMA_rrr_frm_m<OPC_MSUB, 0b01, "fmsub.d", Ext>; 88 defm FNMSUB_D : FPFMA_rrr_frm_m<OPC_NMSUB, 0b01, "fnmsub.d", Ext>; 89 defm FNMADD_D : FPFMA_rrr_frm_m<OPC_NMADD, 0b01, "fnmadd.d", Ext>; 90 } 91 92 let SchedRW = [WriteFAdd64, ReadFAdd64, ReadFAdd64] in { 93 defm FADD_D : FPALU_rr_frm_m<0b0000001, "fadd.d", Ext, Commutable=1>; 94 defm FSUB_D : FPALU_rr_frm_m<0b0000101, "fsub.d", Ext>; 95 } 96 let SchedRW = [WriteFMul64, ReadFMul64, ReadFMul64] in 97 defm FMUL_D : FPALU_rr_frm_m<0b0001001, "fmul.d", Ext, Commutable=1>; 98 99 let SchedRW = [WriteFDiv64, ReadFDiv64, ReadFDiv64] in 100 defm FDIV_D : FPALU_rr_frm_m<0b0001101, "fdiv.d", Ext>; 101 102 defm FSQRT_D : FPUnaryOp_r_frm_m<0b0101101, 0b00000, Ext, Ext.PrimaryTy, 103 Ext.PrimaryTy, "fsqrt.d">, 104 Sched<[WriteFSqrt64, ReadFSqrt64]>; 105 106 let SchedRW = [WriteFSGNJ64, ReadFSGNJ64, ReadFSGNJ64], 107 mayRaiseFPException = 0 in { 108 defm FSGNJ_D : FPALU_rr_m<0b0010001, 0b000, "fsgnj.d", Ext>; 109 defm FSGNJN_D : FPALU_rr_m<0b0010001, 0b001, "fsgnjn.d", Ext>; 110 defm FSGNJX_D : FPALU_rr_m<0b0010001, 0b010, "fsgnjx.d", Ext>; 111 } 112 113 let SchedRW = [WriteFMinMax64, ReadFMinMax64, ReadFMinMax64] in { 114 defm FMIN_D : FPALU_rr_m<0b0010101, 0b000, "fmin.d", Ext, Commutable=1>; 115 defm FMAX_D : FPALU_rr_m<0b0010101, 0b001, "fmax.d", Ext, Commutable=1>; 116 } 117 118 defm FCVT_S_D : FPUnaryOp_r_frm_m<0b0100000, 0b00001, Ext, Ext.F32Ty, 119 Ext.PrimaryTy, "fcvt.s.d">, 120 Sched<[WriteFCvtF64ToF32, ReadFCvtF64ToF32]>; 121 122 defm FCVT_D_S : FPUnaryOp_r_frmlegacy_m<0b0100001, 0b00000, Ext, Ext.PrimaryTy, 123 Ext.F32Ty, "fcvt.d.s">, 124 Sched<[WriteFCvtF32ToF64, ReadFCvtF32ToF64]>; 125 126 let SchedRW = [WriteFCmp64, ReadFCmp64, ReadFCmp64] in { 127 defm FEQ_D : FPCmp_rr_m<0b1010001, 0b010, "feq.d", Ext, Commutable=1>; 128 defm FLT_D : FPCmp_rr_m<0b1010001, 0b001, "flt.d", Ext>; 129 defm FLE_D : FPCmp_rr_m<0b1010001, 0b000, "fle.d", Ext>; 130 } 131 132 let mayRaiseFPException = 0 in 133 defm FCLASS_D : FPUnaryOp_r_m<0b1110001, 0b00000, 0b001, Ext, GPR, Ext.PrimaryTy, 134 "fclass.d">, 135 Sched<[WriteFClass64, ReadFClass64]>; 136 137 let IsSignExtendingOpW = 1 in 138 defm FCVT_W_D : FPUnaryOp_r_frm_m<0b1100001, 0b00000, Ext, GPR, Ext.PrimaryTy, 139 "fcvt.w.d">, 140 Sched<[WriteFCvtF64ToI32, ReadFCvtF64ToI32]>; 141 142 let IsSignExtendingOpW = 1 in 143 defm FCVT_WU_D : FPUnaryOp_r_frm_m<0b1100001, 0b00001, Ext, GPR, Ext.PrimaryTy, 144 "fcvt.wu.d">, 145 Sched<[WriteFCvtF64ToI32, ReadFCvtF64ToI32]>; 146 147 defm FCVT_D_W : FPUnaryOp_r_frmlegacy_m<0b1101001, 0b00000, Ext, Ext.PrimaryTy, GPR, 148 "fcvt.d.w">, 149 Sched<[WriteFCvtI32ToF64, ReadFCvtI32ToF64]>; 150 151 defm FCVT_D_WU : FPUnaryOp_r_frmlegacy_m<0b1101001, 0b00001, Ext, Ext.PrimaryTy, GPR, 152 "fcvt.d.wu">, 153 Sched<[WriteFCvtI32ToF64, ReadFCvtI32ToF64]>; 154} // foreach Ext = DExts 155 156foreach Ext = DExtsRV64 in { 157 defm FCVT_L_D : FPUnaryOp_r_frm_m<0b1100001, 0b00010, Ext, GPR, Ext.PrimaryTy, 158 "fcvt.l.d", [IsRV64]>, 159 Sched<[WriteFCvtF64ToI64, ReadFCvtF64ToI64]>; 160 161 defm FCVT_LU_D : FPUnaryOp_r_frm_m<0b1100001, 0b00011, Ext, GPR, Ext.PrimaryTy, 162 "fcvt.lu.d", [IsRV64]>, 163 Sched<[WriteFCvtF64ToI64, ReadFCvtF64ToI64]>; 164 165 defm FCVT_D_L : FPUnaryOp_r_frm_m<0b1101001, 0b00010, Ext, Ext.PrimaryTy, GPR, 166 "fcvt.d.l", [IsRV64]>, 167 Sched<[WriteFCvtI64ToF64, ReadFCvtI64ToF64]>; 168 169 defm FCVT_D_LU : FPUnaryOp_r_frm_m<0b1101001, 0b00011, Ext, Ext.PrimaryTy, GPR, 170 "fcvt.d.lu", [IsRV64]>, 171 Sched<[WriteFCvtI64ToF64, ReadFCvtI64ToF64]>; 172} // foreach Ext = DExts64 173 174let Predicates = [HasStdExtD, IsRV64], mayRaiseFPException = 0 in 175def FMV_X_D : FPUnaryOp_r<0b1110001, 0b00000, 0b000, GPR, FPR64, "fmv.x.d">, 176 Sched<[WriteFMovF64ToI64, ReadFMovF64ToI64]>; 177 178let Predicates = [HasStdExtD, IsRV64], mayRaiseFPException = 0 in 179def FMV_D_X : FPUnaryOp_r<0b1111001, 0b00000, 0b000, FPR64, GPR, "fmv.d.x">, 180 Sched<[WriteFMovI64ToF64, ReadFMovI64ToF64]>; 181 182//===----------------------------------------------------------------------===// 183// Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20) 184//===----------------------------------------------------------------------===// 185 186let Predicates = [HasStdExtD] in { 187def : InstAlias<"fld $rd, (${rs1})", (FLD FPR64:$rd, GPR:$rs1, 0), 0>; 188def : InstAlias<"fsd $rs2, (${rs1})", (FSD FPR64:$rs2, GPR:$rs1, 0), 0>; 189 190def : InstAlias<"fmv.d $rd, $rs", (FSGNJ_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>; 191def : InstAlias<"fabs.d $rd, $rs", (FSGNJX_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>; 192def : InstAlias<"fneg.d $rd, $rs", (FSGNJN_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>; 193 194// fgt.d/fge.d are recognised by the GNU assembler but the canonical 195// flt.d/fle.d forms will always be printed. Therefore, set a zero weight. 196def : InstAlias<"fgt.d $rd, $rs, $rt", 197 (FLT_D GPR:$rd, FPR64:$rt, FPR64:$rs), 0>; 198def : InstAlias<"fge.d $rd, $rs, $rt", 199 (FLE_D GPR:$rd, FPR64:$rt, FPR64:$rs), 0>; 200 201def PseudoFLD : PseudoFloatLoad<"fld", FPR64>; 202def PseudoFSD : PseudoStore<"fsd", FPR64>; 203let usesCustomInserter = 1 in { 204def PseudoQuietFLE_D : PseudoQuietFCMP<FPR64>; 205def PseudoQuietFLT_D : PseudoQuietFCMP<FPR64>; 206} 207} // Predicates = [HasStdExtD] 208 209let Predicates = [HasStdExtZdinx, IsRV64] in { 210def : InstAlias<"fmv.d $rd, $rs", (FSGNJ_D_INX FPR64INX:$rd, FPR64INX:$rs, FPR64INX:$rs)>; 211def : InstAlias<"fabs.d $rd, $rs", (FSGNJX_D_INX FPR64INX:$rd, FPR64INX:$rs, FPR64INX:$rs)>; 212def : InstAlias<"fneg.d $rd, $rs", (FSGNJN_D_INX FPR64INX:$rd, FPR64INX:$rs, FPR64INX:$rs)>; 213 214def : InstAlias<"fgt.d $rd, $rs, $rt", 215 (FLT_D_INX GPR:$rd, FPR64INX:$rt, FPR64INX:$rs), 0>; 216def : InstAlias<"fge.d $rd, $rs, $rt", 217 (FLE_D_INX GPR:$rd, FPR64INX:$rt, FPR64INX:$rs), 0>; 218let usesCustomInserter = 1 in { 219def PseudoQuietFLE_D_INX : PseudoQuietFCMP<FPR64INX>; 220def PseudoQuietFLT_D_INX : PseudoQuietFCMP<FPR64INX>; 221} 222} // Predicates = [HasStdExtZdinx, IsRV64] 223 224let Predicates = [HasStdExtZdinx, IsRV32] in { 225def : InstAlias<"fmv.d $rd, $rs", (FSGNJ_D_IN32X FPR64IN32X:$rd, FPR64IN32X:$rs, FPR64IN32X:$rs)>; 226def : InstAlias<"fabs.d $rd, $rs", (FSGNJX_D_IN32X FPR64IN32X:$rd, FPR64IN32X:$rs, FPR64IN32X:$rs)>; 227def : InstAlias<"fneg.d $rd, $rs", (FSGNJN_D_IN32X FPR64IN32X:$rd, FPR64IN32X:$rs, FPR64IN32X:$rs)>; 228 229def : InstAlias<"fgt.d $rd, $rs, $rt", 230 (FLT_D_IN32X GPR:$rd, FPR64IN32X:$rt, FPR64IN32X:$rs), 0>; 231def : InstAlias<"fge.d $rd, $rs, $rt", 232 (FLE_D_IN32X GPR:$rd, FPR64IN32X:$rt, FPR64IN32X:$rs), 0>; 233let usesCustomInserter = 1 in { 234def PseudoQuietFLE_D_IN32X : PseudoQuietFCMP<FPR64IN32X>; 235def PseudoQuietFLT_D_IN32X : PseudoQuietFCMP<FPR64IN32X>; 236} 237} // Predicates = [HasStdExtZdinx, IsRV32] 238 239//===----------------------------------------------------------------------===// 240// Pseudo-instructions and codegen patterns 241//===----------------------------------------------------------------------===// 242 243let Predicates = [HasStdExtD] in { 244 245/// Float conversion operations 246 247// f64 -> f32, f32 -> f64 248def : Pat<(any_fpround FPR64:$rs1), (FCVT_S_D FPR64:$rs1, FRM_DYN)>; 249def : Pat<(any_fpextend FPR32:$rs1), (FCVT_D_S FPR32:$rs1, FRM_RNE)>; 250} // Predicates = [HasStdExtD] 251 252let Predicates = [HasStdExtZdinx, IsRV64] in { 253/// Float conversion operations 254 255// f64 -> f32, f32 -> f64 256def : Pat<(any_fpround FPR64INX:$rs1), (FCVT_S_D_INX FPR64INX:$rs1, FRM_DYN)>; 257def : Pat<(any_fpextend FPR32INX:$rs1), (FCVT_D_S_INX FPR32INX:$rs1, FRM_RNE)>; 258} // Predicates = [HasStdExtZdinx, IsRV64] 259 260let Predicates = [HasStdExtZdinx, IsRV32] in { 261/// Float conversion operations 262 263// f64 -> f32, f32 -> f64 264def : Pat<(any_fpround FPR64IN32X:$rs1), (FCVT_S_D_IN32X FPR64IN32X:$rs1, FRM_DYN)>; 265def : Pat<(any_fpextend FPR32INX:$rs1), (FCVT_D_S_IN32X FPR32INX:$rs1, FRM_RNE)>; 266} // Predicates = [HasStdExtZdinx, IsRV32] 267 268// [u]int<->double conversion patterns must be gated on IsRV32 or IsRV64, so 269// are defined later. 270 271/// Float arithmetic operations 272 273foreach Ext = DExts in { 274 defm : PatFprFprDynFrm_m<any_fadd, FADD_D, Ext>; 275 defm : PatFprFprDynFrm_m<any_fsub, FSUB_D, Ext>; 276 defm : PatFprFprDynFrm_m<any_fmul, FMUL_D, Ext>; 277 defm : PatFprFprDynFrm_m<any_fdiv, FDIV_D, Ext>; 278} 279 280let Predicates = [HasStdExtD] in { 281def : Pat<(any_fsqrt FPR64:$rs1), (FSQRT_D FPR64:$rs1, FRM_DYN)>; 282 283def : Pat<(fneg FPR64:$rs1), (FSGNJN_D $rs1, $rs1)>; 284def : Pat<(fabs FPR64:$rs1), (FSGNJX_D $rs1, $rs1)>; 285 286def : Pat<(riscv_fclass FPR64:$rs1), (FCLASS_D $rs1)>; 287 288def : PatFprFpr<fcopysign, FSGNJ_D, FPR64, f64>; 289def : PatFprFpr<riscv_fsgnjx, FSGNJX_D, FPR64, f64>; 290def : Pat<(fcopysign FPR64:$rs1, (fneg FPR64:$rs2)), 291 (FSGNJN_D FPR64:$rs1, FPR64:$rs2)>; 292def : Pat<(fcopysign FPR64:$rs1, FPR32:$rs2), (FSGNJ_D $rs1, (FCVT_D_S $rs2, 293 FRM_RNE))>; 294def : Pat<(fcopysign FPR32:$rs1, FPR64:$rs2), (FSGNJ_S $rs1, (FCVT_S_D $rs2, 295 FRM_DYN))>; 296 297// fmadd: rs1 * rs2 + rs3 298def : Pat<(any_fma FPR64:$rs1, FPR64:$rs2, FPR64:$rs3), 299 (FMADD_D $rs1, $rs2, $rs3, FRM_DYN)>; 300 301// fmsub: rs1 * rs2 - rs3 302def : Pat<(any_fma FPR64:$rs1, FPR64:$rs2, (fneg FPR64:$rs3)), 303 (FMSUB_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, FRM_DYN)>; 304 305// fnmsub: -rs1 * rs2 + rs3 306def : Pat<(any_fma (fneg FPR64:$rs1), FPR64:$rs2, FPR64:$rs3), 307 (FNMSUB_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, FRM_DYN)>; 308 309// fnmadd: -rs1 * rs2 - rs3 310def : Pat<(any_fma (fneg FPR64:$rs1), FPR64:$rs2, (fneg FPR64:$rs3)), 311 (FNMADD_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, FRM_DYN)>; 312 313// fnmadd: -(rs1 * rs2 + rs3) (the nsz flag on the FMA) 314def : Pat<(fneg (any_fma_nsz FPR64:$rs1, FPR64:$rs2, FPR64:$rs3)), 315 (FNMADD_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, FRM_DYN)>; 316} // Predicates = [HasStdExtD] 317 318let Predicates = [HasStdExtZdinx, IsRV64] in { 319def : Pat<(any_fsqrt FPR64INX:$rs1), (FSQRT_D_INX FPR64INX:$rs1, FRM_DYN)>; 320 321def : Pat<(fneg FPR64INX:$rs1), (FSGNJN_D_INX $rs1, $rs1)>; 322def : Pat<(fabs FPR64INX:$rs1), (FSGNJX_D_INX $rs1, $rs1)>; 323 324def : Pat<(riscv_fclass FPR64INX:$rs1), (FCLASS_D_INX $rs1)>; 325 326def : PatFprFpr<fcopysign, FSGNJ_D_INX, FPR64INX, f64>; 327def : PatFprFpr<riscv_fsgnjx, FSGNJX_D_INX, FPR64INX, f64>; 328def : Pat<(fcopysign FPR64INX:$rs1, (fneg FPR64INX:$rs2)), 329 (FSGNJN_D_INX FPR64INX:$rs1, FPR64INX:$rs2)>; 330def : Pat<(fcopysign FPR64INX:$rs1, FPR32INX:$rs2), 331 (FSGNJ_D_INX $rs1, (f64 (FCVT_D_S_INX $rs2, FRM_RNE)))>; 332def : Pat<(fcopysign FPR32INX:$rs1, FPR64INX:$rs2), 333 (FSGNJ_S_INX $rs1, (FCVT_S_D_INX $rs2, FRM_DYN))>; 334 335// fmadd: rs1 * rs2 + rs3 336def : Pat<(any_fma FPR64INX:$rs1, FPR64INX:$rs2, FPR64INX:$rs3), 337 (FMADD_D_INX $rs1, $rs2, $rs3, FRM_DYN)>; 338 339// fmsub: rs1 * rs2 - rs3 340def : Pat<(any_fma FPR64INX:$rs1, FPR64INX:$rs2, (fneg FPR64INX:$rs3)), 341 (FMSUB_D_INX FPR64INX:$rs1, FPR64INX:$rs2, FPR64INX:$rs3, FRM_DYN)>; 342 343// fnmsub: -rs1 * rs2 + rs3 344def : Pat<(any_fma (fneg FPR64INX:$rs1), FPR64INX:$rs2, FPR64INX:$rs3), 345 (FNMSUB_D_INX FPR64INX:$rs1, FPR64INX:$rs2, FPR64INX:$rs3, FRM_DYN)>; 346 347// fnmadd: -rs1 * rs2 - rs3 348def : Pat<(any_fma (fneg FPR64INX:$rs1), FPR64INX:$rs2, (fneg FPR64INX:$rs3)), 349 (FNMADD_D_INX FPR64INX:$rs1, FPR64INX:$rs2, FPR64INX:$rs3, FRM_DYN)>; 350 351// fnmadd: -(rs1 * rs2 + rs3) (the nsz flag on the FMA) 352def : Pat<(fneg (any_fma_nsz FPR64INX:$rs1, FPR64INX:$rs2, FPR64INX:$rs3)), 353 (FNMADD_D_INX FPR64INX:$rs1, FPR64INX:$rs2, FPR64INX:$rs3, FRM_DYN)>; 354} // Predicates = [HasStdExtZdinx, IsRV64] 355 356let Predicates = [HasStdExtZdinx, IsRV32] in { 357def : Pat<(any_fsqrt FPR64IN32X:$rs1), (FSQRT_D_IN32X FPR64IN32X:$rs1, FRM_DYN)>; 358 359def : Pat<(fneg FPR64IN32X:$rs1), (FSGNJN_D_IN32X $rs1, $rs1)>; 360def : Pat<(fabs FPR64IN32X:$rs1), (FSGNJX_D_IN32X $rs1, $rs1)>; 361 362def : Pat<(riscv_fclass FPR64IN32X:$rs1), (FCLASS_D_IN32X $rs1)>; 363 364def : PatFprFpr<fcopysign, FSGNJ_D_IN32X, FPR64IN32X, f64>; 365def : PatFprFpr<riscv_fsgnjx, FSGNJX_D_IN32X, FPR64IN32X, f64>; 366def : Pat<(fcopysign FPR64IN32X:$rs1, (fneg FPR64IN32X:$rs2)), 367 (FSGNJN_D_IN32X FPR64IN32X:$rs1, FPR64IN32X:$rs2)>; 368def : Pat<(fcopysign FPR64IN32X:$rs1, FPR32INX:$rs2), 369 (FSGNJ_D_IN32X $rs1, (FCVT_D_S_IN32X $rs2, FRM_RNE))>; 370def : Pat<(fcopysign FPR32INX:$rs1, FPR64IN32X:$rs2), 371 (FSGNJ_S_INX $rs1, (FCVT_S_D_IN32X $rs2, FRM_DYN))>; 372 373// fmadd: rs1 * rs2 + rs3 374def : Pat<(any_fma FPR64IN32X:$rs1, FPR64IN32X:$rs2, FPR64IN32X:$rs3), 375 (FMADD_D_IN32X $rs1, $rs2, $rs3, FRM_DYN)>; 376 377// fmsub: rs1 * rs2 - rs3 378def : Pat<(any_fma FPR64IN32X:$rs1, FPR64IN32X:$rs2, (fneg FPR64IN32X:$rs3)), 379 (FMSUB_D_IN32X FPR64IN32X:$rs1, FPR64IN32X:$rs2, FPR64IN32X:$rs3, FRM_DYN)>; 380 381// fnmsub: -rs1 * rs2 + rs3 382def : Pat<(any_fma (fneg FPR64IN32X:$rs1), FPR64IN32X:$rs2, FPR64IN32X:$rs3), 383 (FNMSUB_D_IN32X FPR64IN32X:$rs1, FPR64IN32X:$rs2, FPR64IN32X:$rs3, FRM_DYN)>; 384 385// fnmadd: -rs1 * rs2 - rs3 386def : Pat<(any_fma (fneg FPR64IN32X:$rs1), FPR64IN32X:$rs2, (fneg FPR64IN32X:$rs3)), 387 (FNMADD_D_IN32X FPR64IN32X:$rs1, FPR64IN32X:$rs2, FPR64IN32X:$rs3, FRM_DYN)>; 388 389// fnmadd: -(rs1 * rs2 + rs3) (the nsz flag on the FMA) 390def : Pat<(fneg (any_fma_nsz FPR64IN32X:$rs1, FPR64IN32X:$rs2, FPR64IN32X:$rs3)), 391 (FNMADD_D_IN32X FPR64IN32X:$rs1, FPR64IN32X:$rs2, FPR64IN32X:$rs3, FRM_DYN)>; 392} // Predicates = [HasStdExtZdinx, IsRV32] 393 394// The ratified 20191213 ISA spec defines fmin and fmax in a way that matches 395// LLVM's fminnum and fmaxnum. 396// <https://github.com/riscv/riscv-isa-manual/commit/cd20cee7efd9bac7c5aa127ec3b451749d2b3cce>. 397foreach Ext = DExts in { 398 defm : PatFprFpr_m<fminnum, FMIN_D, Ext>; 399 defm : PatFprFpr_m<fmaxnum, FMAX_D, Ext>; 400 defm : PatFprFpr_m<fminimumnum, FMIN_D, Ext>; 401 defm : PatFprFpr_m<fmaximumnum, FMAX_D, Ext>; 402 defm : PatFprFpr_m<riscv_fmin, FMIN_D, Ext>; 403 defm : PatFprFpr_m<riscv_fmax, FMAX_D, Ext>; 404 def : Pat<(f64 (fcanonicalize FPR64:$rs1)), (FMIN_D $rs1, $rs1)>; 405} 406 407/// Setcc 408// FIXME: SETEQ/SETLT/SETLE imply nonans, can we pick better instructions for 409// strict versions of those. 410 411// Match non-signaling FEQ_D 412foreach Ext = DExts in { 413 defm : PatSetCC_m<any_fsetcc, SETEQ, FEQ_D, Ext>; 414 defm : PatSetCC_m<any_fsetcc, SETOEQ, FEQ_D, Ext>; 415 defm : PatSetCC_m<strict_fsetcc, SETLT, PseudoQuietFLT_D, Ext>; 416 defm : PatSetCC_m<strict_fsetcc, SETOLT, PseudoQuietFLT_D, Ext>; 417 defm : PatSetCC_m<strict_fsetcc, SETLE, PseudoQuietFLE_D, Ext>; 418 defm : PatSetCC_m<strict_fsetcc, SETOLE, PseudoQuietFLE_D, Ext>; 419} 420 421let Predicates = [HasStdExtD] in { 422// Match signaling FEQ_D 423def : Pat<(XLenVT (strict_fsetccs FPR64:$rs1, FPR64:$rs2, SETEQ)), 424 (AND (XLenVT (FLE_D $rs1, $rs2)), 425 (XLenVT (FLE_D $rs2, $rs1)))>; 426def : Pat<(XLenVT (strict_fsetccs FPR64:$rs1, FPR64:$rs2, SETOEQ)), 427 (AND (XLenVT (FLE_D $rs1, $rs2)), 428 (XLenVT (FLE_D $rs2, $rs1)))>; 429// If both operands are the same, use a single FLE. 430def : Pat<(XLenVT (strict_fsetccs FPR64:$rs1, FPR64:$rs1, SETEQ)), 431 (FLE_D $rs1, $rs1)>; 432def : Pat<(XLenVT (strict_fsetccs FPR64:$rs1, FPR64:$rs1, SETOEQ)), 433 (FLE_D $rs1, $rs1)>; 434 435def : PatSetCC<FPR64, any_fsetccs, SETLT, FLT_D, f64>; 436def : PatSetCC<FPR64, any_fsetccs, SETOLT, FLT_D, f64>; 437def : PatSetCC<FPR64, any_fsetccs, SETLE, FLE_D, f64>; 438def : PatSetCC<FPR64, any_fsetccs, SETOLE, FLE_D, f64>; 439} // Predicates = [HasStdExtD] 440 441let Predicates = [HasStdExtZdinx, IsRV64] in { 442// Match signaling FEQ_D 443def : Pat<(XLenVT (strict_fsetccs (f64 FPR64INX:$rs1), FPR64INX:$rs2, SETEQ)), 444 (AND (XLenVT (FLE_D_INX $rs1, $rs2)), 445 (XLenVT (FLE_D_INX $rs2, $rs1)))>; 446def : Pat<(XLenVT (strict_fsetccs (f64 FPR64INX:$rs1), FPR64INX:$rs2, SETOEQ)), 447 (AND (XLenVT (FLE_D_INX $rs1, $rs2)), 448 (XLenVT (FLE_D_INX $rs2, $rs1)))>; 449// If both operands are the same, use a single FLE. 450def : Pat<(XLenVT (strict_fsetccs (f64 FPR64INX:$rs1), FPR64INX:$rs1, SETEQ)), 451 (FLE_D_INX $rs1, $rs1)>; 452def : Pat<(XLenVT (strict_fsetccs (f64 FPR64INX:$rs1), FPR64INX:$rs1, SETOEQ)), 453 (FLE_D_INX $rs1, $rs1)>; 454 455def : PatSetCC<FPR64INX, any_fsetccs, SETLT, FLT_D_INX, f64>; 456def : PatSetCC<FPR64INX, any_fsetccs, SETOLT, FLT_D_INX, f64>; 457def : PatSetCC<FPR64INX, any_fsetccs, SETLE, FLE_D_INX, f64>; 458def : PatSetCC<FPR64INX, any_fsetccs, SETOLE, FLE_D_INX, f64>; 459} // Predicates = [HasStdExtZdinx, IsRV64] 460 461let Predicates = [HasStdExtZdinx, IsRV32] in { 462// Match signaling FEQ_D 463def : Pat<(XLenVT (strict_fsetccs (f64 FPR64IN32X:$rs1), FPR64IN32X:$rs2, SETEQ)), 464 (AND (XLenVT (FLE_D_IN32X $rs1, $rs2)), 465 (XLenVT (FLE_D_IN32X $rs2, $rs1)))>; 466def : Pat<(XLenVT (strict_fsetccs (f64 FPR64IN32X:$rs1), FPR64IN32X:$rs2, SETOEQ)), 467 (AND (XLenVT (FLE_D_IN32X $rs1, $rs2)), 468 (XLenVT (FLE_D_IN32X $rs2, $rs1)))>; 469// If both operands are the same, use a single FLE. 470def : Pat<(XLenVT (strict_fsetccs (f64 FPR64IN32X:$rs1), FPR64IN32X:$rs1, SETEQ)), 471 (FLE_D_IN32X $rs1, $rs1)>; 472def : Pat<(XLenVT (strict_fsetccs (f64 FPR64IN32X:$rs1), FPR64IN32X:$rs1, SETOEQ)), 473 (FLE_D_IN32X $rs1, $rs1)>; 474 475def : PatSetCC<FPR64IN32X, any_fsetccs, SETLT, FLT_D_IN32X, f64>; 476def : PatSetCC<FPR64IN32X, any_fsetccs, SETOLT, FLT_D_IN32X, f64>; 477def : PatSetCC<FPR64IN32X, any_fsetccs, SETLE, FLE_D_IN32X, f64>; 478def : PatSetCC<FPR64IN32X, any_fsetccs, SETOLE, FLE_D_IN32X, f64>; 479} // Predicates = [HasStdExtZdinx, IsRV32] 480 481let Predicates = [HasStdExtD] in { 482defm Select_FPR64 : SelectCC_GPR_rrirr<FPR64, f64>; 483 484def PseudoFROUND_D : PseudoFROUND<FPR64, f64>; 485 486/// Loads 487 488def : LdPat<load, FLD, f64>; 489 490/// Stores 491 492def : StPat<store, FSD, FPR64, f64>; 493} // Predicates = [HasStdExtD] 494 495let Predicates = [HasStdExtD, NoStdExtZfa, IsRV32] in { 496/// Pseudo-instructions needed for the soft-float ABI with RV32D 497 498// Moves two GPRs to an FPR. 499let usesCustomInserter = 1 in 500def BuildPairF64Pseudo 501 : Pseudo<(outs FPR64:$dst), (ins GPR:$src1, GPR:$src2), 502 [(set FPR64:$dst, (RISCVBuildPairF64 GPR:$src1, GPR:$src2))]>; 503 504// Moves an FPR to two GPRs. 505let usesCustomInserter = 1 in 506def SplitF64Pseudo 507 : Pseudo<(outs GPR:$dst1, GPR:$dst2), (ins FPR64:$src), 508 [(set GPR:$dst1, GPR:$dst2, (RISCVSplitF64 FPR64:$src))]>; 509 510} // Predicates = [HasStdExtD, NoStdExtZfa, IsRV32] 511 512let Predicates = [HasStdExtZdinx, IsRV64] in { 513defm Select_FPR64INX : SelectCC_GPR_rrirr<FPR64INX, f64>; 514 515def PseudoFROUND_D_INX : PseudoFROUND<FPR64INX, f64>; 516 517/// Loads 518def : LdPat<load, LD, f64>; 519 520/// Stores 521def : StPat<store, SD, GPR, f64>; 522} // Predicates = [HasStdExtZdinx, IsRV64] 523 524let Predicates = [HasStdExtZdinx, IsRV32] in { 525defm Select_FPR64IN32X : SelectCC_GPR_rrirr<FPR64IN32X, f64>; 526 527def PseudoFROUND_D_IN32X : PseudoFROUND<FPR64IN32X, f64>; 528 529/// Loads 530let isCall = 0, mayLoad = 1, mayStore = 0, Size = 8, isCodeGenOnly = 1 in 531def PseudoRV32ZdinxLD : Pseudo<(outs GPRPair:$dst), (ins GPR:$rs1, simm12:$imm12), []>; 532def : Pat<(f64 (load (AddrRegImmINX (XLenVT GPR:$rs1), simm12:$imm12))), 533 (PseudoRV32ZdinxLD GPR:$rs1, simm12:$imm12)>; 534 535/// Stores 536let isCall = 0, mayLoad = 0, mayStore = 1, Size = 8, isCodeGenOnly = 1 in 537def PseudoRV32ZdinxSD : Pseudo<(outs), (ins GPRPair:$rs2, GPRNoX0:$rs1, simm12:$imm12), []>; 538def : Pat<(store (f64 GPRPair:$rs2), (AddrRegImmINX (XLenVT GPR:$rs1), simm12:$imm12)), 539 (PseudoRV32ZdinxSD GPRPair:$rs2, GPR:$rs1, simm12:$imm12)>; 540} // Predicates = [HasStdExtZdinx, IsRV32] 541 542let Predicates = [HasStdExtD, IsRV32] in { 543 544// double->[u]int. Round-to-zero must be used. 545def : Pat<(i32 (any_fp_to_sint FPR64:$rs1)), (FCVT_W_D FPR64:$rs1, FRM_RTZ)>; 546def : Pat<(i32 (any_fp_to_uint FPR64:$rs1)), (FCVT_WU_D FPR64:$rs1, FRM_RTZ)>; 547 548// Saturating double->[u]int32. 549def : Pat<(i32 (riscv_fcvt_x FPR64:$rs1, timm:$frm)), (FCVT_W_D $rs1, timm:$frm)>; 550def : Pat<(i32 (riscv_fcvt_xu FPR64:$rs1, timm:$frm)), (FCVT_WU_D $rs1, timm:$frm)>; 551 552// float->int32 with current rounding mode. 553def : Pat<(i32 (any_lrint FPR64:$rs1)), (FCVT_W_D $rs1, FRM_DYN)>; 554 555// float->int32 rounded to nearest with ties rounded away from zero. 556def : Pat<(i32 (any_lround FPR64:$rs1)), (FCVT_W_D $rs1, FRM_RMM)>; 557 558// [u]int->double. 559def : Pat<(any_sint_to_fp (i32 GPR:$rs1)), (FCVT_D_W GPR:$rs1, FRM_RNE)>; 560def : Pat<(any_uint_to_fp (i32 GPR:$rs1)), (FCVT_D_WU GPR:$rs1, FRM_RNE)>; 561} // Predicates = [HasStdExtD, IsRV32] 562 563let Predicates = [HasStdExtZdinx, IsRV32] in { 564 565// double->[u]int. Round-to-zero must be used. 566def : Pat<(i32 (any_fp_to_sint FPR64IN32X:$rs1)), (FCVT_W_D_IN32X FPR64IN32X:$rs1, FRM_RTZ)>; 567def : Pat<(i32 (any_fp_to_uint FPR64IN32X:$rs1)), (FCVT_WU_D_IN32X FPR64IN32X:$rs1, FRM_RTZ)>; 568 569// Saturating double->[u]int32. 570def : Pat<(i32 (riscv_fcvt_x FPR64IN32X:$rs1, timm:$frm)), (FCVT_W_D_IN32X $rs1, timm:$frm)>; 571def : Pat<(i32 (riscv_fcvt_xu FPR64IN32X:$rs1, timm:$frm)), (FCVT_WU_D_IN32X $rs1, timm:$frm)>; 572 573// float->int32 with current rounding mode. 574def : Pat<(i32 (any_lrint FPR64IN32X:$rs1)), (FCVT_W_D_IN32X $rs1, FRM_DYN)>; 575 576// float->int32 rounded to nearest with ties rounded away from zero. 577def : Pat<(i32 (any_lround FPR64IN32X:$rs1)), (FCVT_W_D_IN32X $rs1, FRM_RMM)>; 578 579// [u]int->double. 580def : Pat<(any_sint_to_fp (i32 GPR:$rs1)), (FCVT_D_W_IN32X GPR:$rs1, FRM_RNE)>; 581def : Pat<(any_uint_to_fp (i32 GPR:$rs1)), (FCVT_D_WU_IN32X GPR:$rs1, FRM_RNE)>; 582} // Predicates = [HasStdExtZdinx, IsRV32] 583 584let Predicates = [HasStdExtD, IsRV64] in { 585 586// Moves (no conversion) 587def : Pat<(bitconvert (i64 GPR:$rs1)), (FMV_D_X GPR:$rs1)>; 588def : Pat<(i64 (bitconvert FPR64:$rs1)), (FMV_X_D FPR64:$rs1)>; 589 590// Use target specific isd nodes to help us remember the result is sign 591// extended. Matching sext_inreg+fptoui/fptosi may cause the conversion to be 592// duplicated if it has another user that didn't need the sign_extend. 593def : Pat<(riscv_any_fcvt_w_rv64 FPR64:$rs1, timm:$frm), (FCVT_W_D $rs1, timm:$frm)>; 594def : Pat<(riscv_any_fcvt_wu_rv64 FPR64:$rs1, timm:$frm), (FCVT_WU_D $rs1, timm:$frm)>; 595 596// [u]int32->fp 597def : Pat<(any_sint_to_fp (i64 (sexti32 (i64 GPR:$rs1)))), (FCVT_D_W $rs1, FRM_RNE)>; 598def : Pat<(any_uint_to_fp (i64 (zexti32 (i64 GPR:$rs1)))), (FCVT_D_WU $rs1, FRM_RNE)>; 599 600// Saturating double->[u]int64. 601def : Pat<(i64 (riscv_fcvt_x FPR64:$rs1, timm:$frm)), (FCVT_L_D $rs1, timm:$frm)>; 602def : Pat<(i64 (riscv_fcvt_xu FPR64:$rs1, timm:$frm)), (FCVT_LU_D $rs1, timm:$frm)>; 603 604// double->[u]int64. Round-to-zero must be used. 605def : Pat<(i64 (any_fp_to_sint FPR64:$rs1)), (FCVT_L_D FPR64:$rs1, FRM_RTZ)>; 606def : Pat<(i64 (any_fp_to_uint FPR64:$rs1)), (FCVT_LU_D FPR64:$rs1, FRM_RTZ)>; 607 608// double->int64 with current rounding mode. 609def : Pat<(i64 (any_lrint FPR64:$rs1)), (FCVT_L_D $rs1, FRM_DYN)>; 610def : Pat<(i64 (any_llrint FPR64:$rs1)), (FCVT_L_D $rs1, FRM_DYN)>; 611 612// double->int64 rounded to nearest with ties rounded away from zero. 613def : Pat<(i64 (any_lround FPR64:$rs1)), (FCVT_L_D $rs1, FRM_RMM)>; 614def : Pat<(i64 (any_llround FPR64:$rs1)), (FCVT_L_D $rs1, FRM_RMM)>; 615 616// [u]int64->fp. Match GCC and default to using dynamic rounding mode. 617def : Pat<(any_sint_to_fp (i64 GPR:$rs1)), (FCVT_D_L GPR:$rs1, FRM_DYN)>; 618def : Pat<(any_uint_to_fp (i64 GPR:$rs1)), (FCVT_D_LU GPR:$rs1, FRM_DYN)>; 619} // Predicates = [HasStdExtD, IsRV64] 620 621let Predicates = [HasStdExtZdinx, IsRV64] in { 622 623// Moves (no conversion) 624def : Pat<(f64 (bitconvert (i64 GPR:$rs1))), (COPY_TO_REGCLASS GPR:$rs1, GPR)>; 625def : Pat<(i64 (bitconvert (f64 GPR:$rs1))), (COPY_TO_REGCLASS GPR:$rs1, GPR)>; 626 627// Use target specific isd nodes to help us remember the result is sign 628// extended. Matching sext_inreg+fptoui/fptosi may cause the conversion to be 629// duplicated if it has another user that didn't need the sign_extend. 630def : Pat<(riscv_any_fcvt_w_rv64 FPR64INX:$rs1, timm:$frm), (FCVT_W_D_INX $rs1, timm:$frm)>; 631def : Pat<(riscv_any_fcvt_wu_rv64 FPR64INX:$rs1, timm:$frm), (FCVT_WU_D_INX $rs1, timm:$frm)>; 632 633// [u]int32->fp 634def : Pat<(any_sint_to_fp (i64 (sexti32 (i64 GPR:$rs1)))), (FCVT_D_W_INX $rs1, FRM_RNE)>; 635def : Pat<(any_uint_to_fp (i64 (zexti32 (i64 GPR:$rs1)))), (FCVT_D_WU_INX $rs1, FRM_RNE)>; 636 637// Saturating double->[u]int64. 638def : Pat<(i64 (riscv_fcvt_x FPR64INX:$rs1, timm:$frm)), (FCVT_L_D_INX $rs1, timm:$frm)>; 639def : Pat<(i64 (riscv_fcvt_xu FPR64INX:$rs1, timm:$frm)), (FCVT_LU_D_INX $rs1, timm:$frm)>; 640 641// double->[u]int64. Round-to-zero must be used. 642def : Pat<(i64 (any_fp_to_sint FPR64INX:$rs1)), (FCVT_L_D_INX FPR64INX:$rs1, FRM_RTZ)>; 643def : Pat<(i64 (any_fp_to_uint FPR64INX:$rs1)), (FCVT_LU_D_INX FPR64INX:$rs1, FRM_RTZ)>; 644 645// double->int64 with current rounding mode. 646def : Pat<(i64 (any_lrint FPR64INX:$rs1)), (FCVT_L_D_INX $rs1, FRM_DYN)>; 647def : Pat<(i64 (any_llrint FPR64INX:$rs1)), (FCVT_L_D_INX $rs1, FRM_DYN)>; 648 649// double->int64 rounded to nearest with ties rounded away from zero. 650def : Pat<(i64 (any_lround FPR64INX:$rs1)), (FCVT_L_D_INX $rs1, FRM_RMM)>; 651def : Pat<(i64 (any_llround FPR64INX:$rs1)), (FCVT_L_D_INX $rs1, FRM_RMM)>; 652 653// [u]int64->fp. Match GCC and default to using dynamic rounding mode. 654def : Pat<(any_sint_to_fp (i64 GPR:$rs1)), (FCVT_D_L_INX GPR:$rs1, FRM_DYN)>; 655def : Pat<(any_uint_to_fp (i64 GPR:$rs1)), (FCVT_D_LU_INX GPR:$rs1, FRM_DYN)>; 656} // Predicates = [HasStdExtZdinx, IsRV64] 657