1//===-- RISCVInstrGISel.td - RISC-V GISel target pseudos ----*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9/// \file 10// RISC-V GlobalISel target pseudo instruction definitions. This is kept 11// separately from the other tablegen files for organizational purposes, but 12// share the same infrastructure. 13// 14//===----------------------------------------------------------------------===// 15 16class RISCVGenericInstruction : GenericInstruction { 17 let Namespace = "RISCV"; 18} 19 20// Pseudo equivalent to a RISCVISD::SRAW. 21def G_SRAW : RISCVGenericInstruction { 22 let OutOperandList = (outs type0:$dst); 23 let InOperandList = (ins type0:$src1, type0:$src2); 24 let hasSideEffects = false; 25} 26def : GINodeEquiv<G_SRAW, riscv_sraw>; 27 28// Pseudo equivalent to a RISCVISD::SRLW. 29def G_SRLW : RISCVGenericInstruction { 30 let OutOperandList = (outs type0:$dst); 31 let InOperandList = (ins type0:$src1, type0:$src2); 32 let hasSideEffects = false; 33} 34def : GINodeEquiv<G_SRLW, riscv_srlw>; 35 36// Pseudo equivalent to a RISCVISD::SLLW. 37def G_SLLW : RISCVGenericInstruction { 38 let OutOperandList = (outs type0:$dst); 39 let InOperandList = (ins type0:$src1, type0:$src2); 40 let hasSideEffects = false; 41} 42def : GINodeEquiv<G_SLLW, riscv_sllw>; 43 44// Pseudo equivalent to a RISCVISD::DIVW. 45def G_DIVW : RISCVGenericInstruction { 46 let OutOperandList = (outs type0:$dst); 47 let InOperandList = (ins type0:$src1, type0:$src2); 48 let hasSideEffects = false; 49} 50def : GINodeEquiv<G_DIVW, riscv_divw>; 51 52// Pseudo equivalent to a RISCVISD::DIVUW. 53def G_DIVUW : RISCVGenericInstruction { 54 let OutOperandList = (outs type0:$dst); 55 let InOperandList = (ins type0:$src1, type0:$src2); 56 let hasSideEffects = false; 57} 58def : GINodeEquiv<G_DIVUW, riscv_divuw>; 59 60// Pseudo equivalent to a RISCVISD::REMUW. 61def G_REMUW : RISCVGenericInstruction { 62 let OutOperandList = (outs type0:$dst); 63 let InOperandList = (ins type0:$src1, type0:$src2); 64 let hasSideEffects = false; 65} 66def : GINodeEquiv<G_REMUW, riscv_remuw>; 67 68// Pseudo equivalent to a RISCVISD::RORW. 69def G_RORW : RISCVGenericInstruction { 70 let OutOperandList = (outs type0:$dst); 71 let InOperandList = (ins type0:$src1, type0:$src2); 72 let hasSideEffects = false; 73} 74def : GINodeEquiv<G_RORW, riscv_rorw>; 75 76// Pseudo equivalent to a RISCVISD::ROLW. 77def G_ROLW : RISCVGenericInstruction { 78 let OutOperandList = (outs type0:$dst); 79 let InOperandList = (ins type0:$src1, type0:$src2); 80 let hasSideEffects = false; 81} 82def : GINodeEquiv<G_ROLW, riscv_rolw>; 83 84// Pseudo equivalent to a RISCVISD::CLZW. 85def G_CLZW : RISCVGenericInstruction { 86 let OutOperandList = (outs type0:$dst); 87 let InOperandList = (ins type0:$src); 88 let hasSideEffects = false; 89} 90def : GINodeEquiv<G_CLZW, riscv_clzw>; 91 92// Pseudo equivalent to a RISCVISD::CTZW. 93def G_CTZW : RISCVGenericInstruction { 94 let OutOperandList = (outs type0:$dst); 95 let InOperandList = (ins type0:$src); 96 let hasSideEffects = false; 97} 98def : GINodeEquiv<G_CTZW, riscv_ctzw>; 99 100// Pseudo equivalent to a RISCVISD::FCVT_W_RV64. 101def G_FCVT_W_RV64 : RISCVGenericInstruction { 102 let OutOperandList = (outs type0:$dst); 103 let InOperandList = (ins type1:$src, untyped_imm_0:$frm); 104 let hasSideEffects = false; 105} 106def : GINodeEquiv<G_FCVT_W_RV64, riscv_fcvt_w_rv64>; 107 108// Pseudo equivalent to a RISCVISD::FCVT_WU_RV64. 109def G_FCVT_WU_RV64 : RISCVGenericInstruction { 110 let OutOperandList = (outs type0:$dst); 111 let InOperandList = (ins type1:$src, untyped_imm_0:$frm); 112 let hasSideEffects = false; 113} 114def : GINodeEquiv<G_FCVT_WU_RV64, riscv_fcvt_wu_rv64>; 115 116// Pseudo equivalent to a RISCVISD::FCLASS. 117def G_FCLASS : RISCVGenericInstruction { 118 let OutOperandList = (outs type0:$dst); 119 let InOperandList = (ins type1:$src); 120 let hasSideEffects = false; 121} 122def : GINodeEquiv<G_FCLASS, riscv_fclass>; 123 124// Pseudo equivalent to a RISCVISD::READ_VLENB. 125def G_READ_VLENB : RISCVGenericInstruction { 126 let OutOperandList = (outs type0:$dst); 127 let InOperandList = (ins); 128 let hasSideEffects = false; 129} 130def : GINodeEquiv<G_READ_VLENB, riscv_read_vlenb>; 131 132// Pseudo equivalent to a RISCVISD::VMCLR_VL 133def G_VMCLR_VL : RISCVGenericInstruction { 134 let OutOperandList = (outs type0:$dst); 135 let InOperandList = (ins type1:$vl); 136 let hasSideEffects = false; 137} 138def : GINodeEquiv<G_VMCLR_VL, riscv_vmclr_vl>; 139 140// Pseudo equivalent to a RISCVISD::VMSET_VL 141def G_VMSET_VL : RISCVGenericInstruction { 142 let OutOperandList = (outs type0:$dst); 143 let InOperandList = (ins type1:$vl); 144 let hasSideEffects = false; 145} 146def : GINodeEquiv<G_VMSET_VL, riscv_vmset_vl>; 147 148// Pseudo equivalent to a RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL. There is no 149// record to mark as equivalent to using GINodeEquiv because it gets lowered 150// before instruction selection. 151def G_SPLAT_VECTOR_SPLIT_I64_VL : RISCVGenericInstruction { 152 let OutOperandList = (outs type0:$dst); 153 let InOperandList = (ins type0:$passthru, type1:$hi, type1:$lo, type2:$vl); 154 let hasSideEffects = false; 155} 156 157// Pseudo equivalent to a RISCVISD::VSLIDEDOWN_VL 158def G_VSLIDEDOWN_VL : RISCVGenericInstruction { 159 let OutOperandList = (outs type0:$dst); 160 let InOperandList = (ins type0:$merge, type0:$vec, type1:$idx, type2:$mask, 161 type1:$vl, type1:$policy); 162 let hasSideEffects = false; 163} 164def : GINodeEquiv<G_VSLIDEDOWN_VL, riscv_slidedown_vl>; 165 166// Pseudo equivalent to a RISCVISD::VMV_V_V_VL 167def G_VMV_V_V_VL : RISCVGenericInstruction { 168 let OutOperandList = (outs type0:$dst); 169 let InOperandList = (ins type0:$passthru, type0:$vec, type1:$vl); 170 let hasSideEffects = false; 171} 172def : GINodeEquiv<G_VMV_V_V_VL, riscv_vmv_v_v_vl>; 173 174// Pseudo equivalent to a RISCVISD::VSLIDEUP_VL 175def G_VSLIDEUP_VL : RISCVGenericInstruction { 176 let OutOperandList = (outs type0:$dst); 177 let InOperandList = (ins type0:$merge, type0:$vec, type1:$idx, type2:$mask, 178 type3:$vl, type4:$policy); 179 let hasSideEffects = false; 180} 181def : GINodeEquiv<G_VSLIDEUP_VL, riscv_slideup_vl>; 182 183