xref: /llvm-project/llvm/lib/Target/RISCV/RISCVFeatures.td (revision 0cb7636a462a8d4209e2b6344304eb43f02853eb) 
1//===-- RISCVFeatures.td - RISC-V Features and Extensions --*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9//===----------------------------------------------------------------------===//
10// RISC-V subtarget features and instruction predicates.
11//===----------------------------------------------------------------------===//
12
13// Subclass of SubtargetFeature to be used when the feature is also a RISC-V
14// extension. Extensions have a version and may be experimental.
15// NOTE: The extension name must start with
16//       - "FeatureStdExt" for standard extensions
17//       - "FeatureVendor" for vendor-specific extensions
18//
19// major     - Major version of extension.
20// minor     - Minor version of extension.
21// desc      - Description of extension.
22// implies   - Extensions or features implied by this extension.
23// fieldname - name of field to create in RISCVSubtarget. By default replaces
24//             uses the record name by replacing Feature with Has.
25// value     - Value to assign to the field in RISCVSubtarget when this
26//             extension is enabled. Usually "true", but can be changed.
27// IsExperimental
28//           - Indicates whether the extension is experimental
29class RISCVExtension<int major, int minor, string desc,
30                     list<SubtargetFeature> implies = [],
31                     string fieldname = !subst("Feature", "Has", NAME),
32                     string value = "true", bit IsExperimental = false>
33    : SubtargetFeature<"", fieldname, value, "", implies> {
34  defvar extName = !subst("FeatureVendor", "", !subst("FeatureStdExt", "", NAME));
35
36  // Name - Name of the extension in lower case.
37  let Name = !if(IsExperimental, "experimental-", "") # !tolower(extName);
38
39  // Desc - Description of extension with its name.
40  let Desc = "'" # extName # "' (" # desc # ")";
41
42  // MajorVersion - The major version for this extension.
43  int MajorVersion = major;
44
45  // MinorVersion - The minor version for this extension.
46  int MinorVersion = minor;
47
48  // Experimental - Does extension require -menable-experimental-extensions.
49  bit Experimental = false;
50}
51
52// The groupID/bitmask of RISCVExtension is used to retrieve a specific bit value
53// from __riscv_feature_bits based on the groupID and bitmask.
54// groupID - groupID of extension
55// bitPos  - bit position of extension bitmask
56class RISCVExtensionBitmask<bits<3> groupID, int bitPos> {
57    int GroupID = groupID;
58    int BitPos = bitPos;
59}
60
61// Version of RISCVExtension to be used for Experimental extensions. This
62// sets the Experimental flag and prepends experimental- to the -mattr name.
63class RISCVExperimentalExtension<int major, int minor, string desc,
64                                 list<RISCVExtension> implies = [],
65                                 string fieldname = !subst("Feature", "Has", NAME),
66                                 string value = "true">
67    : RISCVExtension<major, minor, desc, implies, fieldname, value, true> {
68  let Experimental = true;
69}
70
71// Integer Extensions
72
73def FeatureStdExtI
74    : RISCVExtension<2, 1, "Base Integer Instruction Set">,
75      RISCVExtensionBitmask<0, 8>;
76
77def FeatureStdExtE
78    : RISCVExtension<2, 0, "Embedded Instruction Set with 16 GPRs">;
79
80def FeatureStdExtZic64b
81    : RISCVExtension<1, 0, "Cache Block Size Is 64 Bytes">;
82
83def FeatureStdExtZicbom
84    : RISCVExtension<1, 0, "Cache-Block Management Instructions">;
85def HasStdExtZicbom : Predicate<"Subtarget->hasStdExtZicbom()">,
86                      AssemblerPredicate<(all_of FeatureStdExtZicbom),
87                          "'Zicbom' (Cache-Block Management Instructions)">;
88
89def FeatureStdExtZicbop
90    : RISCVExtension<1, 0, "Cache-Block Prefetch Instructions">;
91def HasStdExtZicbop : Predicate<"Subtarget->hasStdExtZicbop()">,
92                      AssemblerPredicate<(all_of FeatureStdExtZicbop),
93                          "'Zicbop' (Cache-Block Prefetch Instructions)">;
94
95def FeatureStdExtZicboz
96    : RISCVExtension<1, 0, "Cache-Block Zero Instructions">,
97      RISCVExtensionBitmask<0, 37>;
98def HasStdExtZicboz : Predicate<"Subtarget->hasStdExtZicboz()">,
99                      AssemblerPredicate<(all_of FeatureStdExtZicboz),
100                          "'Zicboz' (Cache-Block Zero Instructions)">;
101
102def FeatureStdExtZiccamoa
103    : RISCVExtension<1, 0, "Main Memory Supports All Atomics in A">;
104
105def FeatureStdExtZiccif
106    : RISCVExtension<1, 0,
107                     "Main Memory Supports Instruction Fetch with Atomicity Requirement">;
108
109def FeatureStdExtZicclsm
110    : RISCVExtension<1, 0, "Main Memory Supports Misaligned Loads/Stores">;
111
112def FeatureStdExtZiccrse
113    : RISCVExtension<1, 0,
114                     "Main Memory Supports Forward Progress on LR/SC Sequences">;
115
116def FeatureStdExtZicsr
117    : RISCVExtension<2, 0, "CSRs">;
118def HasStdExtZicsr : Predicate<"Subtarget->hasStdExtZicsr()">,
119                     AssemblerPredicate<(all_of FeatureStdExtZicsr),
120                                        "'Zicsr' (CSRs)">;
121
122def FeatureStdExtZicntr
123    : RISCVExtension<2, 0, "Base Counters and Timers",
124                     [FeatureStdExtZicsr]>;
125
126def FeatureStdExtZicond
127    : RISCVExtension<1, 0, "Integer Conditional Operations">,
128      RISCVExtensionBitmask<0, 38>;
129def HasStdExtZicond : Predicate<"Subtarget->hasStdExtZicond()">,
130                      AssemblerPredicate<(all_of FeatureStdExtZicond),
131                          "(Integer Conditional Operations)">;
132
133def FeatureStdExtZifencei
134    : RISCVExtension<2, 0, "fence.i">;
135def HasStdExtZifencei : Predicate<"Subtarget->hasStdExtZifencei()">,
136                        AssemblerPredicate<(all_of FeatureStdExtZifencei),
137                                           "'Zifencei' (fence.i)">;
138
139def FeatureStdExtZihintpause
140    : RISCVExtension<2, 0, "Pause Hint">,
141      RISCVExtensionBitmask<0, 40>;
142def HasStdExtZihintpause : Predicate<"Subtarget->hasStdExtZihintpause()">,
143                           AssemblerPredicate<(all_of FeatureStdExtZihintpause),
144                                              "'Zihintpause' (Pause Hint)">;
145
146def FeatureStdExtZihintntl
147    : RISCVExtension<1, 0, "Non-Temporal Locality Hints">,
148      RISCVExtensionBitmask<0, 39>;
149def HasStdExtZihintntl : Predicate<"Subtarget->hasStdExtZihintntl()">,
150                         AssemblerPredicate<(all_of FeatureStdExtZihintntl),
151                             "'Zihintntl' (Non-Temporal Locality Hints)">;
152
153def FeatureStdExtZihpm
154    : RISCVExtension<2, 0, "Hardware Performance Counters",
155                     [FeatureStdExtZicsr]>;
156
157def FeatureStdExtZimop : RISCVExtension<1, 0, "May-Be-Operations">;
158def HasStdExtZimop : Predicate<"Subtarget->hasStdExtZimop()">,
159                     AssemblerPredicate<(all_of FeatureStdExtZimop),
160                                        "'Zimop' (May-Be-Operations)">;
161
162def FeatureStdExtZicfilp
163    : RISCVExperimentalExtension<1, 0, "Landing pad",
164                                 [FeatureStdExtZicsr]>;
165def HasStdExtZicfilp : Predicate<"Subtarget->hasStdExtZicfilp()">,
166                       AssemblerPredicate<(all_of FeatureStdExtZicfilp),
167                                          "'Zicfilp' (Landing pad)">;
168def NoStdExtZicfilp : Predicate<"!Subtarget->hasStdExtZicfilp()">,
169                      AssemblerPredicate<(all_of (not FeatureStdExtZicfilp))>;
170
171def FeatureStdExtZicfiss
172    : RISCVExperimentalExtension<1, 0, "Shadow stack",
173                                 [FeatureStdExtZicsr, FeatureStdExtZimop]>;
174def HasStdExtZicfiss : Predicate<"Subtarget->hasStdExtZicfiss()">,
175                       AssemblerPredicate<(all_of FeatureStdExtZicfiss),
176                                          "'Zicfiss' (Shadow stack)">;
177def NoHasStdExtZicfiss : Predicate<"!Subtarget->hasStdExtZicfiss()">;
178
179// Multiply Extensions
180
181def FeatureStdExtZmmul
182    : RISCVExtension<1, 0, "Integer Multiplication">;
183def HasStdExtZmmul : Predicate<"Subtarget->hasStdExtZmmul()">,
184                     AssemblerPredicate<(all_of FeatureStdExtZmmul),
185                     "'Zmmul' (Integer Multiplication)">;
186
187def FeatureStdExtM
188    : RISCVExtension<2, 0, "Integer Multiplication and Division",
189                     [FeatureStdExtZmmul]>,
190      RISCVExtensionBitmask<0, 12>;
191def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
192                 AssemblerPredicate<(all_of FeatureStdExtM),
193                     "'M' (Integer Multiplication and Division)">;
194
195// Atomic Extensions
196
197def FeatureStdExtZaamo
198    : RISCVExtension<1, 0, "Atomic Memory Operations">;
199def HasStdExtZaamo
200    : Predicate<"Subtarget->hasStdExtZaamo()">,
201      AssemblerPredicate<(any_of FeatureStdExtZaamo),
202                         "'Zaamo' (Atomic Memory Operations)">;
203
204def FeatureStdExtZalrsc
205    : RISCVExtension<1, 0, "Load-Reserved/Store-Conditional">;
206def HasStdExtZalrsc
207    : Predicate<"Subtarget->hasStdExtZalrsc()">,
208      AssemblerPredicate<(any_of FeatureStdExtZalrsc),
209                         "'Zalrsc' (Load-Reserved/Store-Conditional)">;
210
211def FeatureStdExtA
212    : RISCVExtension<2, 1, "Atomic Instructions",
213                     [FeatureStdExtZaamo, FeatureStdExtZalrsc]>,
214      RISCVExtensionBitmask<0, 0>;
215def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">,
216                 AssemblerPredicate<(all_of FeatureStdExtA),
217                                    "'A' (Atomic Instructions)">;
218
219def FeatureStdExtZtso
220    : RISCVExtension<1, 0, "Memory Model - Total Store Order">,
221      RISCVExtensionBitmask<0, 47>;
222def HasStdExtZtso : Predicate<"Subtarget->hasStdExtZtso()">,
223                    AssemblerPredicate<(all_of FeatureStdExtZtso),
224                        "'Ztso' (Memory Model - Total Store Order)">;
225def NotHasStdExtZtso : Predicate<"!Subtarget->hasStdExtZtso()">;
226
227def FeatureStdExtZa64rs
228    : RISCVExtension<1, 0, "Reservation Set Size of at Most 64 Bytes">;
229
230def FeatureStdExtZa128rs
231    : RISCVExtension<1, 0, "Reservation Set Size of at Most 128 Bytes">;
232
233def FeatureStdExtZabha
234    : RISCVExtension<1, 0, "Byte and Halfword Atomic Memory Operations",
235                     [FeatureStdExtZaamo]>;
236def HasStdExtZabha : Predicate<"Subtarget->hasStdExtZabha()">,
237                     AssemblerPredicate<(all_of FeatureStdExtZabha),
238                         "'Zabha' (Byte and Halfword Atomic Memory Operations)">;
239
240def FeatureStdExtZacas
241    : RISCVExtension<1, 0, "Atomic Compare-And-Swap Instructions",
242                     [FeatureStdExtZaamo]>,
243      RISCVExtensionBitmask<0, 26>;
244def HasStdExtZacas : Predicate<"Subtarget->hasStdExtZacas()">,
245                     AssemblerPredicate<(all_of FeatureStdExtZacas),
246                         "'Zacas' (Atomic Compare-And-Swap Instructions)">;
247def NoStdExtZacas : Predicate<"!Subtarget->hasStdExtZacas()">;
248
249def FeatureStdExtZalasr
250    : RISCVExperimentalExtension<0, 1, "Load-Acquire and Store-Release Instructions">;
251def HasStdExtZalasr : Predicate<"Subtarget->hasStdExtZalasr()">,
252                      AssemblerPredicate<(all_of FeatureStdExtZalasr),
253                          "'Zalasr' (Load-Acquire and Store-Release Instructions)">;
254
255def FeatureStdExtZama16b
256    : RISCVExtension<1, 0, "Atomic 16-byte misaligned loads, stores and AMOs">;
257
258def FeatureStdExtZawrs : RISCVExtension<1, 0, "Wait on Reservation Set">;
259def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">,
260                     AssemblerPredicate<(all_of FeatureStdExtZawrs),
261                                        "'Zawrs' (Wait on Reservation Set)">;
262
263// Floating Point Extensions
264
265def FeatureStdExtF
266    : RISCVExtension<2, 2, "Single-Precision Floating-Point",
267                     [FeatureStdExtZicsr]>,
268      RISCVExtensionBitmask<0, 5>;
269def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">,
270                 AssemblerPredicate<(all_of FeatureStdExtF),
271                                    "'F' (Single-Precision Floating-Point)">;
272
273def FeatureStdExtD
274    : RISCVExtension<2, 2, "Double-Precision Floating-Point",
275                     [FeatureStdExtF]>,
276      RISCVExtensionBitmask<0, 3>;
277def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">,
278                 AssemblerPredicate<(all_of FeatureStdExtD),
279                                    "'D' (Double-Precision Floating-Point)">;
280
281def FeatureStdExtZfhmin
282    : RISCVExtension<1, 0, "Half-Precision Floating-Point Minimal",
283                     [FeatureStdExtF]>,
284      RISCVExtensionBitmask<0, 36>;
285def HasStdExtZfhmin : Predicate<"Subtarget->hasStdExtZfhmin()">,
286                      AssemblerPredicate<(all_of FeatureStdExtZfhmin),
287                          "'Zfh' (Half-Precision Floating-Point) or "
288                          "'Zfhmin' (Half-Precision Floating-Point Minimal)">;
289
290def FeatureStdExtZfh
291    : RISCVExtension<1, 0, "Half-Precision Floating-Point",
292                     [FeatureStdExtZfhmin]>,
293      RISCVExtensionBitmask<0, 35>;
294def HasStdExtZfh : Predicate<"Subtarget->hasStdExtZfh()">,
295                   AssemblerPredicate<(all_of FeatureStdExtZfh),
296                       "'Zfh' (Half-Precision Floating-Point)">;
297def NoStdExtZfh : Predicate<"!Subtarget->hasStdExtZfh()">;
298
299def FeatureStdExtZfbfmin
300    : RISCVExtension<1, 0, "Scalar BF16 Converts", [FeatureStdExtF]>;
301def HasStdExtZfbfmin : Predicate<"Subtarget->hasStdExtZfbfmin()">,
302                       AssemblerPredicate<(all_of FeatureStdExtZfbfmin),
303                                          "'Zfbfmin' (Scalar BF16 Converts)">;
304
305def HasHalfFPLoadStoreMove
306    : Predicate<"Subtarget->hasHalfFPLoadStoreMove()">,
307      AssemblerPredicate<(any_of FeatureStdExtZfh, FeatureStdExtZfhmin,
308                                 FeatureStdExtZfbfmin),
309                         "'Zfh' (Half-Precision Floating-Point) or "
310                                    "'Zfhmin' (Half-Precision Floating-Point Minimal) or "
311                                    "'Zfbfmin' (Scalar BF16 Converts)">;
312
313def FeatureStdExtZfa
314    : RISCVExtension<1, 0, "Additional Floating-Point", [FeatureStdExtF]>,
315      RISCVExtensionBitmask<0, 34>;
316def HasStdExtZfa : Predicate<"Subtarget->hasStdExtZfa()">,
317                   AssemblerPredicate<(all_of FeatureStdExtZfa),
318                                      "'Zfa' (Additional Floating-Point)">;
319def NoStdExtZfa : Predicate<"!Subtarget->hasStdExtZfa()">;
320
321def FeatureStdExtZfinx
322    : RISCVExtension<1, 0, "Float in Integer", [FeatureStdExtZicsr]>;
323def HasStdExtZfinx : Predicate<"Subtarget->hasStdExtZfinx()">,
324                     AssemblerPredicate<(all_of FeatureStdExtZfinx),
325                                        "'Zfinx' (Float in Integer)">;
326def HasStdExtFOrZfinx : Predicate<"Subtarget->hasStdExtFOrZfinx()">,
327                        AssemblerPredicate<(any_of FeatureStdExtF,
328                                                   FeatureStdExtZfinx),
329                            "'F' (Single-Precision Floating-Point) or "
330                            "'Zfinx' (Float in Integer)">;
331
332def FeatureStdExtZdinx
333    : RISCVExtension<1, 0, "Double in Integer", [FeatureStdExtZfinx]>;
334def HasStdExtZdinx : Predicate<"Subtarget->hasStdExtZdinx()">,
335                     AssemblerPredicate<(all_of FeatureStdExtZdinx),
336                                        "'Zdinx' (Double in Integer)">;
337
338def FeatureStdExtZhinxmin
339    : RISCVExtension<1, 0, "Half Float in Integer Minimal",
340                     [FeatureStdExtZfinx]>;
341def HasStdExtZhinxmin : Predicate<"Subtarget->hasStdExtZhinxmin()">,
342                        AssemblerPredicate<(all_of FeatureStdExtZhinxmin),
343                            "'Zhinx' (Half Float in Integer) or "
344                            "'Zhinxmin' (Half Float in Integer Minimal)">;
345
346def FeatureStdExtZhinx
347    : RISCVExtension<1, 0, "Half Float in Integer", [FeatureStdExtZhinxmin]>;
348def HasStdExtZhinx : Predicate<"Subtarget->hasStdExtZhinx()">,
349                     AssemblerPredicate<(all_of FeatureStdExtZhinx),
350                                        "'Zhinx' (Half Float in Integer)">;
351def NoStdExtZhinx : Predicate<"!Subtarget->hasStdExtZhinx()">;
352
353// Compressed Extensions
354
355def FeatureStdExtC
356    : RISCVExtension<2, 0, "Compressed Instructions">,
357      RISCVExtensionBitmask<0, 2>;
358def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">,
359                 AssemblerPredicate<(all_of FeatureStdExtC),
360                                    "'C' (Compressed Instructions)">;
361
362def FeatureNoRVCHints
363    : SubtargetFeature<"no-rvc-hints", "EnableRVCHintInstrs", "false",
364                       "Disable RVC Hint Instructions.">;
365def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">,
366                  AssemblerPredicate<(all_of(not FeatureNoRVCHints)),
367                                     "RVC Hint Instructions">;
368
369def FeatureStdExtZca
370    : RISCVExtension<1, 0,
371                     "part of the C extension, excluding compressed "
372                     "floating point loads/stores">;
373
374def HasStdExtCOrZca
375    : Predicate<"Subtarget->hasStdExtCOrZca()">,
376      AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZca),
377                         "'C' (Compressed Instructions) or "
378                         "'Zca' (part of the C extension, excluding "
379                         "compressed floating point loads/stores)">;
380
381def FeatureStdExtZcb
382    : RISCVExtension<1, 0, "Compressed basic bit manipulation instructions",
383                     [FeatureStdExtZca]>;
384def HasStdExtZcb : Predicate<"Subtarget->hasStdExtZcb()">,
385                   AssemblerPredicate<(all_of FeatureStdExtZcb),
386                       "'Zcb' (Compressed basic bit manipulation instructions)">;
387
388def FeatureStdExtZcd
389    : RISCVExtension<1, 0,
390                     "Compressed Double-Precision Floating-Point Instructions",
391                     [FeatureStdExtD, FeatureStdExtZca]>;
392
393def HasStdExtCOrZcd
394    : Predicate<"Subtarget->hasStdExtCOrZcd()">,
395      AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZcd),
396                         "'C' (Compressed Instructions) or "
397                         "'Zcd' (Compressed Double-Precision Floating-Point Instructions)">;
398
399def FeatureStdExtZcf
400    : RISCVExtension<1, 0,
401                     "Compressed Single-Precision Floating-Point Instructions",
402                     [FeatureStdExtF, FeatureStdExtZca]>;
403
404def FeatureStdExtZcmp
405    : RISCVExtension<1, 0,
406                     "sequenced instructions for code-size reduction",
407                     [FeatureStdExtZca]>;
408def HasStdExtZcmp : Predicate<"Subtarget->hasStdExtZcmp() && !Subtarget->hasStdExtC()">,
409                    AssemblerPredicate<(all_of FeatureStdExtZcmp),
410                        "'Zcmp' (sequenced instructions for code-size reduction)">;
411
412def FeatureStdExtZcmt
413    : RISCVExtension<1, 0,
414                     "table jump instructions for code-size reduction",
415                     [FeatureStdExtZca, FeatureStdExtZicsr]>;
416def HasStdExtZcmt : Predicate<"Subtarget->hasStdExtZcmt()">,
417                           AssemblerPredicate<(all_of FeatureStdExtZcmt),
418                           "'Zcmt' (table jump instructions for code-size reduction)">;
419
420def FeatureStdExtZce
421    : RISCVExtension<1, 0,
422                     "Compressed extensions for microcontrollers",
423                     [FeatureStdExtZcb, FeatureStdExtZcmp, FeatureStdExtZcmt]>;
424
425def HasStdExtCOrZcfOrZce
426    : Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcf() "
427                "Subtarget->hasStdExtZce()">,
428      AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZcf,
429                                 FeatureStdExtZce),
430                         "'C' (Compressed Instructions) or "
431                         "'Zcf' (Compressed Single-Precision Floating-Point Instructions)">;
432
433def FeatureStdExtZcmop
434    : RISCVExtension<1, 0, "Compressed May-Be-Operations",
435                     [FeatureStdExtZca]>;
436def HasStdExtZcmop : Predicate<"Subtarget->hasStdExtZcmop()">,
437                     AssemblerPredicate<(all_of FeatureStdExtZcmop),
438                         "'Zcmop' (Compressed May-Be-Operations)">;
439
440// Bitmanip Extensions
441
442def FeatureStdExtZba
443    : RISCVExtension<1, 0, "Address Generation Instructions">,
444      RISCVExtensionBitmask<0, 27>;
445def HasStdExtZba : Predicate<"Subtarget->hasStdExtZba()">,
446                   AssemblerPredicate<(all_of FeatureStdExtZba),
447                                      "'Zba' (Address Generation Instructions)">;
448def NotHasStdExtZba : Predicate<"!Subtarget->hasStdExtZba()">;
449
450def FeatureStdExtZbb
451    : RISCVExtension<1, 0, "Basic Bit-Manipulation">,
452      RISCVExtensionBitmask<0, 28>;
453def HasStdExtZbb : Predicate<"Subtarget->hasStdExtZbb()">,
454                   AssemblerPredicate<(all_of FeatureStdExtZbb),
455                                      "'Zbb' (Basic Bit-Manipulation)">;
456def NoStdExtZbb : Predicate<"!Subtarget->hasStdExtZbb()">,
457                  AssemblerPredicate<(all_of (not FeatureStdExtZbb))>;
458
459def FeatureStdExtZbc
460    : RISCVExtension<1, 0, "Carry-Less Multiplication">,
461      RISCVExtensionBitmask<0, 29>;
462def HasStdExtZbc : Predicate<"Subtarget->hasStdExtZbc()">,
463                   AssemblerPredicate<(all_of FeatureStdExtZbc),
464                                      "'Zbc' (Carry-Less Multiplication)">;
465
466def FeatureStdExtZbs
467    : RISCVExtension<1, 0, "Single-Bit Instructions">,
468      RISCVExtensionBitmask<0, 33>;
469def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
470                   AssemblerPredicate<(all_of FeatureStdExtZbs),
471                                      "'Zbs' (Single-Bit Instructions)">;
472
473// Bitmanip Extensions for Cryptography Extensions
474
475def FeatureStdExtB
476    : RISCVExtension<1, 0, "the collection of the Zba, Zbb, Zbs extensions",
477                     [FeatureStdExtZba, FeatureStdExtZbb, FeatureStdExtZbs]>;
478
479def FeatureStdExtZbkb
480    : RISCVExtension<1, 0, "Bitmanip instructions for Cryptography">,
481      RISCVExtensionBitmask<0, 30>;
482def HasStdExtZbkb : Predicate<"Subtarget->hasStdExtZbkb()">,
483                    AssemblerPredicate<(all_of FeatureStdExtZbkb),
484                        "'Zbkb' (Bitmanip instructions for Cryptography)">;
485def NoStdExtZbkb : Predicate<"!Subtarget->hasStdExtZbkb()">,
486                   AssemblerPredicate<(all_of (not FeatureStdExtZbkb))>;
487
488def FeatureStdExtZbkx
489    : RISCVExtension<1, 0, "Crossbar permutation instructions">,
490      RISCVExtensionBitmask<0, 32>;
491def HasStdExtZbkx : Predicate<"Subtarget->hasStdExtZbkx()">,
492                    AssemblerPredicate<(all_of FeatureStdExtZbkx),
493                        "'Zbkx' (Crossbar permutation instructions)">;
494
495def HasStdExtZbbOrZbkb
496    : Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbkb()">,
497      AssemblerPredicate<(any_of FeatureStdExtZbb, FeatureStdExtZbkb),
498                         "'Zbb' (Basic Bit-Manipulation) or "
499                         "'Zbkb' (Bitmanip instructions for Cryptography)">;
500
501// The Carry-less multiply subextension for cryptography is a subset of basic
502// carry-less multiply subextension. The former should be enabled if the latter
503// is enabled.
504def FeatureStdExtZbkc
505    : RISCVExtension<1, 0,
506                     "Carry-less multiply instructions for Cryptography">,
507      RISCVExtensionBitmask<0, 31>;
508def HasStdExtZbkc
509    : Predicate<"Subtarget->hasStdExtZbkc()">,
510      AssemblerPredicate<(all_of FeatureStdExtZbkc),
511          "'Zbkc' (Carry-less multiply instructions for Cryptography)">;
512
513def HasStdExtZbcOrZbkc
514    : Predicate<"Subtarget->hasStdExtZbc() || Subtarget->hasStdExtZbkc()">,
515      AssemblerPredicate<(any_of FeatureStdExtZbc, FeatureStdExtZbkc),
516                         "'Zbc' (Carry-Less Multiplication) or "
517                         "'Zbkc' (Carry-less multiply instructions "
518                         "for Cryptography)">;
519
520// Cryptography Extensions
521
522def FeatureStdExtZknd
523    : RISCVExtension<1, 0, "NIST Suite: AES Decryption">,
524      RISCVExtensionBitmask<0, 41>;
525def HasStdExtZknd : Predicate<"Subtarget->hasStdExtZknd()">,
526                    AssemblerPredicate<(all_of FeatureStdExtZknd),
527                                       "'Zknd' (NIST Suite: AES Decryption)">;
528
529def FeatureStdExtZkne
530    : RISCVExtension<1, 0, "NIST Suite: AES Encryption">,
531      RISCVExtensionBitmask<0, 42>;
532def HasStdExtZkne : Predicate<"Subtarget->hasStdExtZkne()">,
533                    AssemblerPredicate<(all_of FeatureStdExtZkne),
534                                       "'Zkne' (NIST Suite: AES Encryption)">;
535
536// Some instructions belong to both Zknd and Zkne subextensions.
537// They should be enabled if either has been specified.
538def HasStdExtZkndOrZkne
539    : Predicate<"Subtarget->hasStdExtZknd() || Subtarget->hasStdExtZkne()">,
540      AssemblerPredicate<(any_of FeatureStdExtZknd, FeatureStdExtZkne),
541                         "'Zknd' (NIST Suite: AES Decryption) or "
542                         "'Zkne' (NIST Suite: AES Encryption)">;
543
544def FeatureStdExtZknh
545    : RISCVExtension<1, 0, "NIST Suite: Hash Function Instructions">,
546      RISCVExtensionBitmask<0, 43>;
547def HasStdExtZknh : Predicate<"Subtarget->hasStdExtZknh()">,
548                    AssemblerPredicate<(all_of FeatureStdExtZknh),
549                        "'Zknh' (NIST Suite: Hash Function Instructions)">;
550
551def FeatureStdExtZksed
552    : RISCVExtension<1, 0, "ShangMi Suite: SM4 Block Cipher Instructions">,
553      RISCVExtensionBitmask<0, 44>;
554def HasStdExtZksed : Predicate<"Subtarget->hasStdExtZksed()">,
555                     AssemblerPredicate<(all_of FeatureStdExtZksed),
556                         "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">;
557
558def FeatureStdExtZksh
559    : RISCVExtension<1, 0, "ShangMi Suite: SM3 Hash Function Instructions">,
560      RISCVExtensionBitmask<0, 45>;
561def HasStdExtZksh : Predicate<"Subtarget->hasStdExtZksh()">,
562                    AssemblerPredicate<(all_of FeatureStdExtZksh),
563                        "'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">;
564
565def FeatureStdExtZkr
566    : RISCVExtension<1, 0, "Entropy Source Extension">;
567def HasStdExtZkr : Predicate<"Subtarget->hasStdExtZkr()">,
568                   AssemblerPredicate<(all_of FeatureStdExtZkr),
569                                      "'Zkr' (Entropy Source Extension)">;
570
571def FeatureStdExtZkn
572    : RISCVExtension<1, 0, "NIST Algorithm Suite",
573                     [FeatureStdExtZbkb,
574                      FeatureStdExtZbkc,
575                      FeatureStdExtZbkx,
576                      FeatureStdExtZkne,
577                      FeatureStdExtZknd,
578                      FeatureStdExtZknh]>;
579
580def FeatureStdExtZks
581    : RISCVExtension<1, 0, "ShangMi Algorithm Suite",
582                     [FeatureStdExtZbkb,
583                      FeatureStdExtZbkc,
584                      FeatureStdExtZbkx,
585                      FeatureStdExtZksed,
586                      FeatureStdExtZksh]>;
587
588def FeatureStdExtZkt
589    : RISCVExtension<1, 0, "Data Independent Execution Latency">,
590      RISCVExtensionBitmask<0, 46>;
591
592def FeatureStdExtZk
593    : RISCVExtension<1, 0, "Standard scalar cryptography extension",
594                     [FeatureStdExtZkn,
595                      FeatureStdExtZkr,
596                      FeatureStdExtZkt]>;
597
598// Vector Extensions
599
600def FeatureStdExtZvl32b : RISCVExtension<1, 0,
601                                         "Minimum Vector Length 32", [],
602                                         "ZvlLen", "32">;
603
604foreach i = { 6-16 } in {
605  defvar I = !shl(1, i);
606  def FeatureStdExtZvl#I#b :
607      RISCVExtension<1, 0, "Minimum Vector Length "#I,
608                     [!cast<RISCVExtension>("FeatureStdExtZvl"#!srl(I, 1)#"b")],
609                     "ZvlLen", !cast<string>(I)>;
610}
611
612def FeatureStdExtZve32x
613    : RISCVExtension<1, 0,
614                     "Vector Extensions for Embedded Processors "
615                     "with maximal 32 EEW",
616                     [FeatureStdExtZicsr, FeatureStdExtZvl32b]>;
617
618
619def FeatureStdExtZve32f
620    : RISCVExtension<1, 0,
621                     "Vector Extensions for Embedded Processors "
622                     "with maximal 32 EEW and F extension",
623                     [FeatureStdExtZve32x, FeatureStdExtF]>;
624
625def FeatureStdExtZve64x
626    : RISCVExtension<1, 0,
627                     "Vector Extensions for Embedded Processors "
628                     "with maximal 64 EEW",
629                     [FeatureStdExtZve32x, FeatureStdExtZvl64b]>;
630
631def FeatureStdExtZve64f
632    : RISCVExtension<1, 0,
633                     "Vector Extensions for Embedded Processors "
634                     "with maximal 64 EEW and F extension",
635                     [FeatureStdExtZve32f, FeatureStdExtZve64x]>;
636
637def FeatureStdExtZve64d
638    : RISCVExtension<1, 0,
639                     "Vector Extensions for Embedded Processors "
640                     "with maximal 64 EEW, F and D extension",
641                     [FeatureStdExtZve64f, FeatureStdExtD]>;
642
643def FeatureStdExtV
644    : RISCVExtension<1, 0,
645                     "Vector Extension for Application Processors",
646                     [FeatureStdExtZvl128b, FeatureStdExtZve64d]>,
647      RISCVExtensionBitmask<0, 21>;
648
649def FeatureStdExtZvfbfmin
650    : RISCVExtension<1, 0, "Vector BF16 Converts", [FeatureStdExtZve32f]>;
651def HasStdExtZvfbfmin : Predicate<"Subtarget->hasStdExtZvfbfmin()">,
652                        AssemblerPredicate<(all_of FeatureStdExtZvfbfmin),
653                            "'Zvfbfmin' (Vector BF16 Converts)">;
654
655def FeatureStdExtZvfbfwma
656    : RISCVExtension<1, 0, "Vector BF16 widening mul-add",
657                     [FeatureStdExtZvfbfmin, FeatureStdExtZfbfmin]>;
658def HasStdExtZvfbfwma : Predicate<"Subtarget->hasStdExtZvfbfwma()">,
659                        AssemblerPredicate<(all_of FeatureStdExtZvfbfwma),
660                            "'Zvfbfwma' (Vector BF16 widening mul-add)">;
661
662def FeatureStdExtZvfhmin
663    : RISCVExtension<1, 0,
664                     "Vector Half-Precision Floating-Point Minimal",
665                     [FeatureStdExtZve32f]>,
666      RISCVExtensionBitmask<0, 51>;
667
668def FeatureStdExtZvfh
669    : RISCVExtension<1, 0, "Vector Half-Precision Floating-Point",
670                     [FeatureStdExtZvfhmin, FeatureStdExtZfhmin]>,
671      RISCVExtensionBitmask<0, 50>;
672
673def HasStdExtZfhOrZvfh
674    : Predicate<"Subtarget->hasStdExtZfh() || Subtarget->hasStdExtZvfh()">,
675      AssemblerPredicate<(any_of FeatureStdExtZfh, FeatureStdExtZvfh),
676                         "'Zfh' (Half-Precision Floating-Point) or "
677                         "'Zvfh' (Vector Half-Precision Floating-Point)">;
678
679// Vector Cryptography and Bitmanip Extensions
680
681def FeatureStdExtZvkb
682    : RISCVExtension<1, 0, "Vector Bit-manipulation used in Cryptography",
683                     [FeatureStdExtZve32x]>,
684      RISCVExtensionBitmask<0, 52>;
685def HasStdExtZvkb : Predicate<"Subtarget->hasStdExtZvkb()">,
686                    AssemblerPredicate<(all_of FeatureStdExtZvkb),
687                        "'Zvkb' (Vector Bit-manipulation used in Cryptography)">;
688
689def FeatureStdExtZvbb
690    : RISCVExtension<1, 0, "Vector basic bit-manipulation instructions",
691                     [FeatureStdExtZvkb]>,
692      RISCVExtensionBitmask<0, 48>;
693def HasStdExtZvbb : Predicate<"Subtarget->hasStdExtZvbb()">,
694                    AssemblerPredicate<(all_of FeatureStdExtZvbb),
695                        "'Zvbb' (Vector basic bit-manipulation instructions)">;
696
697def FeatureStdExtZvbc
698    : RISCVExtension<1, 0, "Vector Carryless Multiplication",
699                     [FeatureStdExtZve64x]>,
700      RISCVExtensionBitmask<0, 49>;
701def HasStdExtZvbc : Predicate<"Subtarget->hasStdExtZvbc()">,
702                    AssemblerPredicate<(all_of FeatureStdExtZvbc),
703                        "'Zvbc' (Vector Carryless Multiplication)">;
704
705def FeatureStdExtZvbc32e
706    : RISCVExperimentalExtension<0, 7,
707                                 "Vector Carryless Multiplication with 32-bits elements",
708                                 [FeatureStdExtZve32x]>;
709
710def HasStdExtZvbcOrZvbc32e : Predicate<"Subtarget->hasStdExtZvbc() || Subtarget->hasStdExtZvbc32e()">,
711                             AssemblerPredicate<(any_of FeatureStdExtZvbc, FeatureStdExtZvbc32e),
712                             "'Zvbc' or 'Zvbc32e' (Vector Carryless Multiplication)">;
713
714def FeatureStdExtZvkg
715    : RISCVExtension<1, 0, "Vector GCM instructions for Cryptography",
716                     [FeatureStdExtZve32x]>,
717      RISCVExtensionBitmask<0, 53>;
718def HasStdExtZvkg : Predicate<"Subtarget->hasStdExtZvkg()">,
719                    AssemblerPredicate<(all_of FeatureStdExtZvkg),
720                        "'Zvkg' (Vector GCM instructions for Cryptography)">;
721
722def FeatureStdExtZvkgs
723    : RISCVExperimentalExtension<0, 7,
724                                 "Vector-Scalar GCM instructions for Cryptography",
725                                 [FeatureStdExtZvkg]>;
726def HasStdExtZvkgs : Predicate<"Subtarget->hasStdExtZvkgs()">,
727                     AssemblerPredicate<(all_of FeatureStdExtZvkgs),
728                        "'Zvkgs' (Vector-Scalar GCM instructions for Cryptography)">;
729
730def FeatureStdExtZvkned
731    : RISCVExtension<1, 0,
732                     "Vector AES Encryption & Decryption (Single Round)",
733                     [FeatureStdExtZve32x]>,
734      RISCVExtensionBitmask<0, 54>;
735def HasStdExtZvkned : Predicate<"Subtarget->hasStdExtZvkned()">,
736                      AssemblerPredicate<(all_of FeatureStdExtZvkned),
737                          "'Zvkned' (Vector AES Encryption & Decryption (Single Round))">;
738
739def FeatureStdExtZvknha
740    : RISCVExtension<1, 0, "Vector SHA-2 (SHA-256 only)",
741                     [FeatureStdExtZve32x]>,
742      RISCVExtensionBitmask<0, 55>;
743def HasStdExtZvknha : Predicate<"Subtarget->hasStdExtZvknha()">,
744                      AssemblerPredicate<(all_of FeatureStdExtZvknha),
745                          "'Zvknha' (Vector SHA-2 (SHA-256 only))">;
746
747def FeatureStdExtZvknhb
748    : RISCVExtension<1, 0, "Vector SHA-2 (SHA-256 and SHA-512)",
749                     [FeatureStdExtZve64x]>,
750      RISCVExtensionBitmask<0, 56>;
751def HasStdExtZvknhb : Predicate<"Subtarget->hasStdExtZvknhb()">,
752                      AssemblerPredicate<(all_of FeatureStdExtZvknhb),
753                          "'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))">;
754
755def HasStdExtZvknhaOrZvknhb : Predicate<"Subtarget->hasStdExtZvknha() || Subtarget->hasStdExtZvknhb()">,
756                              AssemblerPredicate<(any_of FeatureStdExtZvknha, FeatureStdExtZvknhb),
757                                  "'Zvknha' or 'Zvknhb' (Vector SHA-2)">;
758
759def FeatureStdExtZvksed
760    : RISCVExtension<1, 0, "SM4 Block Cipher Instructions",
761                     [FeatureStdExtZve32x]>,
762      RISCVExtensionBitmask<0, 57>;
763def HasStdExtZvksed : Predicate<"Subtarget->hasStdExtZvksed()">,
764                      AssemblerPredicate<(all_of FeatureStdExtZvksed),
765                          "'Zvksed' (SM4 Block Cipher Instructions)">;
766
767def FeatureStdExtZvksh
768    : RISCVExtension<1, 0, "SM3 Hash Function Instructions",
769                     [FeatureStdExtZve32x]>,
770      RISCVExtensionBitmask<0, 58>;
771def HasStdExtZvksh : Predicate<"Subtarget->hasStdExtZvksh()">,
772                     AssemblerPredicate<(all_of FeatureStdExtZvksh),
773                         "'Zvksh' (SM3 Hash Function Instructions)">;
774
775def FeatureStdExtZvkt
776    : RISCVExtension<1, 0, "Vector Data-Independent Execution Latency">,
777      RISCVExtensionBitmask<0, 59>;
778
779// Zvk short-hand extensions
780
781def FeatureStdExtZvkn
782    : RISCVExtension<1, 0,
783                     "shorthand for 'Zvkned', 'Zvknhb', 'Zvkb', and 'Zvkt'",
784                     [FeatureStdExtZvkned, FeatureStdExtZvknhb,
785                      FeatureStdExtZvkb, FeatureStdExtZvkt]>;
786
787def FeatureStdExtZvknc
788    : RISCVExtension<1, 0, "shorthand for 'Zvknc' and 'Zvbc'",
789                     [FeatureStdExtZvkn, FeatureStdExtZvbc]>;
790
791def FeatureStdExtZvkng
792    : RISCVExtension<1, 0, "shorthand for 'Zvkn' and 'Zvkg'",
793                     [FeatureStdExtZvkn, FeatureStdExtZvkg]>;
794
795def FeatureStdExtZvks
796    : RISCVExtension<1, 0,
797                     "shorthand for 'Zvksed', 'Zvksh', 'Zvkb', and 'Zvkt'",
798                     [FeatureStdExtZvksed, FeatureStdExtZvksh,
799                      FeatureStdExtZvkb, FeatureStdExtZvkt]>;
800
801def FeatureStdExtZvksc
802    : RISCVExtension<1, 0, "shorthand for 'Zvks' and 'Zvbc'",
803                     [FeatureStdExtZvks, FeatureStdExtZvbc]>;
804
805def FeatureStdExtZvksg
806    : RISCVExtension<1, 0, "shorthand for 'Zvks' and 'Zvkg'",
807                     [FeatureStdExtZvks, FeatureStdExtZvkg]>;
808// Vector instruction predicates
809
810def HasVInstructions    : Predicate<"Subtarget->hasVInstructions()">,
811      AssemblerPredicate<
812          (any_of FeatureStdExtZve32x),
813          "'V' (Vector Extension for Application Processors), 'Zve32x' "
814          "(Vector Extensions for Embedded Processors)">;
815def HasVInstructionsI64 : Predicate<"Subtarget->hasVInstructionsI64()">,
816      AssemblerPredicate<
817          (any_of FeatureStdExtZve64x),
818          "'V' (Vector Extension for Application Processors) or 'Zve64x' "
819          "(Vector Extensions for Embedded Processors)">;
820def HasVInstructionsAnyF : Predicate<"Subtarget->hasVInstructionsAnyF()">,
821      AssemblerPredicate<
822          (any_of FeatureStdExtZve32f),
823          "'V' (Vector Extension for Application Processors), 'Zve32f' "
824          "(Vector Extensions for Embedded Processors)">;
825
826def HasVInstructionsF16Minimal : Predicate<"Subtarget->hasVInstructionsF16Minimal()">,
827      AssemblerPredicate<(any_of FeatureStdExtZvfhmin, FeatureStdExtZvfh),
828                         "'Zvfhmin' (Vector Half-Precision Floating-Point Minimal) or "
829                         "'Zvfh' (Vector Half-Precision Floating-Point)">;
830
831def HasVInstructionsBF16Minimal : Predicate<"Subtarget->hasVInstructionsBF16Minimal()">;
832def HasVInstructionsF16 : Predicate<"Subtarget->hasVInstructionsF16()">;
833def HasVInstructionsF64 : Predicate<"Subtarget->hasVInstructionsF64()">;
834
835def HasVInstructionsFullMultiply : Predicate<"Subtarget->hasVInstructionsFullMultiply()">;
836
837// Hypervisor Extensions
838
839def FeatureStdExtH : RISCVExtension<1, 0, "Hypervisor">;
840
841def HasStdExtH : Predicate<"Subtarget->hasStdExtH()">,
842                 AssemblerPredicate<(all_of FeatureStdExtH),
843                                    "'H' (Hypervisor)">;
844
845// Supervisor extensions
846
847def FeatureStdExtSdext : RISCVExperimentalExtension<1, 0, "External debugger">;
848
849def FeatureStdExtSdtrig : RISCVExperimentalExtension<1, 0, "Debugger triggers">;
850
851def FeatureStdExtShgatpa
852    : RISCVExtension<1, 0,
853                     "SvNNx4 mode supported for all modes supported by satp, as well as Bare">;
854def FeatureStdExtShvsatpa
855    : RISCVExtension<1, 0,
856                     "vsatp supports all modes supported by satp">;
857
858def FeatureStdExtSmaia
859    : RISCVExtension<1, 0,
860                     "Advanced Interrupt Architecture Machine Level">;
861def FeatureStdExtSsaia
862    : RISCVExtension<1, 0,
863                     "Advanced Interrupt Architecture Supervisor Level">;
864
865def FeatureStdExtSmcsrind
866    : RISCVExtension<1, 0, "Indirect CSR Access Machine Level">;
867def FeatureStdExtSscsrind
868    : RISCVExtension<1, 0, "Indirect CSR Access Supervisor Level">;
869
870def FeatureStdExtSmdbltrp
871    : RISCVExtension<1, 0, "Double Trap Machine Level">;
872def FeatureStdExtSsdbltrp
873    : RISCVExtension<1, 0, "Double Trap Supervisor Level">;
874
875def FeatureStdExtSmepmp
876    : RISCVExtension<1, 0, "Enhanced Physical Memory Protection">;
877
878def FeatureStdExtSmrnmi
879    : RISCVExtension<1, 0, "Resumable Non-Maskable Interrupts">;
880def HasStdExtSmrnmi : Predicate<"Subtarget->hasStdExtSmrnmi()">,
881                       AssemblerPredicate<(all_of FeatureStdExtSmrnmi),
882                           "'Smrnmi' (Resumable Non-Maskable Interrupts)">;
883
884def FeatureStdExtSmcdeleg
885    : RISCVExtension<1, 0, "Counter Delegation Machine Level">;
886def FeatureStdExtSsccfg
887    : RISCVExtension<1, 0, "Counter Configuration Supervisor Level">;
888
889def FeatureStdExtSsccptr
890    : RISCVExtension<1, 0, "Main memory supports page table reads">;
891
892def FeatureStdExtSscofpmf
893    : RISCVExtension<1, 0, "Count Overflow and Mode-Based Filtering">;
894
895def FeatureStdExtShcounterenw
896    : RISCVExtension<1, 0,
897                     "Support writeable hcounteren enable "
898                     "bit for any hpmcounter that is not read-only zero">;
899def FeatureStdExtSscounterenw
900    : RISCVExtension<1, 0,
901                     "Support writeable scounteren enable "
902                     "bit for any hpmcounter that is not read-only zero">;
903
904def FeatureStdExtSmstateen
905    : RISCVExtension<1, 0,
906                     "Machine-mode view of the state-enable extension">;
907def FeatureStdExtSsstateen
908    : RISCVExtension<1, 0,
909                     "Supervisor-mode view of the state-enable extension">;
910
911def FeatureStdExtSsstrict
912    : RISCVExtension<1, 0,
913                     "No non-conforming extensions are present">;
914
915def FeatureStdExtSstc
916    : RISCVExtension<1, 0, "Supervisor-mode timer interrupts">;
917
918def FeatureStdExtSsqosid
919    : RISCVExtension<1, 0, "Quality-of-Service (QoS) Identifiers">;
920
921def FeatureStdExtShtvala
922    : RISCVExtension<1, 0, "htval provides all needed values">;
923def FeatureStdExtShvstvala
924    : RISCVExtension<1, 0, "vstval provides all needed values">;
925def FeatureStdExtSstvala
926    : RISCVExtension<1, 0, "stval provides all needed values">;
927
928def FeatureStdExtShvstvecd
929    : RISCVExtension<1, 0, "vstvec supports Direct mode">;
930def FeatureStdExtSstvecd
931    : RISCVExtension<1, 0, "stvec supports Direct mode">;
932
933def FeatureStdExtSsu64xl
934    : RISCVExtension<1, 0, "UXLEN=64 supported">;
935
936def FeatureStdExtSvade
937    : RISCVExtension<1, 0, "Raise exceptions on improper A/D bits">;
938
939def FeatureStdExtSvadu
940    : RISCVExtension<1, 0, "Hardware A/D updates">;
941
942def FeatureStdExtSvbare
943    : RISCVExtension<1, 0, "satp mode Bare supported">;
944
945def FeatureStdExtSvinval
946    : RISCVExtension<1, 0,
947                     "Fine-Grained Address-Translation Cache Invalidation">;
948def HasStdExtSvinval : Predicate<"Subtarget->hasStdExtSvinval()">,
949                       AssemblerPredicate<(all_of FeatureStdExtSvinval),
950                           "'Svinval' (Fine-Grained Address-Translation Cache Invalidation)">;
951
952def FeatureStdExtSvnapot
953    : RISCVExtension<1, 0, "NAPOT Translation Contiguity">;
954
955def FeatureStdExtSvpbmt
956    : RISCVExtension<1, 0, "Page-Based Memory Types">;
957
958def FeatureStdExtSvvptc
959    : RISCVExtension<1, 0,
960                     "Obviating Memory-Management Instructions after Marking PTEs Valid">;
961
962def FeatureStdExtSha
963    : RISCVExtension<1, 0, "Augmented Hypervisor",
964                     [FeatureStdExtH, FeatureStdExtSsstateen, FeatureStdExtShcounterenw,
965                      FeatureStdExtShvstvala, FeatureStdExtShtvala, FeatureStdExtShvstvecd,
966                      FeatureStdExtShvsatpa, FeatureStdExtShgatpa]>;
967
968def FeatureStdExtSvukte
969    : RISCVExperimentalExtension<0, 3,
970                                 "Address-Independent Latency of User-Mode Faults to Supervisor Addresses">;
971
972// Pointer Masking extensions
973
974// A supervisor-level extension that provides pointer masking for the next lower
975// privilege mode (U-mode), and for VS- and VU-modes if the H extension is
976// present.
977def FeatureStdExtSsnpm
978    : RISCVExtension<1, 0,
979                     "Supervisor-level Pointer Masking for next lower privilege mode">;
980
981// A machine-level extension that provides pointer masking for the next lower
982// privilege mode (S/HS if S-mode is implemented, or U-mode otherwise).
983def FeatureStdExtSmnpm
984    : RISCVExtension<1, 0,
985                     "Machine-level Pointer Masking for next lower privilege mode">;
986
987// A machine-level extension that provides pointer masking for M-mode.
988def FeatureStdExtSmmpm
989    : RISCVExtension<1, 0,
990                     "Machine-level Pointer Masking for M-mode">;
991
992// An extension that indicates that there is pointer-masking support available
993// in supervisor mode, with some facility provided in the supervisor execution
994// environment to control pointer masking.
995def FeatureStdExtSspm
996    : RISCVExtension<1, 0,
997                     "Indicates Supervisor-mode Pointer Masking">;
998
999// An extension that indicates that there is pointer-masking support available
1000// in user mode, with some facility provided in the application execution
1001// environment to control pointer masking.
1002def FeatureStdExtSupm
1003    : RISCVExtension<1, 0,
1004                     "Indicates User-mode Pointer Masking">;
1005
1006def FeatureStdExtSmctr
1007    : RISCVExperimentalExtension<1, 0,
1008                                 "Control Transfer Records Machine Level",
1009                                 [FeatureStdExtSscsrind]>;
1010def FeatureStdExtSsctr
1011    : RISCVExperimentalExtension<1, 0,
1012                                 "Control Transfer Records Supervisor Level",
1013                                 [FeatureStdExtSscsrind]>;
1014def HasStdExtSmctrOrSsctr : Predicate<"Subtarget->hasStdExtSmctrOrSsctr()">,
1015                            AssemblerPredicate<(any_of FeatureStdExtSmctr, FeatureStdExtSsctr),
1016                               "'Smctr' (Control Transfer Records Machine Level) or "
1017                               "'Ssctr' (Control Transfer Records Supervisor Level)">;
1018
1019//===----------------------------------------------------------------------===//
1020// Vendor extensions
1021//===----------------------------------------------------------------------===//
1022
1023// Ventana Extenions
1024
1025def FeatureVendorXVentanaCondOps
1026    : RISCVExtension<1, 0, "Ventana Conditional Ops">;
1027def HasVendorXVentanaCondOps : Predicate<"Subtarget->hasVendorXVentanaCondOps()">,
1028                               AssemblerPredicate<(all_of FeatureVendorXVentanaCondOps),
1029                                   "'XVentanaCondOps' (Ventana Conditional Ops)">;
1030
1031// T-Head Extensions
1032
1033def FeatureVendorXTHeadBa
1034    : RISCVExtension<1, 0,
1035                     "T-Head address calculation instructions">;
1036def HasVendorXTHeadBa : Predicate<"Subtarget->hasVendorXTHeadBa()">,
1037                        AssemblerPredicate<(all_of FeatureVendorXTHeadBa),
1038                            "'XTHeadBa' (T-Head address calculation instructions)">;
1039
1040def FeatureVendorXTHeadBb
1041    : RISCVExtension<1, 0,
1042                     "T-Head basic bit-manipulation instructions">;
1043def HasVendorXTHeadBb : Predicate<"Subtarget->hasVendorXTHeadBb()">,
1044                        AssemblerPredicate<(all_of FeatureVendorXTHeadBb),
1045                            "'XTHeadBb' (T-Head basic bit-manipulation instructions)">;
1046
1047def FeatureVendorXTHeadBs
1048    : RISCVExtension<1, 0,
1049                     "T-Head single-bit instructions">;
1050def HasVendorXTHeadBs : Predicate<"Subtarget->hasVendorXTHeadBs()">,
1051                        AssemblerPredicate<(all_of FeatureVendorXTHeadBs),
1052                            "'XTHeadBs' (T-Head single-bit instructions)">;
1053
1054def FeatureVendorXTHeadCondMov
1055    : RISCVExtension<1, 0,
1056                     "T-Head conditional move instructions">;
1057def HasVendorXTHeadCondMov : Predicate<"Subtarget->hasVendorXTHeadCondMov()">,
1058                             AssemblerPredicate<(all_of FeatureVendorXTHeadCondMov),
1059                                 "'XTHeadCondMov' (T-Head conditional move instructions)">;
1060
1061def FeatureVendorXTHeadCmo
1062    : RISCVExtension<1, 0,
1063                     "T-Head cache management instructions">;
1064def HasVendorXTHeadCmo : Predicate<"Subtarget->hasVendorXTHeadCmo()">,
1065                         AssemblerPredicate<(all_of FeatureVendorXTHeadCmo),
1066                             "'XTHeadCmo' (T-Head cache management instructions)">;
1067
1068def FeatureVendorXTHeadFMemIdx
1069    : RISCVExtension<1, 0,
1070                     "T-Head FP Indexed Memory Operations">;
1071def HasVendorXTHeadFMemIdx : Predicate<"Subtarget->hasVendorXTHeadFMemIdx()">,
1072                             AssemblerPredicate<(all_of FeatureVendorXTHeadFMemIdx),
1073                                 "'XTHeadFMemIdx' (T-Head FP Indexed Memory Operations)">;
1074
1075def FeatureVendorXTHeadMac
1076    : RISCVExtension<1, 0,
1077                     "T-Head Multiply-Accumulate Instructions">;
1078def HasVendorXTHeadMac : Predicate<"Subtarget->hasVendorXTHeadMac()">,
1079                         AssemblerPredicate<(all_of FeatureVendorXTHeadMac),
1080                             "'XTHeadMac' (T-Head Multiply-Accumulate Instructions)">;
1081
1082def FeatureVendorXTHeadMemIdx
1083    : RISCVExtension<1, 0,
1084                     "T-Head Indexed Memory Operations">;
1085def HasVendorXTHeadMemIdx : Predicate<"Subtarget->hasVendorXTHeadMemIdx()">,
1086                            AssemblerPredicate<(all_of FeatureVendorXTHeadMemIdx),
1087                                "'XTHeadMemIdx' (T-Head Indexed Memory Operations)">;
1088
1089def FeatureVendorXTHeadMemPair
1090    : RISCVExtension<1, 0,
1091                     "T-Head two-GPR Memory Operations">;
1092def HasVendorXTHeadMemPair : Predicate<"Subtarget->hasVendorXTHeadMemPair()">,
1093                             AssemblerPredicate<(all_of FeatureVendorXTHeadMemPair),
1094                                 "'XTHeadMemPair' (T-Head two-GPR Memory Operations)">;
1095
1096def FeatureVendorXTHeadSync
1097    : RISCVExtension<1, 0,
1098                     "T-Head multicore synchronization instructions">;
1099def HasVendorXTHeadSync : Predicate<"Subtarget->hasVendorXTHeadSync()">,
1100                          AssemblerPredicate<(all_of FeatureVendorXTHeadSync),
1101                              "'XTHeadSync' (T-Head multicore synchronization instructions)">;
1102
1103def FeatureVendorXTHeadVdot
1104    : RISCVExtension<1, 0,
1105                     "T-Head Vector Extensions for Dot",
1106                     [FeatureStdExtV]>;
1107def HasVendorXTHeadVdot : Predicate<"Subtarget->hasVendorXTHeadVdot()">,
1108                          AssemblerPredicate<(all_of FeatureVendorXTHeadVdot),
1109                              "'XTHeadVdot' (T-Head Vector Extensions for Dot)">;
1110
1111// SiFive Extensions
1112
1113def FeatureVendorXSfvcp
1114    : RISCVExtension<1, 0,
1115                     "SiFive Custom Vector Coprocessor Interface Instructions",
1116                     [FeatureStdExtZve32x]>;
1117def HasVendorXSfvcp : Predicate<"Subtarget->hasVendorXSfvcp()">,
1118                      AssemblerPredicate<(all_of FeatureVendorXSfvcp),
1119                          "'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions)">;
1120
1121def FeatureVendorXSfvqmaccdod
1122    : RISCVExtension<1, 0,
1123                     "SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2)",
1124                     [FeatureStdExtZve32x]>;
1125def HasVendorXSfvqmaccdod
1126    : Predicate<"Subtarget->hasVendorXSfvqmaccdod()">,
1127      AssemblerPredicate<(all_of FeatureVendorXSfvqmaccdod),
1128                         "'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2))">;
1129
1130def FeatureVendorXSfvqmaccqoq
1131    : RISCVExtension<1, 0,
1132                     "SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4)",
1133                     [FeatureStdExtZve32x]>;
1134def HasVendorXSfvqmaccqoq
1135    : Predicate<"Subtarget->hasVendorXSfvqmaccqoq()">,
1136      AssemblerPredicate<(all_of FeatureVendorXSfvqmaccqoq),
1137                         "'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4))">;
1138
1139def FeatureVendorXSfvfwmaccqqq
1140    : RISCVExtension<1, 0,
1141                     "SiFive Matrix Multiply Accumulate Instruction and 4-by-4)",
1142                     [FeatureStdExtZvfbfmin]>;
1143def HasVendorXSfvfwmaccqqq
1144    : Predicate<"Subtarget->hasVendorXSfvfwmaccqqq()">,
1145      AssemblerPredicate<(all_of FeatureVendorXSfvfwmaccqqq),
1146                         "'XSfvfwmaccqqq' (SiFive Matrix Multiply Accumulate Instruction and 4-by-4))">;
1147
1148def FeatureVendorXSfvfnrclipxfqf
1149    : RISCVExtension<1, 0,
1150                     "SiFive FP32-to-int8 Ranged Clip Instructions",
1151                     [FeatureStdExtZve32f]>;
1152def HasVendorXSfvfnrclipxfqf
1153    : Predicate<"Subtarget->hasVendorXSfvfnrclipxfqf()">,
1154      AssemblerPredicate<(all_of FeatureVendorXSfvfnrclipxfqf),
1155                         "'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions)">;
1156
1157def FeatureVendorXSiFivecdiscarddlone
1158    : RISCVExtension<1, 0,
1159                     "SiFive sf.cdiscard.d.l1 Instruction", []>;
1160def HasVendorXSiFivecdiscarddlone
1161    : Predicate<"Subtarget->hasVendorXSiFivecdiscarddlone()">,
1162      AssemblerPredicate<(all_of FeatureVendorXSiFivecdiscarddlone),
1163                         "'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction)">;
1164
1165def FeatureVendorXSiFivecflushdlone
1166    : RISCVExtension<1, 0,
1167                     "SiFive sf.cflush.d.l1 Instruction", []>;
1168def HasVendorXSiFivecflushdlone
1169    : Predicate<"Subtarget->hasVendorXSiFivecflushdlone()">,
1170      AssemblerPredicate<(all_of FeatureVendorXSiFivecflushdlone),
1171                         "'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction)">;
1172
1173def FeatureVendorXSfcease
1174    : RISCVExtension<1, 0,
1175                     "SiFive sf.cease Instruction", []>;
1176def HasVendorXSfcease
1177    : Predicate<"Subtarget->hasVendorXSfcease()">,
1178      AssemblerPredicate<(all_of FeatureVendorXSfcease),
1179                         "'XSfcease' (SiFive sf.cease Instruction)">;
1180
1181// Core-V Extensions
1182
1183def FeatureVendorXCVelw
1184   : RISCVExtension<1, 0, "CORE-V Event Load Word">;
1185def HasVendorXCVelw
1186   : Predicate<"Subtarget->hasVendorXCVelw()">,
1187     AssemblerPredicate<(any_of FeatureVendorXCVelw),
1188                        "'XCVelw' (CORE-V Event Load Word)">;
1189
1190def FeatureVendorXCVbitmanip
1191    : RISCVExtension<1, 0, "CORE-V Bit Manipulation">;
1192def HasVendorXCVbitmanip
1193    : Predicate<"Subtarget->hasVendorXCVbitmanip()">,
1194      AssemblerPredicate<(all_of FeatureVendorXCVbitmanip),
1195                         "'XCVbitmanip' (CORE-V Bit Manipulation)">;
1196
1197def FeatureVendorXCVmac
1198    : RISCVExtension<1, 0, "CORE-V Multiply-Accumulate">;
1199def HasVendorXCVmac
1200    : Predicate<"Subtarget->hasVendorXCVmac()">,
1201      AssemblerPredicate<(all_of FeatureVendorXCVmac),
1202                         "'XCVmac' (CORE-V Multiply-Accumulate)">;
1203
1204def FeatureVendorXCVmem
1205    : RISCVExtension<1, 0, "CORE-V Post-incrementing Load & Store">;
1206def HasVendorXCVmem
1207    : Predicate<"Subtarget->hasVendorXCVmem()">,
1208      AssemblerPredicate<(any_of FeatureVendorXCVmem),
1209                         "'XCVmem' (CORE-V Post-incrementing Load & Store)">;
1210
1211def FeatureVendorXCValu
1212    : RISCVExtension<1, 0, "CORE-V ALU Operations">;
1213def HasVendorXCValu
1214    : Predicate<"Subtarget->hasVendorXCValu()">,
1215      AssemblerPredicate<(all_of FeatureVendorXCValu),
1216                         "'XCValu' (CORE-V ALU Operations)">;
1217
1218def FeatureVendorXCVsimd
1219    : RISCVExtension<1, 0, "CORE-V SIMD ALU">;
1220def HasVendorXCVsimd
1221    : Predicate<"Subtarget->hasVendorXCVsimd()">,
1222      AssemblerPredicate<(any_of FeatureVendorXCVsimd),
1223                         "'XCVsimd' (CORE-V SIMD ALU)">;
1224
1225def FeatureVendorXCVbi
1226    : RISCVExtension<1, 0, "CORE-V Immediate Branching">;
1227def HasVendorXCVbi
1228    : Predicate<"Subtarget->hasVendorXCVbi()">,
1229      AssemblerPredicate<(all_of FeatureVendorXCVbi),
1230                         "'XCVbi' (CORE-V Immediate Branching)">;
1231// MIPS Extensions
1232
1233def FeatureVendorXMIPSCMove
1234    : RISCVExtension<1, 0, "MIPS conditional move instruction(s) (ccmov)">;
1235def HasVendorXMIPSCMove
1236    : Predicate<"Subtarget->hasVendorXMIPSCMove()">,
1237      AssemblerPredicate<(all_of FeatureVendorXMIPSCMove),
1238                         "'Xmipscmove' ('mips.ccmov' instruction)">;
1239def UseCCMovInsn : Predicate<"Subtarget->useCCMovInsn()">;
1240def FeatureVendorXMIPSLSP
1241    : RISCVExtension<1, 0, "MIPS optimization for hardware load-store bonding">;
1242def HasVendorXMIPSLSP
1243    : Predicate<"Subtarget->hasVendorXMIPSLSP()">,
1244      AssemblerPredicate<(all_of FeatureVendorXMIPSLSP),
1245                         "'Xmipslsp' (load and store pair instructions)">;
1246
1247// WCH / Nanjing Qinheng Microelectronics Extension(s)
1248
1249def FeatureVendorXwchc
1250    : RISCVExtension<2, 2,
1251                     "WCH/QingKe additional compressed opcodes">;
1252def HasVendorXwchc
1253    : Predicate<"Subtarget->hasVendorXwchc()">,
1254      AssemblerPredicate<(all_of FeatureVendorXwchc),
1255                         "'Xwchc' (WCH/QingKe additional compressed opcodes)">;
1256
1257// Qualcomm Extension(s)
1258
1259def FeatureVendorXqcicsr
1260    : RISCVExperimentalExtension<0, 2, "Qualcomm uC CSR Extension">;
1261def HasVendorXqcicsr
1262    : Predicate<"Subtarget->hasVendorXqcicsr()">,
1263      AssemblerPredicate<(all_of FeatureVendorXqcicsr),
1264                         "'Xqcicsr' (Qualcomm uC CSR Extension)">;
1265
1266def FeatureVendorXqcisls
1267    : RISCVExperimentalExtension<0, 2,
1268                                 "Qualcomm uC Scaled Load Store Extension">;
1269def HasVendorXqcisls
1270    : Predicate<"Subtarget->hasVendorXqcisls()">,
1271      AssemblerPredicate<(all_of FeatureVendorXqcisls),
1272                         "'Xqcisls' (Qualcomm uC Scaled Load Store Extension)">;
1273
1274def FeatureVendorXqcia
1275    : RISCVExperimentalExtension<0, 2, "Qualcomm uC Arithmetic Extension">;
1276def HasVendorXqcia
1277    : Predicate<"Subtarget->hasVendorXqcia()">,
1278      AssemblerPredicate<(all_of FeatureVendorXqcia),
1279                         "'Xqcia' (Qualcomm uC Arithmetic Extension)">;
1280
1281def FeatureVendorXqcics
1282    : RISCVExperimentalExtension<0, 2, "Qualcomm uC Conditional Select Extension">;
1283def HasVendorXqcics
1284    : Predicate<"Subtarget->hasVendorXqcics()">,
1285      AssemblerPredicate<(all_of FeatureVendorXqcics),
1286                         "'Xqcics' (Qualcomm uC Conditional Select Extension)">;
1287
1288def FeatureVendorXqcilsm
1289    : RISCVExperimentalExtension<0, 2,
1290                                 "Qualcomm uC Load Store Multiple Extension">;
1291def HasVendorXqcilsm
1292    : Predicate<"Subtarget->hasVendorXqcilsm()">,
1293      AssemblerPredicate<(all_of FeatureVendorXqcilsm),
1294                         "'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)">;
1295
1296def FeatureVendorXqciac
1297    : RISCVExperimentalExtension<0, 3, "Qualcomm uC Load-Store Address Calculation Extension",
1298                                 [FeatureStdExtZca]>;
1299def HasVendorXqciac
1300    : Predicate<"Subtarget->hasVendorXqciac()">,
1301      AssemblerPredicate<(all_of FeatureVendorXqciac),
1302                         "'Xqciac' (Qualcomm uC Load-Store Address Calculation Extension)">;
1303
1304def FeatureVendorXqcicli
1305    : RISCVExperimentalExtension<0, 2,
1306                                 "Qualcomm uC Conditional Load Immediate Extension">;
1307def HasVendorXqcicli
1308    : Predicate<"Subtarget->hasVendorXqcicli()">,
1309      AssemblerPredicate<(all_of FeatureVendorXqcicli),
1310                         "'Xqcicli' (Qualcomm uC Conditional Load Immediate Extension)">;
1311
1312def FeatureVendorXqcicm
1313    : RISCVExperimentalExtension<0, 2, "Qualcomm uC Conditional Move Extension",
1314                                 [FeatureStdExtZca]>;
1315def HasVendorXqcicm
1316    : Predicate<"Subtarget->hasVendorXqcicm()">,
1317      AssemblerPredicate<(all_of FeatureVendorXqcicm),
1318                         "'Xqcicm' (Qualcomm uC Conditional Move Extension)">;
1319
1320def FeatureVendorXqciint
1321    : RISCVExperimentalExtension<0, 2, "Qualcomm uC Interrupts Extension",
1322                                 [FeatureStdExtZca]>;
1323def HasVendorXqciint
1324    : Predicate<"Subtarget->hasVendorXqciint()">,
1325      AssemblerPredicate<(all_of FeatureVendorXqciint),
1326                         "'Xqciint' (Qualcomm uC Interrupts Extension)">;
1327
1328def FeatureVendorXqcilo
1329    : RISCVExperimentalExtension<0, 2, "Qualcomm uC Large Offset Load Store Extension",
1330                                 [FeatureStdExtZca]>;
1331def HasVendorXqcilo
1332    : Predicate<"Subtarget->hasVendorXqcilo()">,
1333      AssemblerPredicate<(all_of FeatureVendorXqcilo),
1334                         "'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)">;
1335
1336//===----------------------------------------------------------------------===//
1337// LLVM specific features and extensions
1338//===----------------------------------------------------------------------===//
1339
1340// Feature32Bit exists to mark CPUs that support RV32 to distinquish them from
1341// tuning CPU names.
1342def Feature32Bit
1343    : SubtargetFeature<"32bit", "IsRV32", "true", "Implements RV32">;
1344def Feature64Bit
1345    : SubtargetFeature<"64bit", "IsRV64", "true", "Implements RV64">;
1346def IsRV64 : Predicate<"Subtarget->is64Bit()">,
1347             AssemblerPredicate<(all_of Feature64Bit),
1348                                "RV64I Base Instruction Set">;
1349def IsRV32 : Predicate<"!Subtarget->is64Bit()">,
1350             AssemblerPredicate<(all_of (not Feature64Bit)),
1351                                "RV32I Base Instruction Set">;
1352
1353defvar RV32 = DefaultMode;
1354def RV64           : HwMode<"+64bit", [IsRV64]>;
1355
1356def FeatureRelax
1357    : SubtargetFeature<"relax", "EnableLinkerRelax", "true",
1358                       "Enable Linker relaxation.">;
1359
1360foreach i = {1-31} in
1361  def FeatureReserveX#i :
1362      SubtargetFeature<"reserve-x"#i, "UserReservedRegister[RISCV::X"#i#"]",
1363                       "true", "Reserve X"#i>;
1364
1365def FeatureSaveRestore : SubtargetFeature<"save-restore", "EnableSaveRestore",
1366                                          "true", "Enable save/restore.">;
1367
1368def FeatureNoTrailingSeqCstFence : SubtargetFeature<"no-trailing-seq-cst-fence",
1369                                          "EnableTrailingSeqCstFence",
1370                                          "false",
1371                                          "Disable trailing fence for seq-cst store.">;
1372
1373def FeatureUnalignedScalarMem
1374   : SubtargetFeature<"unaligned-scalar-mem", "EnableUnalignedScalarMem",
1375                      "true", "Has reasonably performant unaligned scalar "
1376                      "loads and stores">;
1377
1378def FeatureUnalignedVectorMem
1379   : SubtargetFeature<"unaligned-vector-mem", "EnableUnalignedVectorMem",
1380                      "true", "Has reasonably performant unaligned vector "
1381                      "loads and stores">;
1382
1383def TunePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
1384    "UsePostRAScheduler", "true", "Schedule again after register allocation">;
1385
1386def TuneDisableLatencySchedHeuristic
1387    : SubtargetFeature<"disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true",
1388                       "Disable latency scheduling heuristic">;
1389
1390def TunePredictableSelectIsExpensive
1391    : SubtargetFeature<"predictable-select-expensive", "PredictableSelectIsExpensive", "true",
1392                       "Prefer likely predicted branches over selects">;
1393
1394def TuneOptimizedZeroStrideLoad
1395   : SubtargetFeature<"optimized-zero-stride-load", "HasOptimizedZeroStrideLoad",
1396                      "true", "Optimized (perform fewer memory operations)"
1397                      "zero-stride vector load">;
1398
1399foreach nf = {2-8} in
1400  def TuneOptimizedNF#nf#SegmentLoadStore :
1401      SubtargetFeature<"optimized-nf"#nf#"-segment-load-store",
1402                       "HasOptimizedNF"#nf#"SegmentLoadStore",
1403                       "true", "vlseg"#nf#"eN.v and vsseg"#nf#"eN.v are"
1404                       "implemented as a wide memory op and shuffle">;
1405
1406def Experimental
1407   : SubtargetFeature<"experimental", "HasExperimental",
1408                      "true", "Experimental intrinsics">;
1409
1410// Some vector hardware implementations do not process all VLEN bits in parallel
1411// and instead split over multiple cycles. DLEN refers to the datapath width
1412// that can be done in parallel.
1413def TuneDLenFactor2
1414   : SubtargetFeature<"dlen-factor-2", "DLenFactor2", "true",
1415                      "Vector unit DLEN(data path width) is half of VLEN">;
1416
1417def TuneNoDefaultUnroll
1418    : SubtargetFeature<"no-default-unroll", "EnableDefaultUnroll", "false",
1419                       "Disable default unroll preference.">;
1420
1421// SiFive 7 is able to fuse integer ALU operations with a preceding branch
1422// instruction.
1423def TuneShortForwardBranchOpt
1424    : SubtargetFeature<"short-forward-branch-opt", "HasShortForwardBranchOpt",
1425                       "true", "Enable short forward branch optimization">;
1426def HasShortForwardBranchOpt : Predicate<"Subtarget->hasShortForwardBranchOpt()">;
1427def NoShortForwardBranchOpt : Predicate<"!Subtarget->hasShortForwardBranchOpt()">;
1428
1429// Some subtargets require a S2V transfer buffer to move scalars into vectors.
1430// FIXME: Forming .vx/.vf/.wx/.wf can reduce register pressure.
1431def TuneNoSinkSplatOperands
1432    : SubtargetFeature<"no-sink-splat-operands", "SinkSplatOperands",
1433                       "false", "Disable sink splat operands to enable .vx, .vf,"
1434                       ".wx, and .wf instructions">;
1435
1436def TunePreferWInst
1437    : SubtargetFeature<"prefer-w-inst", "PreferWInst", "true",
1438                       "Prefer instructions with W suffix">;
1439
1440def TuneConditionalCompressedMoveFusion
1441    : SubtargetFeature<"conditional-cmv-fusion", "HasConditionalCompressedMoveFusion",
1442                       "true", "Enable branch+c.mv fusion">;
1443def HasConditionalMoveFusion : Predicate<"Subtarget->hasConditionalMoveFusion()">;
1444def NoConditionalMoveFusion  : Predicate<"!Subtarget->hasConditionalMoveFusion()">;
1445
1446def TuneMIPSP8700
1447    : SubtargetFeature<"mips-p8700", "RISCVProcFamily", "MIPSP8700",
1448                       "MIPS p8700 processor">;
1449
1450def TuneSiFive7 : SubtargetFeature<"sifive7", "RISCVProcFamily", "SiFive7",
1451                                   "SiFive 7-Series processors">;
1452
1453def TuneVentanaVeyron : SubtargetFeature<"ventana-veyron", "RISCVProcFamily", "VentanaVeyron",
1454                                         "Ventana Veyron-Series processors">;
1455
1456def TuneVXRMPipelineFlush : SubtargetFeature<"vxrm-pipeline-flush", "HasVXRMPipelineFlush",
1457                                             "true", "VXRM writes causes pipeline flush">;
1458
1459// Assume that lock-free native-width atomics are available, even if the target
1460// and operating system combination would not usually provide them. The user
1461// is responsible for providing any necessary __sync implementations. Code
1462// built with this feature is not ABI-compatible with code built without this
1463// feature, if atomic variables are exposed across the ABI boundary.
1464def FeatureForcedAtomics : SubtargetFeature<
1465    "forced-atomics", "HasForcedAtomics", "true",
1466    "Assume that lock-free native-width atomics are available">;
1467def HasAtomicLdSt
1468    : Predicate<"Subtarget->hasStdExtA() || Subtarget->hasForcedAtomics()">;
1469
1470def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals",
1471    "AllowTaggedGlobals",
1472    "true", "Use an instruction sequence for taking the address of a global "
1473    "that allows a memory tag in the upper address bits">;
1474