1//===-- RISCV.td - Describe the RISC-V Target Machine ------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9include "llvm/Target/Target.td" 10 11//===----------------------------------------------------------------------===// 12// RISC-V subtarget features and instruction predicates. 13//===----------------------------------------------------------------------===// 14 15include "RISCVFeatures.td" 16 17//===----------------------------------------------------------------------===// 18// RISC-V profiles supported. 19//===----------------------------------------------------------------------===// 20 21include "RISCVProfiles.td" 22 23//===----------------------------------------------------------------------===// 24// Named operands for CSR instructions. 25//===----------------------------------------------------------------------===// 26 27include "RISCVSystemOperands.td" 28 29//===----------------------------------------------------------------------===// 30// Registers, calling conventions, instruction descriptions. 31//===----------------------------------------------------------------------===// 32 33include "RISCVRegisterInfo.td" 34include "RISCVSchedule.td" 35include "RISCVCallingConv.td" 36include "RISCVInstrInfo.td" 37include "GISel/RISCVRegisterBanks.td" 38 39//===----------------------------------------------------------------------===// 40// RISC-V macro fusions. 41//===----------------------------------------------------------------------===// 42 43include "RISCVMacroFusion.td" 44 45//===----------------------------------------------------------------------===// 46// RISC-V Scheduling Models 47//===----------------------------------------------------------------------===// 48 49include "RISCVSchedMIPSP8700.td" 50include "RISCVSchedRocket.td" 51include "RISCVSchedSiFive7.td" 52include "RISCVSchedSiFiveP400.td" 53include "RISCVSchedSiFiveP500.td" 54include "RISCVSchedSiFiveP600.td" 55include "RISCVSchedSyntacoreSCR1.td" 56include "RISCVSchedSyntacoreSCR345.td" 57include "RISCVSchedSyntacoreSCR7.td" 58include "RISCVSchedTTAscalonD8.td" 59include "RISCVSchedXiangShanNanHu.td" 60 61//===----------------------------------------------------------------------===// 62// RISC-V processors supported. 63//===----------------------------------------------------------------------===// 64 65include "RISCVProcessors.td" 66 67//===----------------------------------------------------------------------===// 68// Pfm Counters 69//===----------------------------------------------------------------------===// 70 71include "RISCVPfmCounters.td" 72 73//===----------------------------------------------------------------------===// 74// Define the RISC-V target. 75//===----------------------------------------------------------------------===// 76 77def RISCVInstrInfo : InstrInfo { 78 let guessInstructionProperties = 0; 79} 80 81def RISCVAsmParser : AsmParser { 82 let ShouldEmitMatchRegisterAltName = 1; 83 let AllowDuplicateRegisterNames = 1; 84} 85 86def RISCVAsmWriter : AsmWriter { 87 int PassSubtarget = 1; 88} 89 90def RISCV : Target { 91 let InstructionSet = RISCVInstrInfo; 92 let AssemblyParsers = [RISCVAsmParser]; 93 let AssemblyWriters = [RISCVAsmWriter]; 94 let AllowRegisterRenaming = 1; 95} 96