xref: /llvm-project/llvm/lib/Target/RISCV/CMakeLists.txt (revision afa8aeeeec9a897a35ba5c8afc024d9b10504db1) 
1add_llvm_component_group(RISCV)
2
3set(LLVM_TARGET_DEFINITIONS RISCV.td)
4
5tablegen(LLVM RISCVGenAsmMatcher.inc -gen-asm-matcher)
6tablegen(LLVM RISCVGenAsmWriter.inc -gen-asm-writer)
7tablegen(LLVM RISCVGenCompressInstEmitter.inc -gen-compress-inst-emitter)
8tablegen(LLVM RISCVGenMacroFusion.inc -gen-macro-fusion-pred)
9tablegen(LLVM RISCVGenDAGISel.inc -gen-dag-isel)
10tablegen(LLVM RISCVGenDisassemblerTables.inc -gen-disassembler)
11tablegen(LLVM RISCVGenInstrInfo.inc -gen-instr-info)
12tablegen(LLVM RISCVGenMCCodeEmitter.inc -gen-emitter)
13tablegen(LLVM RISCVGenMCPseudoLowering.inc -gen-pseudo-lowering)
14tablegen(LLVM RISCVGenRegisterBank.inc -gen-register-bank)
15tablegen(LLVM RISCVGenRegisterInfo.inc -gen-register-info)
16tablegen(LLVM RISCVGenSearchableTables.inc -gen-searchable-tables)
17tablegen(LLVM RISCVGenSubtargetInfo.inc -gen-subtarget)
18tablegen(LLVM RISCVGenExegesis.inc -gen-exegesis)
19
20set(LLVM_TARGET_DEFINITIONS RISCVGISel.td)
21tablegen(LLVM RISCVGenGlobalISel.inc -gen-global-isel)
22tablegen(LLVM RISCVGenO0PreLegalizeGICombiner.inc -gen-global-isel-combiner
23              -combiners="RISCVO0PreLegalizerCombiner")
24tablegen(LLVM RISCVGenPreLegalizeGICombiner.inc -gen-global-isel-combiner
25              -combiners="RISCVPreLegalizerCombiner")
26tablegen(LLVM RISCVGenPostLegalizeGICombiner.inc -gen-global-isel-combiner
27              -combiners="RISCVPostLegalizerCombiner")
28
29add_public_tablegen_target(RISCVCommonTableGen)
30
31add_llvm_target(RISCVCodeGen
32  RISCVAsmPrinter.cpp
33  RISCVCallingConv.cpp
34  RISCVCodeGenPrepare.cpp
35  RISCVConstantPoolValue.cpp
36  RISCVDeadRegisterDefinitions.cpp
37  RISCVMakeCompressible.cpp
38  RISCVExpandAtomicPseudoInsts.cpp
39  RISCVExpandPseudoInsts.cpp
40  RISCVFrameLowering.cpp
41  RISCVGatherScatterLowering.cpp
42  RISCVIndirectBranchTracking.cpp
43  RISCVInsertVSETVLI.cpp
44  RISCVInsertReadWriteCSR.cpp
45  RISCVInsertWriteVXRM.cpp
46  RISCVInstrInfo.cpp
47  RISCVISelDAGToDAG.cpp
48  RISCVISelLowering.cpp
49  RISCVLandingPadSetup.cpp
50  RISCVMachineFunctionInfo.cpp
51  RISCVMergeBaseOffset.cpp
52  RISCVOptWInstrs.cpp
53  RISCVPostRAExpandPseudoInsts.cpp
54  RISCVRedundantCopyElimination.cpp
55  RISCVMoveMerger.cpp
56  RISCVPushPopOptimizer.cpp
57  RISCVRegisterInfo.cpp
58  RISCVSelectionDAGInfo.cpp
59  RISCVSubtarget.cpp
60  RISCVTargetMachine.cpp
61  RISCVTargetObjectFile.cpp
62  RISCVTargetTransformInfo.cpp
63  RISCVVectorMaskDAGMutation.cpp
64  RISCVVectorPeephole.cpp
65  RISCVVLOptimizer.cpp
66  RISCVZacasABIFix.cpp
67  GISel/RISCVCallLowering.cpp
68  GISel/RISCVInstructionSelector.cpp
69  GISel/RISCVLegalizerInfo.cpp
70  GISel/RISCVPostLegalizerCombiner.cpp
71  GISel/RISCVO0PreLegalizerCombiner.cpp
72  GISel/RISCVPreLegalizerCombiner.cpp
73  GISel/RISCVRegisterBankInfo.cpp
74
75  LINK_COMPONENTS
76  Analysis
77  AsmPrinter
78  CodeGen
79  CodeGenTypes
80  Core
81  GlobalISel
82  IPO
83  MC
84  RISCVDesc
85  RISCVInfo
86  Scalar
87  SelectionDAG
88  Support
89  Target
90  TargetParser
91  TransformUtils
92  Vectorize
93
94  ADD_TO_COMPONENT
95  RISCV
96  )
97
98add_subdirectory(AsmParser)
99add_subdirectory(Disassembler)
100add_subdirectory(MCTargetDesc)
101add_subdirectory(MCA)
102add_subdirectory(TargetInfo)
103