1//===-- PPCRegisterInfoMMA.td - The PowerPC Register File --*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// Register info for registers related to MMA. These are the ACC and UACC 10// registers. 11// 12//===----------------------------------------------------------------------===// 13 14let Namespace = "PPC" in { 15def sub_pair0 : SubRegIndex<256>; 16def sub_pair1 : SubRegIndex<256, 256>; 17} 18 19// ACC - One of the 8 512-bit VSX accumulators. 20class ACC<bits<3> num, string n, list<Register> subregs> : PPCReg<n> { 21 let HWEncoding{2-0} = num; 22 let SubRegs = subregs; 23} 24 25// UACC - One of the 8 512-bit VSX accumulators prior to being primed. 26// Without using this register class, the register allocator has no way to 27// differentiate a primed accumulator from an unprimed accumulator. 28// This may result in invalid copies between primed and unprimed accumulators. 29class UACC<bits<3> num, string n, list<Register> subregs> : PPCReg<n> { 30 let HWEncoding{2-0} = num; 31 let SubRegs = subregs; 32} 33 34// SPE Accumulator for multiply-accumulate SPE operations. Never directly 35// accessed, so there's no real encoding for it. 36def SPEACC: DwarfRegNum<[99, 111]>; 37 38let SubRegIndices = [sub_pair0, sub_pair1] in { 39 def ACC0 : ACC<0, "acc0", [VSRp0, VSRp1]>, DwarfRegNum<[-1, -1]>; 40 def ACC1 : ACC<1, "acc1", [VSRp2, VSRp3]>, DwarfRegNum<[-1, -1]>; 41 def ACC2 : ACC<2, "acc2", [VSRp4, VSRp5]>, DwarfRegNum<[-1, -1]>; 42 def ACC3 : ACC<3, "acc3", [VSRp6, VSRp7]>, DwarfRegNum<[-1, -1]>; 43 def ACC4 : ACC<4, "acc4", [VSRp8, VSRp9]>, DwarfRegNum<[-1, -1]>; 44 def ACC5 : ACC<5, "acc5", [VSRp10, VSRp11]>, DwarfRegNum<[-1, -1]>; 45 def ACC6 : ACC<6, "acc6", [VSRp12, VSRp13]>, DwarfRegNum<[-1, -1]>; 46 def ACC7 : ACC<7, "acc7", [VSRp14, VSRp15]>, DwarfRegNum<[-1, -1]>; 47} 48def ACCRC : RegisterClass<"PPC", [v512i1], 128, (add ACC0, ACC1, ACC2, ACC3, 49 ACC4, ACC5, ACC6, ACC7)> { 50 // The AllocationPriority is in the range [0, 31]. Assigned the ACC registers 51 // the highest possible priority in this range to force the register allocator 52 // to assign these registers first. This is done because the ACC registers 53 // must represent 4 advacent vector registers. For example ACC1 must be 54 // VS4 - VS7. 55 let AllocationPriority = 31; 56 57 // We want to allocate these registers even before we allocate 58 // global ranges. 59 let GlobalPriority = true; 60 let Size = 512; 61} 62 63let SubRegIndices = [sub_pair0, sub_pair1] in { 64 def UACC0 : UACC<0, "acc0", [VSRp0, VSRp1]>, DwarfRegNum<[-1, -1]>; 65 def UACC1 : UACC<1, "acc1", [VSRp2, VSRp3]>, DwarfRegNum<[-1, -1]>; 66 def UACC2 : UACC<2, "acc2", [VSRp4, VSRp5]>, DwarfRegNum<[-1, -1]>; 67 def UACC3 : UACC<3, "acc3", [VSRp6, VSRp7]>, DwarfRegNum<[-1, -1]>; 68 def UACC4 : UACC<4, "acc4", [VSRp8, VSRp9]>, DwarfRegNum<[-1, -1]>; 69 def UACC5 : UACC<5, "acc5", [VSRp10, VSRp11]>, DwarfRegNum<[-1, -1]>; 70 def UACC6 : UACC<6, "acc6", [VSRp12, VSRp13]>, DwarfRegNum<[-1, -1]>; 71 def UACC7 : UACC<7, "acc7", [VSRp14, VSRp15]>, DwarfRegNum<[-1, -1]>; 72} 73def UACCRC : RegisterClass<"PPC", [v512i1], 128, 74 (add UACC0, UACC1, UACC2, UACC3, 75 UACC4, UACC5, UACC6, UACC7)> { 76 // The AllocationPriority for the UACC registers is still high and must be at 77 // least 32 as we want to allocate these registers before we allocate other 78 // global ranges. The value must be less than the AllocationPriority of the 79 // ACC registers. 80 let AllocationPriority = 4; 81 let GlobalPriority = true; 82 let Size = 512; 83} 84 85// FIXME: This allocation order may increase stack frame size when allocating 86// non-volatile registers. 87// 88// Placing Altivec registers first and allocate the rest as underlying VSX 89// ones, to reduce interference with accumulator registers (lower 32 VSRs). 90// This reduces copies when loading for accumulators, which is common use for 91// paired VSX registers. 92def VSRpRC : 93 RegisterClass<"PPC", [v256i1], 128, 94 (add VSRp17, VSRp18, VSRp16, VSRp19, VSRp20, VSRp21, 95 VSRp22, VSRp23, VSRp24, VSRp25, VSRp31, VSRp30, 96 VSRp29, VSRp28, VSRp27, VSRp26, 97 (sequence "VSRp%u", 0, 6), 98 (sequence "VSRp%u", 15, 7))> { 99 // Give the VSRp registers a non-zero AllocationPriority. The value is less 100 // than 32 as these registers should not always be allocated before global 101 // ranges and the value should be less than the AllocationPriority - 32 for 102 // the UACC registers. Even global VSRp registers should be allocated after 103 // the UACC registers have been chosen. 104 let AllocationPriority = 2; 105 let Size = 256; 106} 107 108 109 110 111