1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the TargetRegisterInfo 11 // class. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #define DEBUG_TYPE "reginfo" 16 #include "PPC.h" 17 #include "PPCInstrBuilder.h" 18 #include "PPCMachineFunctionInfo.h" 19 #include "PPCRegisterInfo.h" 20 #include "PPCFrameInfo.h" 21 #include "PPCSubtarget.h" 22 #include "llvm/Constants.h" 23 #include "llvm/Function.h" 24 #include "llvm/Type.h" 25 #include "llvm/CodeGen/ValueTypes.h" 26 #include "llvm/CodeGen/MachineInstrBuilder.h" 27 #include "llvm/CodeGen/MachineModuleInfo.h" 28 #include "llvm/CodeGen/MachineFunction.h" 29 #include "llvm/CodeGen/MachineFrameInfo.h" 30 #include "llvm/CodeGen/MachineLocation.h" 31 #include "llvm/CodeGen/MachineRegisterInfo.h" 32 #include "llvm/CodeGen/RegisterScavenging.h" 33 #include "llvm/CodeGen/SelectionDAGNodes.h" 34 #include "llvm/Target/TargetFrameInfo.h" 35 #include "llvm/Target/TargetInstrInfo.h" 36 #include "llvm/Target/TargetMachine.h" 37 #include "llvm/Target/TargetOptions.h" 38 #include "llvm/Support/CommandLine.h" 39 #include "llvm/Support/Debug.h" 40 #include "llvm/Support/MathExtras.h" 41 #include "llvm/ADT/BitVector.h" 42 #include "llvm/ADT/STLExtras.h" 43 #include <cstdlib> 44 using namespace llvm; 45 46 // FIXME This disables some code that aligns the stack to a boundary 47 // bigger than the default (16 bytes on Darwin) when there is a stack local 48 // of greater alignment. This does not currently work, because the delta 49 // between old and new stack pointers is added to offsets that reference 50 // incoming parameters after the prolog is generated, and the code that 51 // does that doesn't handle a variable delta. You don't want to do that 52 // anyway; a better approach is to reserve another register that retains 53 // to the incoming stack pointer, and reference parameters relative to that. 54 #define ALIGN_STACK 0 55 56 // FIXME (64-bit): Eventually enable by default. 57 cl::opt<bool> EnablePPC32RS("enable-ppc32-regscavenger", 58 cl::init(false), 59 cl::desc("Enable PPC32 register scavenger"), 60 cl::Hidden); 61 cl::opt<bool> EnablePPC64RS("enable-ppc64-regscavenger", 62 cl::init(false), 63 cl::desc("Enable PPC64 register scavenger"), 64 cl::Hidden); 65 #define EnableRegisterScavenging \ 66 ((EnablePPC32RS && !Subtarget.isPPC64()) || \ 67 (EnablePPC64RS && Subtarget.isPPC64())) 68 69 // FIXME (64-bit): Should be inlined. 70 bool 71 PPCRegisterInfo::requiresRegisterScavenging(const MachineFunction &) const { 72 return EnableRegisterScavenging; 73 } 74 75 /// getRegisterNumbering - Given the enum value for some register, e.g. 76 /// PPC::F14, return the number that it corresponds to (e.g. 14). 77 unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) { 78 using namespace PPC; 79 switch (RegEnum) { 80 case 0: return 0; 81 case R0 : case X0 : case F0 : case V0 : case CR0: case CR0LT: return 0; 82 case R1 : case X1 : case F1 : case V1 : case CR1: case CR0GT: return 1; 83 case R2 : case X2 : case F2 : case V2 : case CR2: case CR0EQ: return 2; 84 case R3 : case X3 : case F3 : case V3 : case CR3: case CR0UN: return 3; 85 case R4 : case X4 : case F4 : case V4 : case CR4: case CR1LT: return 4; 86 case R5 : case X5 : case F5 : case V5 : case CR5: case CR1GT: return 5; 87 case R6 : case X6 : case F6 : case V6 : case CR6: case CR1EQ: return 6; 88 case R7 : case X7 : case F7 : case V7 : case CR7: case CR1UN: return 7; 89 case R8 : case X8 : case F8 : case V8 : case CR2LT: return 8; 90 case R9 : case X9 : case F9 : case V9 : case CR2GT: return 9; 91 case R10: case X10: case F10: case V10: case CR2EQ: return 10; 92 case R11: case X11: case F11: case V11: case CR2UN: return 11; 93 case R12: case X12: case F12: case V12: case CR3LT: return 12; 94 case R13: case X13: case F13: case V13: case CR3GT: return 13; 95 case R14: case X14: case F14: case V14: case CR3EQ: return 14; 96 case R15: case X15: case F15: case V15: case CR3UN: return 15; 97 case R16: case X16: case F16: case V16: case CR4LT: return 16; 98 case R17: case X17: case F17: case V17: case CR4GT: return 17; 99 case R18: case X18: case F18: case V18: case CR4EQ: return 18; 100 case R19: case X19: case F19: case V19: case CR4UN: return 19; 101 case R20: case X20: case F20: case V20: case CR5LT: return 20; 102 case R21: case X21: case F21: case V21: case CR5GT: return 21; 103 case R22: case X22: case F22: case V22: case CR5EQ: return 22; 104 case R23: case X23: case F23: case V23: case CR5UN: return 23; 105 case R24: case X24: case F24: case V24: case CR6LT: return 24; 106 case R25: case X25: case F25: case V25: case CR6GT: return 25; 107 case R26: case X26: case F26: case V26: case CR6EQ: return 26; 108 case R27: case X27: case F27: case V27: case CR6UN: return 27; 109 case R28: case X28: case F28: case V28: case CR7LT: return 28; 110 case R29: case X29: case F29: case V29: case CR7GT: return 29; 111 case R30: case X30: case F30: case V30: case CR7EQ: return 30; 112 case R31: case X31: case F31: case V31: case CR7UN: return 31; 113 default: 114 cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n"; 115 abort(); 116 } 117 } 118 119 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST, 120 const TargetInstrInfo &tii) 121 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP), 122 Subtarget(ST), TII(tii) { 123 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 124 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 125 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 126 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 127 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 128 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 129 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 130 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 131 132 // 64-bit 133 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8; 134 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8; 135 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8; 136 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX; 137 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32; 138 } 139 140 const unsigned* 141 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 142 // 32-bit Darwin calling convention. 143 static const unsigned Macho32_CalleeSavedRegs[] = { 144 PPC::R13, PPC::R14, PPC::R15, 145 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 146 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 147 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 148 PPC::R28, PPC::R29, PPC::R30, PPC::R31, 149 150 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 151 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 152 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 153 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 154 PPC::F30, PPC::F31, 155 156 PPC::CR2, PPC::CR3, PPC::CR4, 157 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 158 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 159 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 160 161 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 162 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 163 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 164 165 PPC::LR, 0 166 }; 167 168 static const unsigned ELF32_CalleeSavedRegs[] = { 169 PPC::R13, PPC::R14, PPC::R15, 170 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 171 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 172 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 173 PPC::R28, PPC::R29, PPC::R30, PPC::R31, 174 175 PPC::F9, 176 PPC::F10, PPC::F11, PPC::F12, PPC::F13, 177 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 178 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 179 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 180 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 181 PPC::F30, PPC::F31, 182 183 PPC::CR2, PPC::CR3, PPC::CR4, 184 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 185 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 186 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 187 188 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 189 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 190 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 191 192 PPC::LR, 0 193 }; 194 // 64-bit Darwin calling convention. 195 static const unsigned Macho64_CalleeSavedRegs[] = { 196 PPC::X14, PPC::X15, 197 PPC::X16, PPC::X17, PPC::X18, PPC::X19, 198 PPC::X20, PPC::X21, PPC::X22, PPC::X23, 199 PPC::X24, PPC::X25, PPC::X26, PPC::X27, 200 PPC::X28, PPC::X29, PPC::X30, PPC::X31, 201 202 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 203 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 204 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 205 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 206 PPC::F30, PPC::F31, 207 208 PPC::CR2, PPC::CR3, PPC::CR4, 209 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 210 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 211 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 212 213 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 214 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 215 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 216 217 PPC::LR8, 0 218 }; 219 220 if (Subtarget.isMachoABI()) 221 return Subtarget.isPPC64() ? Macho64_CalleeSavedRegs : 222 Macho32_CalleeSavedRegs; 223 224 // ELF 32. 225 return ELF32_CalleeSavedRegs; 226 } 227 228 const TargetRegisterClass* const* 229 PPCRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const { 230 // 32-bit Macho calling convention. 231 static const TargetRegisterClass * const Macho32_CalleeSavedRegClasses[] = { 232 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 233 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 234 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 235 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 236 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 237 238 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 239 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 240 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 241 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 242 &PPC::F8RCRegClass,&PPC::F8RCRegClass, 243 244 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, 245 246 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 247 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 248 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 249 250 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 251 &PPC::CRBITRCRegClass, 252 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 253 &PPC::CRBITRCRegClass, 254 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 255 &PPC::CRBITRCRegClass, 256 257 &PPC::GPRCRegClass, 0 258 }; 259 260 static const TargetRegisterClass * const ELF32_CalleeSavedRegClasses[] = { 261 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 262 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 263 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 264 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 265 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 266 267 &PPC::F8RCRegClass, 268 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 269 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 270 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 271 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 272 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 273 &PPC::F8RCRegClass,&PPC::F8RCRegClass, 274 275 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, 276 277 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 278 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 279 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 280 281 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 282 &PPC::CRBITRCRegClass, 283 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 284 &PPC::CRBITRCRegClass, 285 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 286 &PPC::CRBITRCRegClass, 287 288 &PPC::GPRCRegClass, 0 289 }; 290 291 // 64-bit Macho calling convention. 292 static const TargetRegisterClass * const Macho64_CalleeSavedRegClasses[] = { 293 &PPC::G8RCRegClass,&PPC::G8RCRegClass, 294 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 295 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 296 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 297 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 298 299 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 300 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 301 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 302 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 303 &PPC::F8RCRegClass,&PPC::F8RCRegClass, 304 305 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, 306 307 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 308 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 309 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 310 311 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 312 &PPC::CRBITRCRegClass, 313 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 314 &PPC::CRBITRCRegClass, 315 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 316 &PPC::CRBITRCRegClass, 317 318 &PPC::G8RCRegClass, 0 319 }; 320 321 if (Subtarget.isMachoABI()) 322 return Subtarget.isPPC64() ? Macho64_CalleeSavedRegClasses : 323 Macho32_CalleeSavedRegClasses; 324 325 // ELF 32. 326 return ELF32_CalleeSavedRegClasses; 327 } 328 329 // needsFP - Return true if the specified function should have a dedicated frame 330 // pointer register. This is true if the function has variable sized allocas or 331 // if frame pointer elimination is disabled. 332 // 333 static bool needsFP(const MachineFunction &MF) { 334 const MachineFrameInfo *MFI = MF.getFrameInfo(); 335 return NoFramePointerElim || MFI->hasVarSizedObjects(); 336 } 337 338 static bool spillsCR(const MachineFunction &MF) { 339 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 340 return FuncInfo->isCRSpilled(); 341 } 342 343 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 344 BitVector Reserved(getNumRegs()); 345 Reserved.set(PPC::R0); 346 Reserved.set(PPC::R1); 347 Reserved.set(PPC::LR); 348 Reserved.set(PPC::LR8); 349 350 // In Linux, r2 is reserved for the OS. 351 if (!Subtarget.isDarwin()) 352 Reserved.set(PPC::R2); 353 354 // On PPC64, r13 is the thread pointer. Never allocate this register. Note 355 // that this is over conservative, as it also prevents allocation of R31 when 356 // the FP is not needed. 357 if (Subtarget.isPPC64()) { 358 Reserved.set(PPC::R13); 359 Reserved.set(PPC::R31); 360 361 if (!EnableRegisterScavenging) 362 Reserved.set(PPC::R0); // FIXME (64-bit): Remove 363 364 Reserved.set(PPC::X0); 365 Reserved.set(PPC::X1); 366 Reserved.set(PPC::X13); 367 Reserved.set(PPC::X31); 368 } 369 370 if (needsFP(MF)) 371 Reserved.set(PPC::R31); 372 373 return Reserved; 374 } 375 376 //===----------------------------------------------------------------------===// 377 // Stack Frame Processing methods 378 //===----------------------------------------------------------------------===// 379 380 // hasFP - Return true if the specified function actually has a dedicated frame 381 // pointer register. This is true if the function needs a frame pointer and has 382 // a non-zero stack size. 383 bool PPCRegisterInfo::hasFP(const MachineFunction &MF) const { 384 const MachineFrameInfo *MFI = MF.getFrameInfo(); 385 return MFI->getStackSize() && needsFP(MF); 386 } 387 388 /// MustSaveLR - Return true if this function requires that we save the LR 389 /// register onto the stack in the prolog and restore it in the epilog of the 390 /// function. 391 static bool MustSaveLR(const MachineFunction &MF) { 392 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>(); 393 394 // We need an save/restore of LR if there is any use/def of LR explicitly, or 395 // if there is some use of the LR stack slot (e.g. for builtin_return_address. 396 return MFI->usesLR() || MFI->isLRStoreRequired() || 397 // FIXME: Anything that has a call should clobber the LR register, 398 // isn't this redundant?? 399 MF.getFrameInfo()->hasCalls(); 400 } 401 402 void PPCRegisterInfo:: 403 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 404 MachineBasicBlock::iterator I) const { 405 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions. 406 MBB.erase(I); 407 } 408 409 /// findScratchRegister - Find a 'free' PPC register. Try for a call-clobbered 410 /// register first and then a spilled callee-saved register if that fails. 411 static 412 unsigned findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS, 413 const TargetRegisterClass *RC, int SPAdj) { 414 assert(RS && "Register scavenging must be on"); 415 unsigned Reg = RS->FindUnusedReg(RC, true); 416 // FIXME: move ARM callee-saved reg scan to target independent code, then 417 // search for already spilled CS register here. 418 if (Reg == 0) 419 Reg = RS->scavengeRegister(RC, II, SPAdj); 420 return Reg; 421 } 422 423 /// lowerDynamicAlloc - Generate the code for allocating an object in the 424 /// current frame. The sequence of code with be in the general form 425 /// 426 /// addi R0, SP, #frameSize ; get the address of the previous frame 427 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size 428 /// addi Rnew, SP, #maxCalFrameSize ; get the top of the allocation 429 /// 430 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II, 431 int SPAdj, RegScavenger *RS) const { 432 // Get the instruction. 433 MachineInstr &MI = *II; 434 // Get the instruction's basic block. 435 MachineBasicBlock &MBB = *MI.getParent(); 436 // Get the basic block's function. 437 MachineFunction &MF = *MBB.getParent(); 438 // Get the frame info. 439 MachineFrameInfo *MFI = MF.getFrameInfo(); 440 // Determine whether 64-bit pointers are used. 441 bool LP64 = Subtarget.isPPC64(); 442 443 // Get the maximum call stack size. 444 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 445 // Get the total frame size. 446 unsigned FrameSize = MFI->getStackSize(); 447 448 // Get stack alignments. 449 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 450 unsigned MaxAlign = MFI->getMaxAlignment(); 451 assert(MaxAlign <= TargetAlign && 452 "Dynamic alloca with large aligns not supported"); 453 454 // Determine the previous frame's address. If FrameSize can't be 455 // represented as 16 bits or we need special alignment, then we load the 456 // previous frame's address from 0(SP). Why not do an addis of the hi? 457 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. 458 // Constructing the constant and adding would take 3 instructions. 459 // Fortunately, a frame greater than 32K is rare. 460 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 461 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 462 const TargetRegisterClass *RC = LP64 ? G8RC : GPRC; 463 464 // FIXME (64-bit): Use "findScratchRegister" 465 unsigned Reg; 466 if (EnableRegisterScavenging) 467 Reg = findScratchRegister(II, RS, RC, SPAdj); 468 else 469 Reg = PPC::R0; 470 471 if (MaxAlign < TargetAlign && isInt16(FrameSize)) { 472 BuildMI(MBB, II, TII.get(PPC::ADDI), Reg) 473 .addReg(PPC::R31) 474 .addImm(FrameSize); 475 } else if (LP64) { 476 if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part. 477 BuildMI(MBB, II, TII.get(PPC::LD), Reg) 478 .addImm(0) 479 .addReg(PPC::X1); 480 else 481 BuildMI(MBB, II, TII.get(PPC::LD), PPC::X0) 482 .addImm(0) 483 .addReg(PPC::X1); 484 } else { 485 BuildMI(MBB, II, TII.get(PPC::LWZ), Reg) 486 .addImm(0) 487 .addReg(PPC::R1); 488 } 489 490 // Grow the stack and update the stack pointer link, then determine the 491 // address of new allocated space. 492 if (LP64) { 493 if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part. 494 BuildMI(MBB, II, TII.get(PPC::STDUX)) 495 .addReg(Reg, false, false, true) 496 .addReg(PPC::X1) 497 .addReg(MI.getOperand(1).getReg()); 498 else 499 BuildMI(MBB, II, TII.get(PPC::STDUX)) 500 .addReg(PPC::X0, false, false, true) 501 .addReg(PPC::X1) 502 .addReg(MI.getOperand(1).getReg()); 503 504 if (!MI.getOperand(1).isKill()) 505 BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 506 .addReg(PPC::X1) 507 .addImm(maxCallFrameSize); 508 else 509 // Implicitly kill the register. 510 BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 511 .addReg(PPC::X1) 512 .addImm(maxCallFrameSize) 513 .addReg(MI.getOperand(1).getReg(), false, true, true); 514 } else { 515 BuildMI(MBB, II, TII.get(PPC::STWUX)) 516 .addReg(Reg, false, false, true) 517 .addReg(PPC::R1) 518 .addReg(MI.getOperand(1).getReg()); 519 520 if (!MI.getOperand(1).isKill()) 521 BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 522 .addReg(PPC::R1) 523 .addImm(maxCallFrameSize); 524 else 525 // Implicitly kill the register. 526 BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 527 .addReg(PPC::R1) 528 .addImm(maxCallFrameSize) 529 .addReg(MI.getOperand(1).getReg(), false, true, true); 530 } 531 532 // Discard the DYNALLOC instruction. 533 MBB.erase(II); 534 } 535 536 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of 537 /// reserving a whole register (R0), we scrounge for one here. This generates 538 /// code like this: 539 /// 540 /// mfcr rA ; Move the conditional register into GPR rA. 541 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot. 542 /// stw rA, FI ; Store rA to the frame. 543 /// 544 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, 545 unsigned FrameIndex, int SPAdj, 546 RegScavenger *RS) const { 547 // Get the instruction. 548 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>, <FI> 549 // Get the instruction's basic block. 550 MachineBasicBlock &MBB = *MI.getParent(); 551 552 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 553 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 554 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC; 555 unsigned Reg = findScratchRegister(II, RS, RC, SPAdj); 556 557 // We need to store the CR in the low 4-bits of the saved value. First, issue 558 // an MFCR to save all of the CRBits. Add an implicit kill of the CR. 559 if (!MI.getOperand(0).isKill()) 560 BuildMI(MBB, II, TII.get(PPC::MFCR), Reg); 561 else 562 // Implicitly kill the CR register. 563 BuildMI(MBB, II, TII.get(PPC::MFCR), Reg) 564 .addReg(MI.getOperand(0).getReg(), false, true, true); 565 566 // If the saved register wasn't CR0, shift the bits left so that they are in 567 // CR0's slot. 568 unsigned SrcReg = MI.getOperand(0).getReg(); 569 if (SrcReg != PPC::CR0) 570 // rlwinm rA, rA, ShiftBits, 0, 31. 571 BuildMI(MBB, II, TII.get(PPC::RLWINM), Reg) 572 .addReg(Reg, false, false, true) 573 .addImm(PPCRegisterInfo::getRegisterNumbering(SrcReg) * 4) 574 .addImm(0) 575 .addImm(31); 576 577 addFrameReference(BuildMI(MBB, II, TII.get(PPC::STW)) 578 .addReg(Reg, false, false, MI.getOperand(1).getImm()), 579 FrameIndex); 580 581 // Discard the pseudo instruction. 582 MBB.erase(II); 583 } 584 585 void PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 586 int SPAdj, RegScavenger *RS) const { 587 assert(SPAdj == 0 && "Unexpected"); 588 589 // Get the instruction. 590 MachineInstr &MI = *II; 591 // Get the instruction's basic block. 592 MachineBasicBlock &MBB = *MI.getParent(); 593 // Get the basic block's function. 594 MachineFunction &MF = *MBB.getParent(); 595 // Get the frame info. 596 MachineFrameInfo *MFI = MF.getFrameInfo(); 597 598 // Find out which operand is the frame index. 599 unsigned FIOperandNo = 0; 600 while (!MI.getOperand(FIOperandNo).isFrameIndex()) { 601 ++FIOperandNo; 602 assert(FIOperandNo != MI.getNumOperands() && 603 "Instr doesn't have FrameIndex operand!"); 604 } 605 // Take into account whether it's an add or mem instruction 606 unsigned OffsetOperandNo = (FIOperandNo == 2) ? 1 : 2; 607 if (MI.getOpcode() == TargetInstrInfo::INLINEASM) 608 OffsetOperandNo = FIOperandNo-1; 609 610 // Get the frame index. 611 int FrameIndex = MI.getOperand(FIOperandNo).getIndex(); 612 613 // Get the frame pointer save index. Users of this index are primarily 614 // DYNALLOC instructions. 615 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 616 int FPSI = FI->getFramePointerSaveIndex(); 617 // Get the instruction opcode. 618 unsigned OpC = MI.getOpcode(); 619 620 // Special case for dynamic alloca. 621 if (FPSI && FrameIndex == FPSI && 622 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { 623 lowerDynamicAlloc(II, SPAdj, RS); 624 return; 625 } 626 627 // Special case for pseudo-op SPILL_CR. 628 if (EnableRegisterScavenging) // FIXME (64-bit): Enable by default. 629 if (OpC == PPC::SPILL_CR) { 630 lowerCRSpilling(II, FrameIndex, SPAdj, RS); 631 return; 632 } 633 634 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 635 MI.getOperand(FIOperandNo).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1, 636 false); 637 638 // Figure out if the offset in the instruction is shifted right two bits. This 639 // is true for instructions like "STD", which the machine implicitly adds two 640 // low zeros to. 641 bool isIXAddr = false; 642 switch (OpC) { 643 case PPC::LWA: 644 case PPC::LD: 645 case PPC::STD: 646 case PPC::STD_32: 647 isIXAddr = true; 648 break; 649 } 650 651 // Now add the frame object offset to the offset from r1. 652 int Offset = MFI->getObjectOffset(FrameIndex); 653 if (!isIXAddr) 654 Offset += MI.getOperand(OffsetOperandNo).getImm(); 655 else 656 Offset += MI.getOperand(OffsetOperandNo).getImm() << 2; 657 658 // If we're not using a Frame Pointer that has been set to the value of the 659 // SP before having the stack size subtracted from it, then add the stack size 660 // to Offset to get the correct offset. 661 Offset += MFI->getStackSize(); 662 663 // If we can, encode the offset directly into the instruction. If this is a 664 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If 665 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits 666 // clear can be encoded. This is extremely uncommon, because normally you 667 // only "std" to a stack slot that is at least 4-byte aligned, but it can 668 // happen in invalid code. 669 if (isInt16(Offset) && (!isIXAddr || (Offset & 3) == 0)) { 670 if (isIXAddr) 671 Offset >>= 2; // The actual encoded value has the low two bits zero. 672 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 673 return; 674 } 675 676 // The offset doesn't fit into a single register, scavenge one to build the 677 // offset in. 678 // FIXME: figure out what SPAdj is doing here. 679 680 // FIXME (64-bit): Use "findScratchRegister". 681 unsigned SReg; 682 if (EnableRegisterScavenging) 683 SReg = findScratchRegister(II, RS, &PPC::GPRCRegClass, SPAdj); 684 else 685 SReg = PPC::R0; 686 687 // Insert a set of rA with the full offset value before the ld, st, or add 688 BuildMI(MBB, II, TII.get(PPC::LIS), SReg) 689 .addImm(Offset >> 16); 690 BuildMI(MBB, II, TII.get(PPC::ORI), SReg) 691 .addReg(SReg, false, false, true) 692 .addImm(Offset); 693 694 // Convert into indexed form of the instruction: 695 // 696 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 697 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 698 unsigned OperandBase; 699 700 if (OpC != TargetInstrInfo::INLINEASM) { 701 assert(ImmToIdxMap.count(OpC) && 702 "No indexed form of load or store available!"); 703 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; 704 MI.setDesc(TII.get(NewOpcode)); 705 OperandBase = 1; 706 } else { 707 OperandBase = OffsetOperandNo; 708 } 709 710 unsigned StackReg = MI.getOperand(FIOperandNo).getReg(); 711 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false); 712 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false); 713 } 714 715 /// VRRegNo - Map from a numbered VR register to its enum value. 716 /// 717 static const unsigned short VRRegNo[] = { 718 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 , 719 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, 720 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, 721 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31 722 }; 723 724 /// RemoveVRSaveCode - We have found that this function does not need any code 725 /// to manipulate the VRSAVE register, even though it uses vector registers. 726 /// This can happen when the only registers used are known to be live in or out 727 /// of the function. Remove all of the VRSAVE related code from the function. 728 static void RemoveVRSaveCode(MachineInstr *MI) { 729 MachineBasicBlock *Entry = MI->getParent(); 730 MachineFunction *MF = Entry->getParent(); 731 732 // We know that the MTVRSAVE instruction immediately follows MI. Remove it. 733 MachineBasicBlock::iterator MBBI = MI; 734 ++MBBI; 735 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE); 736 MBBI->eraseFromParent(); 737 738 bool RemovedAllMTVRSAVEs = true; 739 // See if we can find and remove the MTVRSAVE instruction from all of the 740 // epilog blocks. 741 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) { 742 // If last instruction is a return instruction, add an epilogue 743 if (!I->empty() && I->back().getDesc().isReturn()) { 744 bool FoundIt = false; 745 for (MBBI = I->end(); MBBI != I->begin(); ) { 746 --MBBI; 747 if (MBBI->getOpcode() == PPC::MTVRSAVE) { 748 MBBI->eraseFromParent(); // remove it. 749 FoundIt = true; 750 break; 751 } 752 } 753 RemovedAllMTVRSAVEs &= FoundIt; 754 } 755 } 756 757 // If we found and removed all MTVRSAVE instructions, remove the read of 758 // VRSAVE as well. 759 if (RemovedAllMTVRSAVEs) { 760 MBBI = MI; 761 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?"); 762 --MBBI; 763 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?"); 764 MBBI->eraseFromParent(); 765 } 766 767 // Finally, nuke the UPDATE_VRSAVE. 768 MI->eraseFromParent(); 769 } 770 771 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the 772 // instruction selector. Based on the vector registers that have been used, 773 // transform this into the appropriate ORI instruction. 774 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) { 775 MachineFunction *MF = MI->getParent()->getParent(); 776 777 unsigned UsedRegMask = 0; 778 for (unsigned i = 0; i != 32; ++i) 779 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i])) 780 UsedRegMask |= 1 << (31-i); 781 782 // Live in and live out values already must be in the mask, so don't bother 783 // marking them. 784 for (MachineRegisterInfo::livein_iterator 785 I = MF->getRegInfo().livein_begin(), 786 E = MF->getRegInfo().livein_end(); I != E; ++I) { 787 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first); 788 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg. 789 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 790 } 791 for (MachineRegisterInfo::liveout_iterator 792 I = MF->getRegInfo().liveout_begin(), 793 E = MF->getRegInfo().liveout_end(); I != E; ++I) { 794 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I); 795 if (VRRegNo[RegNo] == *I) // If this really is a vector reg. 796 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 797 } 798 799 // If no registers are used, turn this into a copy. 800 if (UsedRegMask == 0) { 801 // Remove all VRSAVE code. 802 RemoveVRSaveCode(MI); 803 return; 804 } 805 806 unsigned SrcReg = MI->getOperand(1).getReg(); 807 unsigned DstReg = MI->getOperand(0).getReg(); 808 809 if ((UsedRegMask & 0xFFFF) == UsedRegMask) { 810 if (DstReg != SrcReg) 811 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg) 812 .addReg(SrcReg) 813 .addImm(UsedRegMask); 814 else 815 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg) 816 .addReg(SrcReg, false, false, true) 817 .addImm(UsedRegMask); 818 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { 819 if (DstReg != SrcReg) 820 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) 821 .addReg(SrcReg) 822 .addImm(UsedRegMask >> 16); 823 else 824 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) 825 .addReg(SrcReg, false, false, true) 826 .addImm(UsedRegMask >> 16); 827 } else { 828 if (DstReg != SrcReg) 829 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) 830 .addReg(SrcReg) 831 .addImm(UsedRegMask >> 16); 832 else 833 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) 834 .addReg(SrcReg, false, false, true) 835 .addImm(UsedRegMask >> 16); 836 837 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg) 838 .addReg(DstReg, false, false, true) 839 .addImm(UsedRegMask & 0xFFFF); 840 } 841 842 // Remove the old UPDATE_VRSAVE instruction. 843 MI->eraseFromParent(); 844 } 845 846 /// determineFrameLayout - Determine the size of the frame and maximum call 847 /// frame size. 848 void PPCRegisterInfo::determineFrameLayout(MachineFunction &MF) const { 849 MachineFrameInfo *MFI = MF.getFrameInfo(); 850 851 // Get the number of bytes to allocate from the FrameInfo 852 unsigned FrameSize = MFI->getStackSize(); 853 854 // Get the alignments provided by the target, and the maximum alignment 855 // (if any) of the fixed frame objects. 856 unsigned MaxAlign = MFI->getMaxAlignment(); 857 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 858 unsigned AlignMask = TargetAlign - 1; // 859 860 // If we are a leaf function, and use up to 224 bytes of stack space, 861 // don't have a frame pointer, calls, or dynamic alloca then we do not need 862 // to adjust the stack pointer (we fit in the Red Zone). 863 if (FrameSize <= 224 && // Fits in red zone. 864 !MFI->hasVarSizedObjects() && // No dynamic alloca. 865 !MFI->hasCalls() && // No calls. 866 (!ALIGN_STACK || MaxAlign <= TargetAlign)) { // No special alignment. 867 // No need for frame 868 MFI->setStackSize(0); 869 return; 870 } 871 872 // Get the maximum call frame size of all the calls. 873 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 874 875 // Maximum call frame needs to be at least big enough for linkage and 8 args. 876 unsigned minCallFrameSize = 877 PPCFrameInfo::getMinCallFrameSize(Subtarget.isPPC64(), 878 Subtarget.isMachoABI()); 879 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize); 880 881 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so 882 // that allocations will be aligned. 883 if (MFI->hasVarSizedObjects()) 884 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask; 885 886 // Update maximum call frame size. 887 MFI->setMaxCallFrameSize(maxCallFrameSize); 888 889 // Include call frame size in total. 890 FrameSize += maxCallFrameSize; 891 892 // Make sure the frame is aligned. 893 FrameSize = (FrameSize + AlignMask) & ~AlignMask; 894 895 // Update frame info. 896 MFI->setStackSize(FrameSize); 897 } 898 899 void 900 PPCRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 901 RegScavenger *RS) const { 902 // Save and clear the LR state. 903 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 904 unsigned LR = getRARegister(); 905 FI->setUsesLR(MF.getRegInfo().isPhysRegUsed(LR)); 906 MF.getRegInfo().setPhysRegUnused(LR); 907 908 // Save R31 if necessary 909 int FPSI = FI->getFramePointerSaveIndex(); 910 bool IsPPC64 = Subtarget.isPPC64(); 911 bool IsELF32_ABI = Subtarget.isELF32_ABI(); 912 bool IsMachoABI = Subtarget.isMachoABI(); 913 MachineFrameInfo *MFI = MF.getFrameInfo(); 914 915 // If the frame pointer save index hasn't been defined yet. 916 if (!FPSI && (NoFramePointerElim || MFI->hasVarSizedObjects()) && 917 IsELF32_ABI) { 918 // Find out what the fix offset of the frame pointer save area. 919 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, 920 IsMachoABI); 921 // Allocate the frame index for frame pointer save area. 922 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset); 923 // Save the result. 924 FI->setFramePointerSaveIndex(FPSI); 925 } 926 927 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or 928 // a large stack, which will require scavenging a register to materialize a 929 // large offset. 930 // FIXME: this doesn't actually check stack size, so is a bit pessimistic 931 // FIXME: doesn't detect whether or not we need to spill vXX, which requires 932 // r0 for now. 933 934 if (EnableRegisterScavenging) // FIXME (64-bit): Enable. 935 if (needsFP(MF) || spillsCR(MF)) { 936 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 937 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 938 const TargetRegisterClass *RC = IsPPC64 ? G8RC : GPRC; 939 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 940 RC->getAlignment())); 941 } 942 } 943 944 void 945 PPCRegisterInfo::emitPrologue(MachineFunction &MF) const { 946 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB 947 MachineBasicBlock::iterator MBBI = MBB.begin(); 948 MachineFrameInfo *MFI = MF.getFrameInfo(); 949 MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); 950 bool needsFrameInfo = (MMI && MMI->hasDebugInfo()) || 951 !MF.getFunction()->doesNotThrow(); 952 953 // Prepare for frame info. 954 unsigned FrameLabelId = 0; 955 956 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it, 957 // process it. 958 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { 959 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) { 960 HandleVRSaveUpdate(MBBI, TII); 961 break; 962 } 963 } 964 965 // Move MBBI back to the beginning of the function. 966 MBBI = MBB.begin(); 967 968 // Work out frame sizes. 969 determineFrameLayout(MF); 970 unsigned FrameSize = MFI->getStackSize(); 971 972 int NegFrameSize = -FrameSize; 973 974 // Get processor type. 975 bool IsPPC64 = Subtarget.isPPC64(); 976 // Get operating system 977 bool IsMachoABI = Subtarget.isMachoABI(); 978 // Check if the link register (LR) has been used. 979 bool UsesLR = MustSaveLR(MF); 980 // Do we have a frame pointer for this function? 981 bool HasFP = hasFP(MF) && FrameSize; 982 983 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI); 984 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI); 985 986 if (IsPPC64) { 987 if (UsesLR) 988 BuildMI(MBB, MBBI, TII.get(PPC::MFLR8), PPC::X0); 989 990 if (HasFP) 991 BuildMI(MBB, MBBI, TII.get(PPC::STD)) 992 .addReg(PPC::X31) 993 .addImm(FPOffset/4) 994 .addReg(PPC::X1); 995 996 if (UsesLR) 997 BuildMI(MBB, MBBI, TII.get(PPC::STD)) 998 .addReg(PPC::X0) 999 .addImm(LROffset / 4) 1000 .addReg(PPC::X1); 1001 } else { 1002 if (UsesLR) 1003 BuildMI(MBB, MBBI, TII.get(PPC::MFLR), PPC::R0); 1004 1005 if (HasFP) 1006 BuildMI(MBB, MBBI, TII.get(PPC::STW)) 1007 .addReg(PPC::R31) 1008 .addImm(FPOffset) 1009 .addReg(PPC::R1); 1010 1011 if (UsesLR) 1012 BuildMI(MBB, MBBI, TII.get(PPC::STW)) 1013 .addReg(PPC::R0) 1014 .addImm(LROffset) 1015 .addReg(PPC::R1); 1016 } 1017 1018 // Skip if a leaf routine. 1019 if (!FrameSize) return; 1020 1021 // Get stack alignments. 1022 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 1023 unsigned MaxAlign = MFI->getMaxAlignment(); 1024 1025 if (needsFrameInfo) { 1026 // Mark effective beginning of when frame pointer becomes valid. 1027 FrameLabelId = MMI->NextLabelID(); 1028 BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(FrameLabelId).addImm(0); 1029 } 1030 1031 // Adjust stack pointer: r1 += NegFrameSize. 1032 // If there is a preferred stack alignment, align R1 now 1033 if (!IsPPC64) { 1034 // PPC32. 1035 if (ALIGN_STACK && MaxAlign > TargetAlign) { 1036 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!"); 1037 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!"); 1038 1039 BuildMI(MBB, MBBI, TII.get(PPC::RLWINM), PPC::R0) 1040 .addReg(PPC::R1) 1041 .addImm(0) 1042 .addImm(32 - Log2_32(MaxAlign)) 1043 .addImm(31); 1044 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC) ,PPC::R0) 1045 .addReg(PPC::R0, false, false, true) 1046 .addImm(NegFrameSize); 1047 BuildMI(MBB, MBBI, TII.get(PPC::STWUX)) 1048 .addReg(PPC::R1) 1049 .addReg(PPC::R1) 1050 .addReg(PPC::R0); 1051 } else if (isInt16(NegFrameSize)) { 1052 BuildMI(MBB, MBBI, TII.get(PPC::STWU), PPC::R1) 1053 .addReg(PPC::R1) 1054 .addImm(NegFrameSize) 1055 .addReg(PPC::R1); 1056 } else { 1057 BuildMI(MBB, MBBI, TII.get(PPC::LIS), PPC::R0) 1058 .addImm(NegFrameSize >> 16); 1059 BuildMI(MBB, MBBI, TII.get(PPC::ORI), PPC::R0) 1060 .addReg(PPC::R0, false, false, true) 1061 .addImm(NegFrameSize & 0xFFFF); 1062 BuildMI(MBB, MBBI, TII.get(PPC::STWUX)) 1063 .addReg(PPC::R1) 1064 .addReg(PPC::R1) 1065 .addReg(PPC::R0); 1066 } 1067 } else { // PPC64. 1068 if (ALIGN_STACK && MaxAlign > TargetAlign) { 1069 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!"); 1070 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!"); 1071 1072 BuildMI(MBB, MBBI, TII.get(PPC::RLDICL), PPC::X0) 1073 .addReg(PPC::X1) 1074 .addImm(0) 1075 .addImm(64 - Log2_32(MaxAlign)); 1076 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC8), PPC::X0) 1077 .addReg(PPC::X0) 1078 .addImm(NegFrameSize); 1079 BuildMI(MBB, MBBI, TII.get(PPC::STDUX)) 1080 .addReg(PPC::X1) 1081 .addReg(PPC::X1) 1082 .addReg(PPC::X0); 1083 } else if (isInt16(NegFrameSize)) { 1084 BuildMI(MBB, MBBI, TII.get(PPC::STDU), PPC::X1) 1085 .addReg(PPC::X1) 1086 .addImm(NegFrameSize / 4) 1087 .addReg(PPC::X1); 1088 } else { 1089 BuildMI(MBB, MBBI, TII.get(PPC::LIS8), PPC::X0) 1090 .addImm(NegFrameSize >> 16); 1091 BuildMI(MBB, MBBI, TII.get(PPC::ORI8), PPC::X0) 1092 .addReg(PPC::X0, false, false, true) 1093 .addImm(NegFrameSize & 0xFFFF); 1094 BuildMI(MBB, MBBI, TII.get(PPC::STDUX)) 1095 .addReg(PPC::X1) 1096 .addReg(PPC::X1) 1097 .addReg(PPC::X0); 1098 } 1099 } 1100 1101 if (needsFrameInfo) { 1102 std::vector<MachineMove> &Moves = MMI->getFrameMoves(); 1103 1104 if (NegFrameSize) { 1105 // Show update of SP. 1106 MachineLocation SPDst(MachineLocation::VirtualFP); 1107 MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize); 1108 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc)); 1109 } else { 1110 MachineLocation SP(IsPPC64 ? PPC::X31 : PPC::R31); 1111 Moves.push_back(MachineMove(FrameLabelId, SP, SP)); 1112 } 1113 1114 if (HasFP) { 1115 MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset); 1116 MachineLocation FPSrc(IsPPC64 ? PPC::X31 : PPC::R31); 1117 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc)); 1118 } 1119 1120 // Add callee saved registers to move list. 1121 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 1122 for (unsigned I = 0, E = CSI.size(); I != E; ++I) { 1123 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx()); 1124 unsigned Reg = CSI[I].getReg(); 1125 if (Reg == PPC::LR || Reg == PPC::LR8) continue; 1126 MachineLocation CSDst(MachineLocation::VirtualFP, Offset); 1127 MachineLocation CSSrc(Reg); 1128 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc)); 1129 } 1130 1131 MachineLocation LRDst(MachineLocation::VirtualFP, LROffset); 1132 MachineLocation LRSrc(IsPPC64 ? PPC::LR8 : PPC::LR); 1133 Moves.push_back(MachineMove(FrameLabelId, LRDst, LRSrc)); 1134 1135 // Mark effective beginning of when frame pointer is ready. 1136 unsigned ReadyLabelId = MMI->NextLabelID(); 1137 BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(ReadyLabelId).addImm(0); 1138 1139 MachineLocation FPDst(HasFP ? (IsPPC64 ? PPC::X31 : PPC::R31) : 1140 (IsPPC64 ? PPC::X1 : PPC::R1)); 1141 MachineLocation FPSrc(MachineLocation::VirtualFP); 1142 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc)); 1143 } 1144 1145 // If there is a frame pointer, copy R1 into R31 1146 if (HasFP) { 1147 if (!IsPPC64) { 1148 BuildMI(MBB, MBBI, TII.get(PPC::OR), PPC::R31) 1149 .addReg(PPC::R1) 1150 .addReg(PPC::R1); 1151 } else { 1152 BuildMI(MBB, MBBI, TII.get(PPC::OR8), PPC::X31) 1153 .addReg(PPC::X1) 1154 .addReg(PPC::X1); 1155 } 1156 } 1157 } 1158 1159 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF, 1160 MachineBasicBlock &MBB) const { 1161 MachineBasicBlock::iterator MBBI = prior(MBB.end()); 1162 assert(MBBI->getOpcode() == PPC::BLR && 1163 "Can only insert epilog into returning blocks"); 1164 1165 // Get alignment info so we know how to restore r1 1166 const MachineFrameInfo *MFI = MF.getFrameInfo(); 1167 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 1168 unsigned MaxAlign = MFI->getMaxAlignment(); 1169 1170 // Get the number of bytes allocated from the FrameInfo. 1171 unsigned FrameSize = MFI->getStackSize(); 1172 1173 // Get processor type. 1174 bool IsPPC64 = Subtarget.isPPC64(); 1175 // Get operating system 1176 bool IsMachoABI = Subtarget.isMachoABI(); 1177 // Check if the link register (LR) has been used. 1178 bool UsesLR = MustSaveLR(MF); 1179 // Do we have a frame pointer for this function? 1180 bool HasFP = hasFP(MF) && FrameSize; 1181 1182 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI); 1183 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI); 1184 1185 if (FrameSize) { 1186 // The loaded (or persistent) stack pointer value is offset by the 'stwu' 1187 // on entry to the function. Add this offset back now. 1188 if (!Subtarget.isPPC64()) { 1189 if (isInt16(FrameSize) && (!ALIGN_STACK || TargetAlign >= MaxAlign) && 1190 !MFI->hasVarSizedObjects()) { 1191 BuildMI(MBB, MBBI, TII.get(PPC::ADDI), PPC::R1) 1192 .addReg(PPC::R1).addImm(FrameSize); 1193 } else { 1194 BuildMI(MBB, MBBI, TII.get(PPC::LWZ),PPC::R1).addImm(0).addReg(PPC::R1); 1195 } 1196 } else { 1197 if (isInt16(FrameSize) && TargetAlign >= MaxAlign && 1198 !MFI->hasVarSizedObjects()) { 1199 BuildMI(MBB, MBBI, TII.get(PPC::ADDI8), PPC::X1) 1200 .addReg(PPC::X1).addImm(FrameSize); 1201 } else { 1202 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X1).addImm(0).addReg(PPC::X1); 1203 } 1204 } 1205 } 1206 1207 if (IsPPC64) { 1208 if (UsesLR) 1209 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X0) 1210 .addImm(LROffset/4).addReg(PPC::X1); 1211 1212 if (HasFP) 1213 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X31) 1214 .addImm(FPOffset/4).addReg(PPC::X1); 1215 1216 if (UsesLR) 1217 BuildMI(MBB, MBBI, TII.get(PPC::MTLR8)).addReg(PPC::X0); 1218 } else { 1219 if (UsesLR) 1220 BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R0) 1221 .addImm(LROffset).addReg(PPC::R1); 1222 1223 if (HasFP) 1224 BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R31) 1225 .addImm(FPOffset).addReg(PPC::R1); 1226 1227 if (UsesLR) 1228 BuildMI(MBB, MBBI, TII.get(PPC::MTLR)).addReg(PPC::R0); 1229 } 1230 } 1231 1232 unsigned PPCRegisterInfo::getRARegister() const { 1233 return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8; 1234 } 1235 1236 unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const { 1237 if (!Subtarget.isPPC64()) 1238 return hasFP(MF) ? PPC::R31 : PPC::R1; 1239 else 1240 return hasFP(MF) ? PPC::X31 : PPC::X1; 1241 } 1242 1243 void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) 1244 const { 1245 // Initial state of the frame pointer is R1. 1246 MachineLocation Dst(MachineLocation::VirtualFP); 1247 MachineLocation Src(PPC::R1, 0); 1248 Moves.push_back(MachineMove(0, Dst, Src)); 1249 } 1250 1251 unsigned PPCRegisterInfo::getEHExceptionRegister() const { 1252 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3; 1253 } 1254 1255 unsigned PPCRegisterInfo::getEHHandlerRegister() const { 1256 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4; 1257 } 1258 1259 int PPCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { 1260 // FIXME: Most probably dwarf numbers differs for Linux and Darwin 1261 return PPCGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); 1262 } 1263 1264 #include "PPCGenRegisterInfo.inc" 1265 1266