1 //===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the TargetRegisterInfo 11 // class. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "PPCRegisterInfo.h" 16 #include "PPC.h" 17 #include "PPCFrameLowering.h" 18 #include "PPCInstrBuilder.h" 19 #include "PPCMachineFunctionInfo.h" 20 #include "PPCSubtarget.h" 21 #include "llvm/ADT/BitVector.h" 22 #include "llvm/ADT/STLExtras.h" 23 #include "llvm/CodeGen/MachineFrameInfo.h" 24 #include "llvm/CodeGen/MachineFunction.h" 25 #include "llvm/CodeGen/MachineInstrBuilder.h" 26 #include "llvm/CodeGen/MachineModuleInfo.h" 27 #include "llvm/CodeGen/MachineRegisterInfo.h" 28 #include "llvm/CodeGen/RegisterScavenging.h" 29 #include "llvm/IR/CallingConv.h" 30 #include "llvm/IR/Constants.h" 31 #include "llvm/IR/Function.h" 32 #include "llvm/IR/Type.h" 33 #include "llvm/Support/CommandLine.h" 34 #include "llvm/Support/Debug.h" 35 #include "llvm/Support/ErrorHandling.h" 36 #include "llvm/Support/MathExtras.h" 37 #include "llvm/Support/raw_ostream.h" 38 #include "llvm/Target/TargetFrameLowering.h" 39 #include "llvm/Target/TargetInstrInfo.h" 40 #include "llvm/Target/TargetMachine.h" 41 #include "llvm/Target/TargetOptions.h" 42 #include <cstdlib> 43 44 using namespace llvm; 45 46 #define DEBUG_TYPE "reginfo" 47 48 #define GET_REGINFO_TARGET_DESC 49 #include "PPCGenRegisterInfo.inc" 50 51 static cl::opt<bool> 52 EnableBasePointer("ppc-use-base-pointer", cl::Hidden, cl::init(true), 53 cl::desc("Enable use of a base pointer for complex stack frames")); 54 55 static cl::opt<bool> 56 AlwaysBasePointer("ppc-always-use-base-pointer", cl::Hidden, cl::init(false), 57 cl::desc("Force the use of a base pointer in every function")); 58 59 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST) 60 : PPCGenRegisterInfo(ST.isPPC64() ? PPC::LR8 : PPC::LR, 61 ST.isPPC64() ? 0 : 1, 62 ST.isPPC64() ? 0 : 1), 63 Subtarget(ST) { 64 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 65 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 66 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 67 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 68 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 69 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 70 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 71 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 72 ImmToIdxMap[PPC::LWA_32] = PPC::LWAX_32; 73 74 // 64-bit 75 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8; 76 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8; 77 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8; 78 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX; 79 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; 80 } 81 82 /// getPointerRegClass - Return the register class to use to hold pointers. 83 /// This is used for addressing modes. 84 const TargetRegisterClass * 85 PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) 86 const { 87 // Note that PPCInstrInfo::FoldImmediate also directly uses this Kind value 88 // when it checks for ZERO folding. 89 if (Kind == 1) { 90 if (Subtarget.isPPC64()) 91 return &PPC::G8RC_NOX0RegClass; 92 return &PPC::GPRC_NOR0RegClass; 93 } 94 95 if (Subtarget.isPPC64()) 96 return &PPC::G8RCRegClass; 97 return &PPC::GPRCRegClass; 98 } 99 100 const MCPhysReg* 101 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 102 if (Subtarget.isDarwinABI()) 103 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ? 104 CSR_Darwin64_Altivec_SaveList : 105 CSR_Darwin64_SaveList) : 106 (Subtarget.hasAltivec() ? 107 CSR_Darwin32_Altivec_SaveList : 108 CSR_Darwin32_SaveList); 109 110 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ? 111 CSR_SVR464_Altivec_SaveList : 112 CSR_SVR464_SaveList) : 113 (Subtarget.hasAltivec() ? 114 CSR_SVR432_Altivec_SaveList : 115 CSR_SVR432_SaveList); 116 } 117 118 const uint32_t* 119 PPCRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const { 120 if (Subtarget.isDarwinABI()) 121 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ? 122 CSR_Darwin64_Altivec_RegMask : 123 CSR_Darwin64_RegMask) : 124 (Subtarget.hasAltivec() ? 125 CSR_Darwin32_Altivec_RegMask : 126 CSR_Darwin32_RegMask); 127 128 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ? 129 CSR_SVR464_Altivec_RegMask : 130 CSR_SVR464_RegMask) : 131 (Subtarget.hasAltivec() ? 132 CSR_SVR432_Altivec_RegMask : 133 CSR_SVR432_RegMask); 134 } 135 136 const uint32_t* 137 PPCRegisterInfo::getNoPreservedMask() const { 138 return CSR_NoRegs_RegMask; 139 } 140 141 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 142 BitVector Reserved(getNumRegs()); 143 const PPCFrameLowering *PPCFI = static_cast<const PPCFrameLowering *>( 144 MF.getSubtarget().getFrameLowering()); 145 146 // The ZERO register is not really a register, but the representation of r0 147 // when used in instructions that treat r0 as the constant 0. 148 Reserved.set(PPC::ZERO); 149 Reserved.set(PPC::ZERO8); 150 151 // The FP register is also not really a register, but is the representation 152 // of the frame pointer register used by ISD::FRAMEADDR. 153 Reserved.set(PPC::FP); 154 Reserved.set(PPC::FP8); 155 156 // The BP register is also not really a register, but is the representation 157 // of the base pointer register used by setjmp. 158 Reserved.set(PPC::BP); 159 Reserved.set(PPC::BP8); 160 161 // The counter registers must be reserved so that counter-based loops can 162 // be correctly formed (and the mtctr instructions are not DCE'd). 163 Reserved.set(PPC::CTR); 164 Reserved.set(PPC::CTR8); 165 166 Reserved.set(PPC::R1); 167 Reserved.set(PPC::LR); 168 Reserved.set(PPC::LR8); 169 Reserved.set(PPC::RM); 170 171 if (!Subtarget.isDarwinABI() || !Subtarget.hasAltivec()) 172 Reserved.set(PPC::VRSAVE); 173 174 // The SVR4 ABI reserves r2 and r13 175 if (Subtarget.isSVR4ABI()) { 176 Reserved.set(PPC::R2); // System-reserved register 177 Reserved.set(PPC::R13); // Small Data Area pointer register 178 } 179 180 // On PPC64, r13 is the thread pointer. Never allocate this register. 181 if (Subtarget.isPPC64()) { 182 Reserved.set(PPC::R13); 183 184 Reserved.set(PPC::X1); 185 Reserved.set(PPC::X13); 186 187 if (PPCFI->needsFP(MF)) 188 Reserved.set(PPC::X31); 189 190 if (hasBasePointer(MF)) 191 Reserved.set(PPC::X30); 192 193 // The 64-bit SVR4 ABI reserves r2 for the TOC pointer. 194 if (Subtarget.isSVR4ABI()) { 195 Reserved.set(PPC::X2); 196 } 197 } 198 199 if (PPCFI->needsFP(MF)) 200 Reserved.set(PPC::R31); 201 202 if (hasBasePointer(MF)) { 203 if (Subtarget.isSVR4ABI() && !Subtarget.isPPC64() && 204 MF.getTarget().getRelocationModel() == Reloc::PIC_) 205 Reserved.set(PPC::R29); 206 else 207 Reserved.set(PPC::R30); 208 } 209 210 if (Subtarget.isSVR4ABI() && !Subtarget.isPPC64() && 211 MF.getTarget().getRelocationModel() == Reloc::PIC_) 212 Reserved.set(PPC::R30); 213 214 // Reserve Altivec registers when Altivec is unavailable. 215 if (!Subtarget.hasAltivec()) 216 for (TargetRegisterClass::iterator I = PPC::VRRCRegClass.begin(), 217 IE = PPC::VRRCRegClass.end(); I != IE; ++I) 218 Reserved.set(*I); 219 220 return Reserved; 221 } 222 223 unsigned 224 PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 225 MachineFunction &MF) const { 226 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); 227 const unsigned DefaultSafety = 1; 228 229 switch (RC->getID()) { 230 default: 231 return 0; 232 case PPC::G8RC_NOX0RegClassID: 233 case PPC::GPRC_NOR0RegClassID: 234 case PPC::G8RCRegClassID: 235 case PPC::GPRCRegClassID: { 236 unsigned FP = TFI->hasFP(MF) ? 1 : 0; 237 return 32 - FP - DefaultSafety; 238 } 239 case PPC::F8RCRegClassID: 240 case PPC::F4RCRegClassID: 241 case PPC::VRRCRegClassID: 242 case PPC::VFRCRegClassID: 243 case PPC::VSLRCRegClassID: 244 case PPC::VSHRCRegClassID: 245 return 32 - DefaultSafety; 246 case PPC::VSRCRegClassID: 247 case PPC::VSFRCRegClassID: 248 return 64 - DefaultSafety; 249 case PPC::CRRCRegClassID: 250 return 8 - DefaultSafety; 251 } 252 } 253 254 const TargetRegisterClass* 255 PPCRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC)const { 256 if (Subtarget.hasVSX()) { 257 // With VSX, we can inflate various sub-register classes to the full VSX 258 // register set. 259 260 if (RC == &PPC::F8RCRegClass) 261 return &PPC::VSFRCRegClass; 262 else if (RC == &PPC::VRRCRegClass) 263 return &PPC::VSRCRegClass; 264 } 265 266 return TargetRegisterInfo::getLargestLegalSuperClass(RC); 267 } 268 269 //===----------------------------------------------------------------------===// 270 // Stack Frame Processing methods 271 //===----------------------------------------------------------------------===// 272 273 /// lowerDynamicAlloc - Generate the code for allocating an object in the 274 /// current frame. The sequence of code with be in the general form 275 /// 276 /// addi R0, SP, \#frameSize ; get the address of the previous frame 277 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size 278 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation 279 /// 280 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const { 281 // Get the instruction. 282 MachineInstr &MI = *II; 283 // Get the instruction's basic block. 284 MachineBasicBlock &MBB = *MI.getParent(); 285 // Get the basic block's function. 286 MachineFunction &MF = *MBB.getParent(); 287 // Get the frame info. 288 MachineFrameInfo *MFI = MF.getFrameInfo(); 289 // Get the instruction info. 290 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); 291 // Determine whether 64-bit pointers are used. 292 bool LP64 = Subtarget.isPPC64(); 293 DebugLoc dl = MI.getDebugLoc(); 294 295 // Get the maximum call stack size. 296 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 297 // Get the total frame size. 298 unsigned FrameSize = MFI->getStackSize(); 299 300 // Get stack alignments. 301 unsigned TargetAlign = MF.getTarget() 302 .getSubtargetImpl() 303 ->getFrameLowering() 304 ->getStackAlignment(); 305 unsigned MaxAlign = MFI->getMaxAlignment(); 306 assert((maxCallFrameSize & (MaxAlign-1)) == 0 && 307 "Maximum call-frame size not sufficiently aligned"); 308 309 // Determine the previous frame's address. If FrameSize can't be 310 // represented as 16 bits or we need special alignment, then we load the 311 // previous frame's address from 0(SP). Why not do an addis of the hi? 312 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. 313 // Constructing the constant and adding would take 3 instructions. 314 // Fortunately, a frame greater than 32K is rare. 315 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 316 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 317 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 318 319 if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) { 320 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) 321 .addReg(PPC::R31) 322 .addImm(FrameSize); 323 } else if (LP64) { 324 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg) 325 .addImm(0) 326 .addReg(PPC::X1); 327 } else { 328 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) 329 .addImm(0) 330 .addReg(PPC::R1); 331 } 332 333 bool KillNegSizeReg = MI.getOperand(1).isKill(); 334 unsigned NegSizeReg = MI.getOperand(1).getReg(); 335 336 // Grow the stack and update the stack pointer link, then determine the 337 // address of new allocated space. 338 if (LP64) { 339 if (MaxAlign > TargetAlign) { 340 unsigned UnalNegSizeReg = NegSizeReg; 341 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC); 342 343 // Unfortunately, there is no andi, only andi., and we can't insert that 344 // here because we might clobber cr0 while it is live. 345 BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg) 346 .addImm(~(MaxAlign-1)); 347 348 unsigned NegSizeReg1 = NegSizeReg; 349 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC); 350 BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg) 351 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg)) 352 .addReg(NegSizeReg1, RegState::Kill); 353 KillNegSizeReg = true; 354 } 355 356 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1) 357 .addReg(Reg, RegState::Kill) 358 .addReg(PPC::X1) 359 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg)); 360 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 361 .addReg(PPC::X1) 362 .addImm(maxCallFrameSize); 363 } else { 364 if (MaxAlign > TargetAlign) { 365 unsigned UnalNegSizeReg = NegSizeReg; 366 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); 367 368 // Unfortunately, there is no andi, only andi., and we can't insert that 369 // here because we might clobber cr0 while it is live. 370 BuildMI(MBB, II, dl, TII.get(PPC::LI), NegSizeReg) 371 .addImm(~(MaxAlign-1)); 372 373 unsigned NegSizeReg1 = NegSizeReg; 374 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); 375 BuildMI(MBB, II, dl, TII.get(PPC::AND), NegSizeReg) 376 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg)) 377 .addReg(NegSizeReg1, RegState::Kill); 378 KillNegSizeReg = true; 379 } 380 381 BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1) 382 .addReg(Reg, RegState::Kill) 383 .addReg(PPC::R1) 384 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg)); 385 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 386 .addReg(PPC::R1) 387 .addImm(maxCallFrameSize); 388 } 389 390 // Discard the DYNALLOC instruction. 391 MBB.erase(II); 392 } 393 394 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of 395 /// reserving a whole register (R0), we scrounge for one here. This generates 396 /// code like this: 397 /// 398 /// mfcr rA ; Move the conditional register into GPR rA. 399 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot. 400 /// stw rA, FI ; Store rA to the frame. 401 /// 402 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, 403 unsigned FrameIndex) const { 404 // Get the instruction. 405 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset> 406 // Get the instruction's basic block. 407 MachineBasicBlock &MBB = *MI.getParent(); 408 MachineFunction &MF = *MBB.getParent(); 409 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); 410 DebugLoc dl = MI.getDebugLoc(); 411 412 bool LP64 = Subtarget.isPPC64(); 413 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 414 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 415 416 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 417 unsigned SrcReg = MI.getOperand(0).getReg(); 418 419 // We need to store the CR in the low 4-bits of the saved value. First, issue 420 // an MFOCRF to save all of the CRBits and, if needed, kill the SrcReg. 421 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg) 422 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 423 424 // If the saved register wasn't CR0, shift the bits left so that they are in 425 // CR0's slot. 426 if (SrcReg != PPC::CR0) { 427 unsigned Reg1 = Reg; 428 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 429 430 // rlwinm rA, rA, ShiftBits, 0, 31. 431 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 432 .addReg(Reg1, RegState::Kill) 433 .addImm(getEncodingValue(SrcReg) * 4) 434 .addImm(0) 435 .addImm(31); 436 } 437 438 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW)) 439 .addReg(Reg, RegState::Kill), 440 FrameIndex); 441 442 // Discard the pseudo instruction. 443 MBB.erase(II); 444 } 445 446 void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II, 447 unsigned FrameIndex) const { 448 // Get the instruction. 449 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset> 450 // Get the instruction's basic block. 451 MachineBasicBlock &MBB = *MI.getParent(); 452 MachineFunction &MF = *MBB.getParent(); 453 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); 454 DebugLoc dl = MI.getDebugLoc(); 455 456 bool LP64 = Subtarget.isPPC64(); 457 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 458 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 459 460 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 461 unsigned DestReg = MI.getOperand(0).getReg(); 462 assert(MI.definesRegister(DestReg) && 463 "RESTORE_CR does not define its destination"); 464 465 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), 466 Reg), FrameIndex); 467 468 // If the reloaded register isn't CR0, shift the bits right so that they are 469 // in the right CR's slot. 470 if (DestReg != PPC::CR0) { 471 unsigned Reg1 = Reg; 472 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 473 474 unsigned ShiftBits = getEncodingValue(DestReg)*4; 475 // rlwinm r11, r11, 32-ShiftBits, 0, 31. 476 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 477 .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0) 478 .addImm(31); 479 } 480 481 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), DestReg) 482 .addReg(Reg, RegState::Kill); 483 484 // Discard the pseudo instruction. 485 MBB.erase(II); 486 } 487 488 static unsigned getCRFromCRBit(unsigned SrcReg) { 489 unsigned Reg = 0; 490 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT || 491 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN) 492 Reg = PPC::CR0; 493 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT || 494 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN) 495 Reg = PPC::CR1; 496 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT || 497 SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN) 498 Reg = PPC::CR2; 499 else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT || 500 SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN) 501 Reg = PPC::CR3; 502 else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT || 503 SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN) 504 Reg = PPC::CR4; 505 else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT || 506 SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN) 507 Reg = PPC::CR5; 508 else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT || 509 SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN) 510 Reg = PPC::CR6; 511 else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT || 512 SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN) 513 Reg = PPC::CR7; 514 515 assert(Reg != 0 && "Invalid CR bit register"); 516 return Reg; 517 } 518 519 void PPCRegisterInfo::lowerCRBitSpilling(MachineBasicBlock::iterator II, 520 unsigned FrameIndex) const { 521 // Get the instruction. 522 MachineInstr &MI = *II; // ; SPILL_CRBIT <SrcReg>, <offset> 523 // Get the instruction's basic block. 524 MachineBasicBlock &MBB = *MI.getParent(); 525 MachineFunction &MF = *MBB.getParent(); 526 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); 527 DebugLoc dl = MI.getDebugLoc(); 528 529 bool LP64 = Subtarget.isPPC64(); 530 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 531 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 532 533 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 534 unsigned SrcReg = MI.getOperand(0).getReg(); 535 536 BuildMI(MBB, II, dl, TII.get(TargetOpcode::KILL), 537 getCRFromCRBit(SrcReg)) 538 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 539 540 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg) 541 .addReg(getCRFromCRBit(SrcReg)); 542 543 // If the saved register wasn't CR0LT, shift the bits left so that the bit to 544 // store is the first one. Mask all but that bit. 545 unsigned Reg1 = Reg; 546 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 547 548 // rlwinm rA, rA, ShiftBits, 0, 0. 549 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 550 .addReg(Reg1, RegState::Kill) 551 .addImm(getEncodingValue(SrcReg)) 552 .addImm(0).addImm(0); 553 554 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW)) 555 .addReg(Reg, RegState::Kill), 556 FrameIndex); 557 558 // Discard the pseudo instruction. 559 MBB.erase(II); 560 } 561 562 void PPCRegisterInfo::lowerCRBitRestore(MachineBasicBlock::iterator II, 563 unsigned FrameIndex) const { 564 // Get the instruction. 565 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CRBIT <offset> 566 // Get the instruction's basic block. 567 MachineBasicBlock &MBB = *MI.getParent(); 568 MachineFunction &MF = *MBB.getParent(); 569 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); 570 DebugLoc dl = MI.getDebugLoc(); 571 572 bool LP64 = Subtarget.isPPC64(); 573 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 574 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 575 576 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 577 unsigned DestReg = MI.getOperand(0).getReg(); 578 assert(MI.definesRegister(DestReg) && 579 "RESTORE_CRBIT does not define its destination"); 580 581 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), 582 Reg), FrameIndex); 583 584 BuildMI(MBB, II, dl, TII.get(TargetOpcode::IMPLICIT_DEF), DestReg); 585 586 unsigned RegO = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 587 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), RegO) 588 .addReg(getCRFromCRBit(DestReg)); 589 590 unsigned ShiftBits = getEncodingValue(DestReg); 591 // rlwimi r11, r10, 32-ShiftBits, ..., ... 592 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWIMI8 : PPC::RLWIMI), RegO) 593 .addReg(RegO, RegState::Kill).addReg(Reg, RegState::Kill) 594 .addImm(ShiftBits ? 32-ShiftBits : 0) 595 .addImm(ShiftBits).addImm(ShiftBits); 596 597 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), 598 getCRFromCRBit(DestReg)) 599 .addReg(RegO, RegState::Kill) 600 // Make sure we have a use dependency all the way through this 601 // sequence of instructions. We can't have the other bits in the CR 602 // modified in between the mfocrf and the mtocrf. 603 .addReg(getCRFromCRBit(DestReg), RegState::Implicit); 604 605 // Discard the pseudo instruction. 606 MBB.erase(II); 607 } 608 609 void PPCRegisterInfo::lowerVRSAVESpilling(MachineBasicBlock::iterator II, 610 unsigned FrameIndex) const { 611 // Get the instruction. 612 MachineInstr &MI = *II; // ; SPILL_VRSAVE <SrcReg>, <offset> 613 // Get the instruction's basic block. 614 MachineBasicBlock &MBB = *MI.getParent(); 615 MachineFunction &MF = *MBB.getParent(); 616 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); 617 DebugLoc dl = MI.getDebugLoc(); 618 619 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 620 unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC); 621 unsigned SrcReg = MI.getOperand(0).getReg(); 622 623 BuildMI(MBB, II, dl, TII.get(PPC::MFVRSAVEv), Reg) 624 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 625 626 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::STW)) 627 .addReg(Reg, RegState::Kill), 628 FrameIndex); 629 630 // Discard the pseudo instruction. 631 MBB.erase(II); 632 } 633 634 void PPCRegisterInfo::lowerVRSAVERestore(MachineBasicBlock::iterator II, 635 unsigned FrameIndex) const { 636 // Get the instruction. 637 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_VRSAVE <offset> 638 // Get the instruction's basic block. 639 MachineBasicBlock &MBB = *MI.getParent(); 640 MachineFunction &MF = *MBB.getParent(); 641 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); 642 DebugLoc dl = MI.getDebugLoc(); 643 644 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 645 unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC); 646 unsigned DestReg = MI.getOperand(0).getReg(); 647 assert(MI.definesRegister(DestReg) && 648 "RESTORE_VRSAVE does not define its destination"); 649 650 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::LWZ), 651 Reg), FrameIndex); 652 653 BuildMI(MBB, II, dl, TII.get(PPC::MTVRSAVEv), DestReg) 654 .addReg(Reg, RegState::Kill); 655 656 // Discard the pseudo instruction. 657 MBB.erase(II); 658 } 659 660 bool 661 PPCRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF, 662 unsigned Reg, int &FrameIdx) const { 663 664 // For the nonvolatile condition registers (CR2, CR3, CR4) in an SVR4 665 // ABI, return true to prevent allocating an additional frame slot. 666 // For 64-bit, the CR save area is at SP+8; the value of FrameIdx = 0 667 // is arbitrary and will be subsequently ignored. For 32-bit, we have 668 // previously created the stack slot if needed, so return its FrameIdx. 669 if (Subtarget.isSVR4ABI() && PPC::CR2 <= Reg && Reg <= PPC::CR4) { 670 if (Subtarget.isPPC64()) 671 FrameIdx = 0; 672 else { 673 const PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 674 FrameIdx = FI->getCRSpillFrameIndex(); 675 } 676 return true; 677 } 678 return false; 679 } 680 681 // Figure out if the offset in the instruction must be a multiple of 4. 682 // This is true for instructions like "STD". 683 static bool usesIXAddr(const MachineInstr &MI) { 684 unsigned OpC = MI.getOpcode(); 685 686 switch (OpC) { 687 default: 688 return false; 689 case PPC::LWA: 690 case PPC::LWA_32: 691 case PPC::LD: 692 case PPC::STD: 693 return true; 694 } 695 } 696 697 // Return the OffsetOperandNo given the FIOperandNum (and the instruction). 698 static unsigned getOffsetONFromFION(const MachineInstr &MI, 699 unsigned FIOperandNum) { 700 // Take into account whether it's an add or mem instruction 701 unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2; 702 if (MI.isInlineAsm()) 703 OffsetOperandNo = FIOperandNum-1; 704 705 return OffsetOperandNo; 706 } 707 708 void 709 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 710 int SPAdj, unsigned FIOperandNum, 711 RegScavenger *RS) const { 712 assert(SPAdj == 0 && "Unexpected"); 713 714 // Get the instruction. 715 MachineInstr &MI = *II; 716 // Get the instruction's basic block. 717 MachineBasicBlock &MBB = *MI.getParent(); 718 // Get the basic block's function. 719 MachineFunction &MF = *MBB.getParent(); 720 // Get the instruction info. 721 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); 722 // Get the frame info. 723 MachineFrameInfo *MFI = MF.getFrameInfo(); 724 DebugLoc dl = MI.getDebugLoc(); 725 726 unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum); 727 728 // Get the frame index. 729 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 730 731 // Get the frame pointer save index. Users of this index are primarily 732 // DYNALLOC instructions. 733 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 734 int FPSI = FI->getFramePointerSaveIndex(); 735 // Get the instruction opcode. 736 unsigned OpC = MI.getOpcode(); 737 738 // Special case for dynamic alloca. 739 if (FPSI && FrameIndex == FPSI && 740 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { 741 lowerDynamicAlloc(II); 742 return; 743 } 744 745 // Special case for pseudo-ops SPILL_CR and RESTORE_CR, etc. 746 if (OpC == PPC::SPILL_CR) { 747 lowerCRSpilling(II, FrameIndex); 748 return; 749 } else if (OpC == PPC::RESTORE_CR) { 750 lowerCRRestore(II, FrameIndex); 751 return; 752 } else if (OpC == PPC::SPILL_CRBIT) { 753 lowerCRBitSpilling(II, FrameIndex); 754 return; 755 } else if (OpC == PPC::RESTORE_CRBIT) { 756 lowerCRBitRestore(II, FrameIndex); 757 return; 758 } else if (OpC == PPC::SPILL_VRSAVE) { 759 lowerVRSAVESpilling(II, FrameIndex); 760 return; 761 } else if (OpC == PPC::RESTORE_VRSAVE) { 762 lowerVRSAVERestore(II, FrameIndex); 763 return; 764 } 765 766 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 767 MI.getOperand(FIOperandNum).ChangeToRegister( 768 FrameIndex < 0 ? getBaseRegister(MF) : getFrameRegister(MF), false); 769 770 // Figure out if the offset in the instruction is shifted right two bits. 771 bool isIXAddr = usesIXAddr(MI); 772 773 // If the instruction is not present in ImmToIdxMap, then it has no immediate 774 // form (and must be r+r). 775 bool noImmForm = !MI.isInlineAsm() && !ImmToIdxMap.count(OpC); 776 777 // Now add the frame object offset to the offset from r1. 778 int Offset = MFI->getObjectOffset(FrameIndex); 779 Offset += MI.getOperand(OffsetOperandNo).getImm(); 780 781 // If we're not using a Frame Pointer that has been set to the value of the 782 // SP before having the stack size subtracted from it, then add the stack size 783 // to Offset to get the correct offset. 784 // Naked functions have stack size 0, although getStackSize may not reflect that 785 // because we didn't call all the pieces that compute it for naked functions. 786 if (!MF.getFunction()->getAttributes(). 787 hasAttribute(AttributeSet::FunctionIndex, Attribute::Naked)) { 788 if (!(hasBasePointer(MF) && FrameIndex < 0)) 789 Offset += MFI->getStackSize(); 790 } 791 792 // If we can, encode the offset directly into the instruction. If this is a 793 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If 794 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits 795 // clear can be encoded. This is extremely uncommon, because normally you 796 // only "std" to a stack slot that is at least 4-byte aligned, but it can 797 // happen in invalid code. 798 assert(OpC != PPC::DBG_VALUE && 799 "This should be handle in a target independent way"); 800 if (!noImmForm && isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0)) { 801 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 802 return; 803 } 804 805 // The offset doesn't fit into a single register, scavenge one to build the 806 // offset in. 807 808 bool is64Bit = Subtarget.isPPC64(); 809 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 810 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 811 const TargetRegisterClass *RC = is64Bit ? G8RC : GPRC; 812 unsigned SRegHi = MF.getRegInfo().createVirtualRegister(RC), 813 SReg = MF.getRegInfo().createVirtualRegister(RC); 814 815 // Insert a set of rA with the full offset value before the ld, st, or add 816 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SRegHi) 817 .addImm(Offset >> 16); 818 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg) 819 .addReg(SRegHi, RegState::Kill) 820 .addImm(Offset); 821 822 // Convert into indexed form of the instruction: 823 // 824 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 825 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 826 unsigned OperandBase; 827 828 if (noImmForm) 829 OperandBase = 1; 830 else if (OpC != TargetOpcode::INLINEASM) { 831 assert(ImmToIdxMap.count(OpC) && 832 "No indexed form of load or store available!"); 833 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; 834 MI.setDesc(TII.get(NewOpcode)); 835 OperandBase = 1; 836 } else { 837 OperandBase = OffsetOperandNo; 838 } 839 840 unsigned StackReg = MI.getOperand(FIOperandNum).getReg(); 841 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false); 842 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true); 843 } 844 845 unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 846 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); 847 848 if (!Subtarget.isPPC64()) 849 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1; 850 else 851 return TFI->hasFP(MF) ? PPC::X31 : PPC::X1; 852 } 853 854 unsigned PPCRegisterInfo::getBaseRegister(const MachineFunction &MF) const { 855 if (!hasBasePointer(MF)) 856 return getFrameRegister(MF); 857 858 if (Subtarget.isPPC64()) 859 return PPC::X30; 860 861 if (Subtarget.isSVR4ABI() && 862 MF.getTarget().getRelocationModel() == Reloc::PIC_) 863 return PPC::R29; 864 865 return PPC::R30; 866 } 867 868 bool PPCRegisterInfo::hasBasePointer(const MachineFunction &MF) const { 869 if (!EnableBasePointer) 870 return false; 871 if (AlwaysBasePointer) 872 return true; 873 874 // If we need to realign the stack, then the stack pointer can no longer 875 // serve as an offset into the caller's stack space. As a result, we need a 876 // base pointer. 877 return needsStackRealignment(MF); 878 } 879 880 bool PPCRegisterInfo::canRealignStack(const MachineFunction &MF) const { 881 if (MF.getFunction()->hasFnAttribute("no-realign-stack")) 882 return false; 883 884 return true; 885 } 886 887 bool PPCRegisterInfo::needsStackRealignment(const MachineFunction &MF) const { 888 const MachineFrameInfo *MFI = MF.getFrameInfo(); 889 const Function *F = MF.getFunction(); 890 unsigned StackAlign = MF.getTarget() 891 .getSubtargetImpl() 892 ->getFrameLowering() 893 ->getStackAlignment(); 894 bool requiresRealignment = 895 ((MFI->getMaxAlignment() > StackAlign) || 896 F->getAttributes().hasAttribute(AttributeSet::FunctionIndex, 897 Attribute::StackAlignment)); 898 899 return requiresRealignment && canRealignStack(MF); 900 } 901 902 /// Returns true if the instruction's frame index 903 /// reference would be better served by a base register other than FP 904 /// or SP. Used by LocalStackFrameAllocation to determine which frame index 905 /// references it should create new base registers for. 906 bool PPCRegisterInfo:: 907 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { 908 assert(Offset < 0 && "Local offset must be negative"); 909 910 // It's the load/store FI references that cause issues, as it can be difficult 911 // to materialize the offset if it won't fit in the literal field. Estimate 912 // based on the size of the local frame and some conservative assumptions 913 // about the rest of the stack frame (note, this is pre-regalloc, so 914 // we don't know everything for certain yet) whether this offset is likely 915 // to be out of range of the immediate. Return true if so. 916 917 // We only generate virtual base registers for loads and stores that have 918 // an r+i form. Return false for everything else. 919 unsigned OpC = MI->getOpcode(); 920 if (!ImmToIdxMap.count(OpC)) 921 return false; 922 923 // Don't generate a new virtual base register just to add zero to it. 924 if ((OpC == PPC::ADDI || OpC == PPC::ADDI8) && 925 MI->getOperand(2).getImm() == 0) 926 return false; 927 928 MachineBasicBlock &MBB = *MI->getParent(); 929 MachineFunction &MF = *MBB.getParent(); 930 931 const PPCFrameLowering *PPCFI = static_cast<const PPCFrameLowering *>( 932 MF.getSubtarget().getFrameLowering()); 933 unsigned StackEst = 934 PPCFI->determineFrameLayout(MF, false, true); 935 936 // If we likely don't need a stack frame, then we probably don't need a 937 // virtual base register either. 938 if (!StackEst) 939 return false; 940 941 // Estimate an offset from the stack pointer. 942 // The incoming offset is relating to the SP at the start of the function, 943 // but when we access the local it'll be relative to the SP after local 944 // allocation, so adjust our SP-relative offset by that allocation size. 945 Offset += StackEst; 946 947 // The frame pointer will point to the end of the stack, so estimate the 948 // offset as the difference between the object offset and the FP location. 949 return !isFrameOffsetLegal(MI, Offset); 950 } 951 952 /// Insert defining instruction(s) for BaseReg to 953 /// be a pointer to FrameIdx at the beginning of the basic block. 954 void PPCRegisterInfo:: 955 materializeFrameBaseRegister(MachineBasicBlock *MBB, 956 unsigned BaseReg, int FrameIdx, 957 int64_t Offset) const { 958 unsigned ADDriOpc = Subtarget.isPPC64() ? PPC::ADDI8 : PPC::ADDI; 959 960 MachineBasicBlock::iterator Ins = MBB->begin(); 961 DebugLoc DL; // Defaults to "unknown" 962 if (Ins != MBB->end()) 963 DL = Ins->getDebugLoc(); 964 965 const MachineFunction &MF = *MBB->getParent(); 966 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); 967 const MCInstrDesc &MCID = TII.get(ADDriOpc); 968 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 969 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); 970 971 BuildMI(*MBB, Ins, DL, MCID, BaseReg) 972 .addFrameIndex(FrameIdx).addImm(Offset); 973 } 974 975 void PPCRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, 976 int64_t Offset) const { 977 unsigned FIOperandNum = 0; 978 while (!MI.getOperand(FIOperandNum).isFI()) { 979 ++FIOperandNum; 980 assert(FIOperandNum < MI.getNumOperands() && 981 "Instr doesn't have FrameIndex operand!"); 982 } 983 984 MI.getOperand(FIOperandNum).ChangeToRegister(BaseReg, false); 985 unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum); 986 Offset += MI.getOperand(OffsetOperandNo).getImm(); 987 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 988 989 MachineBasicBlock &MBB = *MI.getParent(); 990 MachineFunction &MF = *MBB.getParent(); 991 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); 992 const MCInstrDesc &MCID = MI.getDesc(); 993 MachineRegisterInfo &MRI = MF.getRegInfo(); 994 MRI.constrainRegClass(BaseReg, 995 TII.getRegClass(MCID, FIOperandNum, this, MF)); 996 } 997 998 bool PPCRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, 999 int64_t Offset) const { 1000 unsigned FIOperandNum = 0; 1001 while (!MI->getOperand(FIOperandNum).isFI()) { 1002 ++FIOperandNum; 1003 assert(FIOperandNum < MI->getNumOperands() && 1004 "Instr doesn't have FrameIndex operand!"); 1005 } 1006 1007 unsigned OffsetOperandNo = getOffsetONFromFION(*MI, FIOperandNum); 1008 Offset += MI->getOperand(OffsetOperandNo).getImm(); 1009 1010 return MI->getOpcode() == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm 1011 (isInt<16>(Offset) && (!usesIXAddr(*MI) || (Offset & 3) == 0)); 1012 } 1013 1014