1 //===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the TargetRegisterInfo 11 // class. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #define DEBUG_TYPE "reginfo" 16 #include "PPCRegisterInfo.h" 17 #include "PPC.h" 18 #include "PPCFrameLowering.h" 19 #include "PPCInstrBuilder.h" 20 #include "PPCMachineFunctionInfo.h" 21 #include "PPCSubtarget.h" 22 #include "llvm/ADT/BitVector.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/CodeGen/MachineFrameInfo.h" 25 #include "llvm/CodeGen/MachineFunction.h" 26 #include "llvm/CodeGen/MachineInstrBuilder.h" 27 #include "llvm/CodeGen/MachineModuleInfo.h" 28 #include "llvm/CodeGen/MachineRegisterInfo.h" 29 #include "llvm/CodeGen/RegisterScavenging.h" 30 #include "llvm/CodeGen/ValueTypes.h" 31 #include "llvm/IR/CallingConv.h" 32 #include "llvm/IR/Constants.h" 33 #include "llvm/IR/Function.h" 34 #include "llvm/IR/Type.h" 35 #include "llvm/Support/CommandLine.h" 36 #include "llvm/Support/Debug.h" 37 #include "llvm/Support/ErrorHandling.h" 38 #include "llvm/Support/MathExtras.h" 39 #include "llvm/Support/raw_ostream.h" 40 #include "llvm/Target/TargetFrameLowering.h" 41 #include "llvm/Target/TargetInstrInfo.h" 42 #include "llvm/Target/TargetMachine.h" 43 #include "llvm/Target/TargetOptions.h" 44 #include <cstdlib> 45 46 #define GET_REGINFO_TARGET_DESC 47 #include "PPCGenRegisterInfo.inc" 48 49 using namespace llvm; 50 51 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST, 52 const TargetInstrInfo &tii) 53 : PPCGenRegisterInfo(ST.isPPC64() ? PPC::LR8 : PPC::LR, 54 ST.isPPC64() ? 0 : 1, 55 ST.isPPC64() ? 0 : 1), 56 Subtarget(ST), TII(tii) { 57 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 58 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 59 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 60 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 61 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 62 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 63 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 64 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 65 66 // 64-bit 67 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8; 68 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8; 69 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8; 70 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX; 71 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32; 72 } 73 74 /// getPointerRegClass - Return the register class to use to hold pointers. 75 /// This is used for addressing modes. 76 const TargetRegisterClass * 77 PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) 78 const { 79 if (Kind == 1) { 80 if (Subtarget.isPPC64()) 81 return &PPC::G8RC_NOX0RegClass; 82 return &PPC::GPRC_NOR0RegClass; 83 } 84 85 if (Subtarget.isPPC64()) 86 return &PPC::G8RCRegClass; 87 return &PPC::GPRCRegClass; 88 } 89 90 const uint16_t* 91 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 92 if (Subtarget.isDarwinABI()) 93 return Subtarget.isPPC64() ? CSR_Darwin64_SaveList : 94 CSR_Darwin32_SaveList; 95 96 return Subtarget.isPPC64() ? CSR_SVR464_SaveList : CSR_SVR432_SaveList; 97 } 98 99 const uint32_t* 100 PPCRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const { 101 if (Subtarget.isDarwinABI()) 102 return Subtarget.isPPC64() ? CSR_Darwin64_RegMask : 103 CSR_Darwin32_RegMask; 104 105 return Subtarget.isPPC64() ? CSR_SVR464_RegMask : CSR_SVR432_RegMask; 106 } 107 108 const uint32_t* 109 PPCRegisterInfo::getNoPreservedMask() const { 110 // The naming here is inverted: The CSR_NoRegs_Altivec has the 111 // Altivec registers masked so that they're not saved and restored around 112 // instructions with this preserved mask. 113 114 if (!Subtarget.hasAltivec()) 115 return CSR_NoRegs_Altivec_RegMask; 116 117 return CSR_NoRegs_RegMask; 118 } 119 120 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 121 BitVector Reserved(getNumRegs()); 122 const PPCFrameLowering *PPCFI = 123 static_cast<const PPCFrameLowering*>(MF.getTarget().getFrameLowering()); 124 125 // The ZERO register is not really a register, but the representation of r0 126 // when used in instructions that treat r0 as the constant 0. 127 Reserved.set(PPC::ZERO); 128 Reserved.set(PPC::ZERO8); 129 130 // The FP register is also not really a register, but is the representation 131 // of the frame pointer register used by ISD::FRAMEADDR. 132 Reserved.set(PPC::FP); 133 Reserved.set(PPC::FP8); 134 135 Reserved.set(PPC::R0); 136 Reserved.set(PPC::R1); 137 Reserved.set(PPC::LR); 138 Reserved.set(PPC::LR8); 139 Reserved.set(PPC::RM); 140 141 // The SVR4 ABI reserves r2 and r13 142 if (Subtarget.isSVR4ABI()) { 143 Reserved.set(PPC::R2); // System-reserved register 144 Reserved.set(PPC::R13); // Small Data Area pointer register 145 } 146 147 // On PPC64, r13 is the thread pointer. Never allocate this register. 148 if (Subtarget.isPPC64()) { 149 Reserved.set(PPC::R13); 150 151 Reserved.set(PPC::X0); 152 Reserved.set(PPC::X1); 153 Reserved.set(PPC::X13); 154 155 if (PPCFI->needsFP(MF)) 156 Reserved.set(PPC::X31); 157 158 // The 64-bit SVR4 ABI reserves r2 for the TOC pointer. 159 if (Subtarget.isSVR4ABI()) { 160 Reserved.set(PPC::X2); 161 } 162 } 163 164 if (PPCFI->needsFP(MF)) 165 Reserved.set(PPC::R31); 166 167 return Reserved; 168 } 169 170 unsigned 171 PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 172 MachineFunction &MF) const { 173 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 174 const unsigned DefaultSafety = 1; 175 176 switch (RC->getID()) { 177 default: 178 return 0; 179 case PPC::G8RC_NOX0RegClassID: 180 case PPC::GPRC_NOR0RegClassID: 181 case PPC::G8RCRegClassID: 182 case PPC::GPRCRegClassID: { 183 unsigned FP = TFI->hasFP(MF) ? 1 : 0; 184 return 32 - FP - DefaultSafety; 185 } 186 case PPC::F8RCRegClassID: 187 case PPC::F4RCRegClassID: 188 case PPC::VRRCRegClassID: 189 return 32 - DefaultSafety; 190 case PPC::CRRCRegClassID: 191 return 8 - DefaultSafety; 192 } 193 } 194 195 //===----------------------------------------------------------------------===// 196 // Stack Frame Processing methods 197 //===----------------------------------------------------------------------===// 198 199 /// lowerDynamicAlloc - Generate the code for allocating an object in the 200 /// current frame. The sequence of code with be in the general form 201 /// 202 /// addi R0, SP, \#frameSize ; get the address of the previous frame 203 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size 204 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation 205 /// 206 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II, 207 int SPAdj, RegScavenger *RS) const { 208 // Get the instruction. 209 MachineInstr &MI = *II; 210 // Get the instruction's basic block. 211 MachineBasicBlock &MBB = *MI.getParent(); 212 // Get the basic block's function. 213 MachineFunction &MF = *MBB.getParent(); 214 // Get the frame info. 215 MachineFrameInfo *MFI = MF.getFrameInfo(); 216 // Determine whether 64-bit pointers are used. 217 bool LP64 = Subtarget.isPPC64(); 218 DebugLoc dl = MI.getDebugLoc(); 219 220 // Get the maximum call stack size. 221 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 222 // Get the total frame size. 223 unsigned FrameSize = MFI->getStackSize(); 224 225 // Get stack alignments. 226 unsigned TargetAlign = MF.getTarget().getFrameLowering()->getStackAlignment(); 227 unsigned MaxAlign = MFI->getMaxAlignment(); 228 if (MaxAlign > TargetAlign) 229 report_fatal_error("Dynamic alloca with large aligns not supported"); 230 231 // Determine the previous frame's address. If FrameSize can't be 232 // represented as 16 bits or we need special alignment, then we load the 233 // previous frame's address from 0(SP). Why not do an addis of the hi? 234 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. 235 // Constructing the constant and adding would take 3 instructions. 236 // Fortunately, a frame greater than 32K is rare. 237 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 238 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 239 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 240 241 if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) { 242 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) 243 .addReg(PPC::R31) 244 .addImm(FrameSize); 245 } else if (LP64) { 246 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg) 247 .addImm(0) 248 .addReg(PPC::X1); 249 } else { 250 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) 251 .addImm(0) 252 .addReg(PPC::R1); 253 } 254 255 // Grow the stack and update the stack pointer link, then determine the 256 // address of new allocated space. 257 if (LP64) { 258 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1) 259 .addReg(Reg, RegState::Kill) 260 .addReg(PPC::X1) 261 .addReg(MI.getOperand(1).getReg()); 262 if (!MI.getOperand(1).isKill()) 263 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 264 .addReg(PPC::X1) 265 .addImm(maxCallFrameSize); 266 else 267 // Implicitly kill the register. 268 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 269 .addReg(PPC::X1) 270 .addImm(maxCallFrameSize) 271 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill); 272 } else { 273 BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1) 274 .addReg(Reg, RegState::Kill) 275 .addReg(PPC::R1) 276 .addReg(MI.getOperand(1).getReg()); 277 278 if (!MI.getOperand(1).isKill()) 279 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 280 .addReg(PPC::R1) 281 .addImm(maxCallFrameSize); 282 else 283 // Implicitly kill the register. 284 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 285 .addReg(PPC::R1) 286 .addImm(maxCallFrameSize) 287 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill); 288 } 289 290 // Discard the DYNALLOC instruction. 291 MBB.erase(II); 292 } 293 294 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of 295 /// reserving a whole register (R0), we scrounge for one here. This generates 296 /// code like this: 297 /// 298 /// mfcr rA ; Move the conditional register into GPR rA. 299 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot. 300 /// stw rA, FI ; Store rA to the frame. 301 /// 302 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, 303 unsigned FrameIndex, int SPAdj, 304 RegScavenger *RS) const { 305 // Get the instruction. 306 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset> 307 // Get the instruction's basic block. 308 MachineBasicBlock &MBB = *MI.getParent(); 309 DebugLoc dl = MI.getDebugLoc(); 310 311 // FIXME: Once LLVM supports creating virtual registers here, or the register 312 // scavenger can return multiple registers, stop using reserved registers 313 // here. 314 (void) SPAdj; 315 (void) RS; 316 317 bool LP64 = Subtarget.isPPC64(); 318 unsigned Reg = LP64 ? PPC::X0 : PPC::R0; 319 unsigned SrcReg = MI.getOperand(0).getReg(); 320 321 // We need to store the CR in the low 4-bits of the saved value. First, issue 322 // an MFCRpsued to save all of the CRBits and, if needed, kill the SrcReg. 323 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFCR8pseud : PPC::MFCRpseud), Reg) 324 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 325 326 // If the saved register wasn't CR0, shift the bits left so that they are in 327 // CR0's slot. 328 if (SrcReg != PPC::CR0) 329 // rlwinm rA, rA, ShiftBits, 0, 31. 330 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 331 .addReg(Reg, RegState::Kill) 332 .addImm(getPPCRegisterNumbering(SrcReg) * 4) 333 .addImm(0) 334 .addImm(31); 335 336 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW)) 337 .addReg(Reg, getKillRegState(MI.getOperand(1).getImm())), 338 FrameIndex); 339 340 // Discard the pseudo instruction. 341 MBB.erase(II); 342 } 343 344 void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II, 345 unsigned FrameIndex, int SPAdj, 346 RegScavenger *RS) const { 347 // Get the instruction. 348 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset> 349 // Get the instruction's basic block. 350 MachineBasicBlock &MBB = *MI.getParent(); 351 DebugLoc dl = MI.getDebugLoc(); 352 353 // FIXME: Once LLVM supports creating virtual registers here, or the register 354 // scavenger can return multiple registers, stop using reserved registers 355 // here. 356 (void) SPAdj; 357 (void) RS; 358 359 bool LP64 = Subtarget.isPPC64(); 360 unsigned Reg = LP64 ? PPC::X0 : PPC::R0; 361 unsigned DestReg = MI.getOperand(0).getReg(); 362 assert(MI.definesRegister(DestReg) && 363 "RESTORE_CR does not define its destination"); 364 365 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), 366 Reg), FrameIndex); 367 368 // If the reloaded register isn't CR0, shift the bits right so that they are 369 // in the right CR's slot. 370 if (DestReg != PPC::CR0) { 371 unsigned ShiftBits = getPPCRegisterNumbering(DestReg)*4; 372 // rlwinm r11, r11, 32-ShiftBits, 0, 31. 373 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 374 .addReg(Reg).addImm(32-ShiftBits).addImm(0) 375 .addImm(31); 376 } 377 378 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTCRF8 : PPC::MTCRF), DestReg) 379 .addReg(Reg); 380 381 // Discard the pseudo instruction. 382 MBB.erase(II); 383 } 384 385 void PPCRegisterInfo::lowerVRSAVESpilling(MachineBasicBlock::iterator II, 386 unsigned FrameIndex, int SPAdj, 387 RegScavenger *RS) const { 388 // Get the instruction. 389 MachineInstr &MI = *II; // ; SPILL_VRSAVE <SrcReg>, <offset> 390 // Get the instruction's basic block. 391 MachineBasicBlock &MBB = *MI.getParent(); 392 DebugLoc dl = MI.getDebugLoc(); 393 394 // FIXME: Once LLVM supports creating virtual registers here, or the register 395 // scavenger can return multiple registers, stop using reserved registers 396 // here. 397 (void) SPAdj; 398 (void) RS; 399 400 unsigned Reg = PPC::R0; 401 unsigned SrcReg = MI.getOperand(0).getReg(); 402 403 BuildMI(MBB, II, dl, TII.get(PPC::MFVRSAVEv), Reg) 404 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 405 406 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::STW)) 407 .addReg(Reg, getKillRegState(MI.getOperand(1).getImm())), 408 FrameIndex); 409 410 // Discard the pseudo instruction. 411 MBB.erase(II); 412 } 413 414 void PPCRegisterInfo::lowerVRSAVERestore(MachineBasicBlock::iterator II, 415 unsigned FrameIndex, int SPAdj, 416 RegScavenger *RS) const { 417 // Get the instruction. 418 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_VRSAVE <offset> 419 // Get the instruction's basic block. 420 MachineBasicBlock &MBB = *MI.getParent(); 421 DebugLoc dl = MI.getDebugLoc(); 422 423 // FIXME: Once LLVM supports creating virtual registers here, or the register 424 // scavenger can return multiple registers, stop using reserved registers 425 // here. 426 (void) SPAdj; 427 (void) RS; 428 429 unsigned Reg = PPC::R0; 430 unsigned DestReg = MI.getOperand(0).getReg(); 431 assert(MI.definesRegister(DestReg) && 432 "RESTORE_VRSAVE does not define its destination"); 433 434 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::LWZ), 435 Reg), FrameIndex); 436 437 BuildMI(MBB, II, dl, TII.get(PPC::MTVRSAVEv), DestReg) 438 .addReg(Reg); 439 440 // Discard the pseudo instruction. 441 MBB.erase(II); 442 } 443 444 bool 445 PPCRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF, 446 unsigned Reg, int &FrameIdx) const { 447 448 // For the nonvolatile condition registers (CR2, CR3, CR4) in an SVR4 449 // ABI, return true to prevent allocating an additional frame slot. 450 // For 64-bit, the CR save area is at SP+8; the value of FrameIdx = 0 451 // is arbitrary and will be subsequently ignored. For 32-bit, we have 452 // previously created the stack slot if needed, so return its FrameIdx. 453 if (Subtarget.isSVR4ABI() && PPC::CR2 <= Reg && Reg <= PPC::CR4) { 454 if (Subtarget.isPPC64()) 455 FrameIdx = 0; 456 else { 457 const PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 458 FrameIdx = FI->getCRSpillFrameIndex(); 459 } 460 return true; 461 } 462 return false; 463 } 464 465 void 466 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 467 int SPAdj, unsigned FIOperandNum, 468 RegScavenger *RS) const { 469 assert(SPAdj == 0 && "Unexpected"); 470 471 // Get the instruction. 472 MachineInstr &MI = *II; 473 // Get the instruction's basic block. 474 MachineBasicBlock &MBB = *MI.getParent(); 475 // Get the basic block's function. 476 MachineFunction &MF = *MBB.getParent(); 477 // Get the frame info. 478 MachineFrameInfo *MFI = MF.getFrameInfo(); 479 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 480 DebugLoc dl = MI.getDebugLoc(); 481 482 // Take into account whether it's an add or mem instruction 483 unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2; 484 if (MI.isInlineAsm()) 485 OffsetOperandNo = FIOperandNum-1; 486 487 // Get the frame index. 488 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 489 490 // Get the frame pointer save index. Users of this index are primarily 491 // DYNALLOC instructions. 492 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 493 int FPSI = FI->getFramePointerSaveIndex(); 494 // Get the instruction opcode. 495 unsigned OpC = MI.getOpcode(); 496 497 // Special case for dynamic alloca. 498 if (FPSI && FrameIndex == FPSI && 499 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { 500 lowerDynamicAlloc(II, SPAdj, RS); 501 return; 502 } 503 504 // Special case for pseudo-ops SPILL_CR and RESTORE_CR, etc. 505 if (OpC == PPC::SPILL_CR) { 506 lowerCRSpilling(II, FrameIndex, SPAdj, RS); 507 return; 508 } else if (OpC == PPC::RESTORE_CR) { 509 lowerCRRestore(II, FrameIndex, SPAdj, RS); 510 return; 511 } else if (OpC == PPC::SPILL_VRSAVE) { 512 lowerVRSAVESpilling(II, FrameIndex, SPAdj, RS); 513 return; 514 } else if (OpC == PPC::RESTORE_VRSAVE) { 515 lowerVRSAVERestore(II, FrameIndex, SPAdj, RS); 516 return; 517 } 518 519 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 520 521 bool is64Bit = Subtarget.isPPC64(); 522 MI.getOperand(FIOperandNum).ChangeToRegister(TFI->hasFP(MF) ? 523 (is64Bit ? PPC::X31 : PPC::R31) : 524 (is64Bit ? PPC::X1 : PPC::R1), 525 false); 526 527 // Figure out if the offset in the instruction is shifted right two bits. This 528 // is true for instructions like "STD", which the machine implicitly adds two 529 // low zeros to. 530 bool isIXAddr = false; 531 switch (OpC) { 532 case PPC::LWA: 533 case PPC::LD: 534 case PPC::STD: 535 case PPC::STD_32: 536 isIXAddr = true; 537 break; 538 } 539 540 bool noImmForm = false; 541 switch (OpC) { 542 case PPC::LVEBX: 543 case PPC::LVEHX: 544 case PPC::LVEWX: 545 case PPC::LVX: 546 case PPC::LVXL: 547 case PPC::LVSL: 548 case PPC::LVSR: 549 case PPC::STVEBX: 550 case PPC::STVEHX: 551 case PPC::STVEWX: 552 case PPC::STVX: 553 case PPC::STVXL: 554 noImmForm = true; 555 break; 556 } 557 558 // Now add the frame object offset to the offset from r1. 559 int Offset = MFI->getObjectOffset(FrameIndex); 560 if (!isIXAddr) 561 Offset += MI.getOperand(OffsetOperandNo).getImm(); 562 else 563 Offset += MI.getOperand(OffsetOperandNo).getImm() << 2; 564 565 // If we're not using a Frame Pointer that has been set to the value of the 566 // SP before having the stack size subtracted from it, then add the stack size 567 // to Offset to get the correct offset. 568 // Naked functions have stack size 0, although getStackSize may not reflect that 569 // because we didn't call all the pieces that compute it for naked functions. 570 if (!MF.getFunction()->getAttributes(). 571 hasAttribute(AttributeSet::FunctionIndex, Attribute::Naked)) 572 Offset += MFI->getStackSize(); 573 574 // If we can, encode the offset directly into the instruction. If this is a 575 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If 576 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits 577 // clear can be encoded. This is extremely uncommon, because normally you 578 // only "std" to a stack slot that is at least 4-byte aligned, but it can 579 // happen in invalid code. 580 if (OpC == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm 581 (!noImmForm && 582 isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0))) { 583 if (isIXAddr) 584 Offset >>= 2; // The actual encoded value has the low two bits zero. 585 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 586 return; 587 } 588 589 // The offset doesn't fit into a single register, scavenge one to build the 590 // offset in. 591 592 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 593 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 594 unsigned SReg = MF.getRegInfo().createVirtualRegister(is64Bit ? G8RC : GPRC); 595 596 // Insert a set of rA with the full offset value before the ld, st, or add 597 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SReg) 598 .addImm(Offset >> 16); 599 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg) 600 .addReg(SReg, RegState::Kill) 601 .addImm(Offset); 602 603 // Convert into indexed form of the instruction: 604 // 605 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 606 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 607 unsigned OperandBase; 608 609 if (noImmForm) 610 OperandBase = 1; 611 else if (OpC != TargetOpcode::INLINEASM) { 612 assert(ImmToIdxMap.count(OpC) && 613 "No indexed form of load or store available!"); 614 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; 615 MI.setDesc(TII.get(NewOpcode)); 616 OperandBase = 1; 617 } else { 618 OperandBase = OffsetOperandNo; 619 } 620 621 unsigned StackReg = MI.getOperand(FIOperandNum).getReg(); 622 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false); 623 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true); 624 } 625 626 unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 627 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 628 629 if (!Subtarget.isPPC64()) 630 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1; 631 else 632 return TFI->hasFP(MF) ? PPC::X31 : PPC::X1; 633 } 634 635 unsigned PPCRegisterInfo::getEHExceptionRegister() const { 636 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3; 637 } 638 639 unsigned PPCRegisterInfo::getEHHandlerRegister() const { 640 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4; 641 } 642