1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file was developed by the LLVM research group and is distributed under 6 // the University of Illinois Open Source License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the MRegisterInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #define DEBUG_TYPE "reginfo" 15 #include "PPC.h" 16 #include "PPCInstrBuilder.h" 17 #include "PPCMachineFunctionInfo.h" 18 #include "PPCRegisterInfo.h" 19 #include "PPCFrameInfo.h" 20 #include "PPCSubtarget.h" 21 #include "llvm/Constants.h" 22 #include "llvm/Type.h" 23 #include "llvm/CodeGen/ValueTypes.h" 24 #include "llvm/CodeGen/MachineInstrBuilder.h" 25 #include "llvm/CodeGen/MachineDebugInfo.h" 26 #include "llvm/CodeGen/MachineFunction.h" 27 #include "llvm/CodeGen/MachineFrameInfo.h" 28 #include "llvm/CodeGen/MachineLocation.h" 29 #include "llvm/CodeGen/SelectionDAGNodes.h" 30 #include "llvm/Target/TargetFrameInfo.h" 31 #include "llvm/Target/TargetInstrInfo.h" 32 #include "llvm/Target/TargetMachine.h" 33 #include "llvm/Target/TargetOptions.h" 34 #include "llvm/Support/CommandLine.h" 35 #include "llvm/Support/Debug.h" 36 #include "llvm/Support/MathExtras.h" 37 #include "llvm/ADT/STLExtras.h" 38 #include <cstdlib> 39 using namespace llvm; 40 41 /// getRegisterNumbering - Given the enum value for some register, e.g. 42 /// PPC::F14, return the number that it corresponds to (e.g. 14). 43 unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) { 44 using namespace PPC; 45 switch (RegEnum) { 46 case R0 : case X0 : case F0 : case V0 : case CR0: return 0; 47 case R1 : case X1 : case F1 : case V1 : case CR1: return 1; 48 case R2 : case X2 : case F2 : case V2 : case CR2: return 2; 49 case R3 : case X3 : case F3 : case V3 : case CR3: return 3; 50 case R4 : case X4 : case F4 : case V4 : case CR4: return 4; 51 case R5 : case X5 : case F5 : case V5 : case CR5: return 5; 52 case R6 : case X6 : case F6 : case V6 : case CR6: return 6; 53 case R7 : case X7 : case F7 : case V7 : case CR7: return 7; 54 case R8 : case X8 : case F8 : case V8 : return 8; 55 case R9 : case X9 : case F9 : case V9 : return 9; 56 case R10: case X10: case F10: case V10: return 10; 57 case R11: case X11: case F11: case V11: return 11; 58 case R12: case X12: case F12: case V12: return 12; 59 case R13: case X13: case F13: case V13: return 13; 60 case R14: case X14: case F14: case V14: return 14; 61 case R15: case X15: case F15: case V15: return 15; 62 case R16: case X16: case F16: case V16: return 16; 63 case R17: case X17: case F17: case V17: return 17; 64 case R18: case X18: case F18: case V18: return 18; 65 case R19: case X19: case F19: case V19: return 19; 66 case R20: case X20: case F20: case V20: return 20; 67 case R21: case X21: case F21: case V21: return 21; 68 case R22: case X22: case F22: case V22: return 22; 69 case R23: case X23: case F23: case V23: return 23; 70 case R24: case X24: case F24: case V24: return 24; 71 case R25: case X25: case F25: case V25: return 25; 72 case R26: case X26: case F26: case V26: return 26; 73 case R27: case X27: case F27: case V27: return 27; 74 case R28: case X28: case F28: case V28: return 28; 75 case R29: case X29: case F29: case V29: return 29; 76 case R30: case X30: case F30: case V30: return 30; 77 case R31: case X31: case F31: case V31: return 31; 78 default: 79 cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n"; 80 abort(); 81 } 82 } 83 84 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST, 85 const TargetInstrInfo &tii) 86 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP), 87 Subtarget(ST), TII(tii) { 88 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 89 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 90 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 91 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 92 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 93 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 94 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 95 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 96 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; 97 } 98 99 void 100 PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 101 MachineBasicBlock::iterator MI, 102 unsigned SrcReg, int FrameIdx, 103 const TargetRegisterClass *RC) const { 104 if (RC == PPC::GPRCRegisterClass) { 105 if (SrcReg != PPC::LR) { 106 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW)).addReg(SrcReg), 107 FrameIdx); 108 } else { 109 // FIXME: this spills LR immediately to memory in one step. To do this, 110 // we use R11, which we know cannot be used in the prolog/epilog. This is 111 // a hack. 112 BuildMI(MBB, MI, TII.get(PPC::MFLR), PPC::R11); 113 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW)).addReg(PPC::R11), 114 FrameIdx); 115 } 116 } else if (RC == PPC::G8RCRegisterClass) { 117 if (SrcReg != PPC::LR8) { 118 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STD)).addReg(SrcReg), 119 FrameIdx); 120 } else { 121 // FIXME: this spills LR immediately to memory in one step. To do this, 122 // we use R11, which we know cannot be used in the prolog/epilog. This is 123 // a hack. 124 BuildMI(MBB, MI, TII.get(PPC::MFLR8), PPC::X11); 125 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STD)).addReg(PPC::X11), 126 FrameIdx); 127 } 128 } else if (RC == PPC::F8RCRegisterClass) { 129 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STFD)).addReg(SrcReg), 130 FrameIdx); 131 } else if (RC == PPC::F4RCRegisterClass) { 132 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STFS)).addReg(SrcReg), 133 FrameIdx); 134 } else if (RC == PPC::CRRCRegisterClass) { 135 // FIXME: We use R0 here, because it isn't available for RA. 136 // We need to store the CR in the low 4-bits of the saved value. First, 137 // issue a MFCR to save all of the CRBits. 138 BuildMI(MBB, MI, TII.get(PPC::MFCR), PPC::R0); 139 140 // If the saved register wasn't CR0, shift the bits left so that they are in 141 // CR0's slot. 142 if (SrcReg != PPC::CR0) { 143 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4; 144 // rlwinm r0, r0, ShiftBits, 0, 31. 145 BuildMI(MBB, MI, TII.get(PPC::RLWINM), PPC::R0) 146 .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31); 147 } 148 149 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW)).addReg(PPC::R0), 150 FrameIdx); 151 } else if (RC == PPC::VRRCRegisterClass) { 152 // We don't have indexed addressing for vector loads. Emit: 153 // R11 = ADDI FI# 154 // Dest = LVX R0, R11 155 // 156 // FIXME: We use R0 here, because it isn't available for RA. 157 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::ADDI), PPC::R0), 158 FrameIdx, 0, 0); 159 BuildMI(MBB, MI, TII.get(PPC::STVX)) 160 .addReg(SrcReg).addReg(PPC::R0).addReg(PPC::R0); 161 } else { 162 assert(0 && "Unknown regclass!"); 163 abort(); 164 } 165 } 166 167 void 168 PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 169 MachineBasicBlock::iterator MI, 170 unsigned DestReg, int FrameIdx, 171 const TargetRegisterClass *RC) const { 172 if (RC == PPC::GPRCRegisterClass) { 173 if (DestReg != PPC::LR) { 174 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LWZ), DestReg), FrameIdx); 175 } else { 176 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LWZ), PPC::R11),FrameIdx); 177 BuildMI(MBB, MI, TII.get(PPC::MTLR)).addReg(PPC::R11); 178 } 179 } else if (RC == PPC::G8RCRegisterClass) { 180 if (DestReg != PPC::LR8) { 181 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LD), DestReg), FrameIdx); 182 } else { 183 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LD), PPC::R11), FrameIdx); 184 BuildMI(MBB, MI, TII.get(PPC::MTLR8)).addReg(PPC::R11); 185 } 186 } else if (RC == PPC::F8RCRegisterClass) { 187 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LFD), DestReg), FrameIdx); 188 } else if (RC == PPC::F4RCRegisterClass) { 189 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LFS), DestReg), FrameIdx); 190 } else if (RC == PPC::CRRCRegisterClass) { 191 // FIXME: We use R0 here, because it isn't available for RA. 192 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LWZ), PPC::R0), FrameIdx); 193 194 // If the reloaded register isn't CR0, shift the bits right so that they are 195 // in the right CR's slot. 196 if (DestReg != PPC::CR0) { 197 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4; 198 // rlwinm r11, r11, 32-ShiftBits, 0, 31. 199 BuildMI(MBB, MI, TII.get(PPC::RLWINM), PPC::R0) 200 .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31); 201 } 202 203 BuildMI(MBB, MI, TII.get(PPC::MTCRF), DestReg).addReg(PPC::R0); 204 } else if (RC == PPC::VRRCRegisterClass) { 205 // We don't have indexed addressing for vector loads. Emit: 206 // R11 = ADDI FI# 207 // Dest = LVX R0, R11 208 // 209 // FIXME: We use R0 here, because it isn't available for RA. 210 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::ADDI), PPC::R0), 211 FrameIdx, 0, 0); 212 BuildMI(MBB, MI, TII.get(PPC::LVX),DestReg).addReg(PPC::R0).addReg(PPC::R0); 213 } else { 214 assert(0 && "Unknown regclass!"); 215 abort(); 216 } 217 } 218 219 void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, 220 MachineBasicBlock::iterator MI, 221 unsigned DestReg, unsigned SrcReg, 222 const TargetRegisterClass *RC) const { 223 if (RC == PPC::GPRCRegisterClass) { 224 BuildMI(MBB, MI, TII.get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg); 225 } else if (RC == PPC::G8RCRegisterClass) { 226 BuildMI(MBB, MI, TII.get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg); 227 } else if (RC == PPC::F4RCRegisterClass) { 228 BuildMI(MBB, MI, TII.get(PPC::FMRS), DestReg).addReg(SrcReg); 229 } else if (RC == PPC::F8RCRegisterClass) { 230 BuildMI(MBB, MI, TII.get(PPC::FMRD), DestReg).addReg(SrcReg); 231 } else if (RC == PPC::CRRCRegisterClass) { 232 BuildMI(MBB, MI, TII.get(PPC::MCRF), DestReg).addReg(SrcReg); 233 } else if (RC == PPC::VRRCRegisterClass) { 234 BuildMI(MBB, MI, TII.get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg); 235 } else { 236 cerr << "Attempt to copy register that is not GPR or FPR"; 237 abort(); 238 } 239 } 240 241 const unsigned* PPCRegisterInfo::getCalleeSavedRegs() const { 242 // 32-bit Darwin calling convention. 243 static const unsigned Darwin32_CalleeSavedRegs[] = { 244 PPC::R13, PPC::R14, PPC::R15, 245 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 246 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 247 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 248 PPC::R28, PPC::R29, PPC::R30, PPC::R31, 249 250 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 251 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 252 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 253 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 254 PPC::F30, PPC::F31, 255 256 PPC::CR2, PPC::CR3, PPC::CR4, 257 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 258 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 259 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 260 261 PPC::LR, 0 262 }; 263 // 64-bit Darwin calling convention. 264 static const unsigned Darwin64_CalleeSavedRegs[] = { 265 PPC::X14, PPC::X15, 266 PPC::X16, PPC::X17, PPC::X18, PPC::X19, 267 PPC::X20, PPC::X21, PPC::X22, PPC::X23, 268 PPC::X24, PPC::X25, PPC::X26, PPC::X27, 269 PPC::X28, PPC::X29, PPC::X30, PPC::X31, 270 271 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 272 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 273 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 274 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 275 PPC::F30, PPC::F31, 276 277 PPC::CR2, PPC::CR3, PPC::CR4, 278 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 279 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 280 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 281 282 PPC::LR8, 0 283 }; 284 285 return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegs : 286 Darwin32_CalleeSavedRegs; 287 } 288 289 const TargetRegisterClass* const* 290 PPCRegisterInfo::getCalleeSavedRegClasses() const { 291 // 32-bit Darwin calling convention. 292 static const TargetRegisterClass * const Darwin32_CalleeSavedRegClasses[] = { 293 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 294 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 295 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 296 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 297 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 298 299 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 300 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 301 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 302 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 303 &PPC::F8RCRegClass,&PPC::F8RCRegClass, 304 305 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, 306 307 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 308 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 309 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 310 311 &PPC::GPRCRegClass, 0 312 }; 313 314 // 64-bit Darwin calling convention. 315 static const TargetRegisterClass * const Darwin64_CalleeSavedRegClasses[] = { 316 &PPC::G8RCRegClass,&PPC::G8RCRegClass, 317 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 318 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 319 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 320 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 321 322 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 323 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 324 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 325 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 326 &PPC::F8RCRegClass,&PPC::F8RCRegClass, 327 328 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, 329 330 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 331 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 332 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 333 334 &PPC::G8RCRegClass, 0 335 }; 336 337 return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegClasses : 338 Darwin32_CalleeSavedRegClasses; 339 } 340 341 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into 342 /// copy instructions, turning them into load/store instructions. 343 MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI, 344 unsigned OpNum, 345 int FrameIndex) const { 346 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because 347 // it takes more than one instruction to store it. 348 unsigned Opc = MI->getOpcode(); 349 350 MachineInstr *NewMI = NULL; 351 if ((Opc == PPC::OR && 352 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { 353 if (OpNum == 0) { // move -> store 354 unsigned InReg = MI->getOperand(1).getReg(); 355 NewMI = addFrameReference(BuildMI(TII.get(PPC::STW)).addReg(InReg), 356 FrameIndex); 357 } else { // move -> load 358 unsigned OutReg = MI->getOperand(0).getReg(); 359 NewMI = addFrameReference(BuildMI(TII.get(PPC::LWZ), OutReg), 360 FrameIndex); 361 } 362 } else if ((Opc == PPC::OR8 && 363 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { 364 if (OpNum == 0) { // move -> store 365 unsigned InReg = MI->getOperand(1).getReg(); 366 NewMI = addFrameReference(BuildMI(TII.get(PPC::STD)).addReg(InReg), 367 FrameIndex); 368 } else { // move -> load 369 unsigned OutReg = MI->getOperand(0).getReg(); 370 NewMI = addFrameReference(BuildMI(TII.get(PPC::LD), OutReg), FrameIndex); 371 } 372 } else if (Opc == PPC::FMRD) { 373 if (OpNum == 0) { // move -> store 374 unsigned InReg = MI->getOperand(1).getReg(); 375 NewMI = addFrameReference(BuildMI(TII.get(PPC::STFD)).addReg(InReg), 376 FrameIndex); 377 } else { // move -> load 378 unsigned OutReg = MI->getOperand(0).getReg(); 379 NewMI = addFrameReference(BuildMI(TII.get(PPC::LFD), OutReg), FrameIndex); 380 } 381 } else if (Opc == PPC::FMRS) { 382 if (OpNum == 0) { // move -> store 383 unsigned InReg = MI->getOperand(1).getReg(); 384 NewMI = addFrameReference(BuildMI(TII.get(PPC::STFS)).addReg(InReg), 385 FrameIndex); 386 } else { // move -> load 387 unsigned OutReg = MI->getOperand(0).getReg(); 388 NewMI = addFrameReference(BuildMI(TII.get(PPC::LFS), OutReg), FrameIndex); 389 } 390 } 391 392 if (NewMI) 393 NewMI->copyKillDeadInfo(MI); 394 return NewMI; 395 } 396 397 //===----------------------------------------------------------------------===// 398 // Stack Frame Processing methods 399 //===----------------------------------------------------------------------===// 400 401 // needsFP - Return true if the specified function should have a dedicated frame 402 // pointer register. This is true if the function has variable sized allocas or 403 // if frame pointer elimination is disabled. 404 // 405 static bool needsFP(const MachineFunction &MF) { 406 const MachineFrameInfo *MFI = MF.getFrameInfo(); 407 return NoFramePointerElim || MFI->hasVarSizedObjects(); 408 } 409 410 // hasFP - Return true if the specified function actually has a dedicated frame 411 // pointer register. This is true if the function needs a frame pointer and has 412 // a non-zero stack size. 413 bool PPCRegisterInfo::hasFP(const MachineFunction &MF) const { 414 const MachineFrameInfo *MFI = MF.getFrameInfo(); 415 return MFI->getStackSize() && needsFP(MF); 416 } 417 418 /// usesLR - Returns if the link registers (LR) has been used in the function. 419 /// 420 bool PPCRegisterInfo::usesLR(MachineFunction &MF) const { 421 const bool *PhysRegsUsed = MF.getUsedPhysregs(); 422 return PhysRegsUsed[getRARegister()]; 423 } 424 425 void PPCRegisterInfo:: 426 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 427 MachineBasicBlock::iterator I) const { 428 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions. 429 MBB.erase(I); 430 } 431 432 /// LowerDynamicAlloc - Generate the code for allocating an object in the 433 /// current frame. The sequence of code with be in the general form 434 /// 435 /// addi R0, SP, #frameSize ; get the address of the previous frame 436 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size 437 /// addi Rnew, SP, #maxCalFrameSize ; get the top of the allocation 438 /// 439 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const { 440 // Get the instruction. 441 MachineInstr &MI = *II; 442 // Get the instruction's basic block. 443 MachineBasicBlock &MBB = *MI.getParent(); 444 // Get the basic block's function. 445 MachineFunction &MF = *MBB.getParent(); 446 // Get the frame info. 447 MachineFrameInfo *MFI = MF.getFrameInfo(); 448 // Determine whether 64-bit pointers are used. 449 bool LP64 = Subtarget.isPPC64(); 450 451 // Determine the maximum call stack size. maxCallFrameSize may be 452 // less than the minimum. 453 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 454 unsigned getMinCallFrameSize = 455 PPCFrameInfo::getMinCallFrameSize(LP64); 456 maxCallFrameSize = std::max(maxCallFrameSize, getMinCallFrameSize); 457 // Get the total frame size. 458 unsigned FrameSize = MFI->getStackSize(); 459 460 // Get stack alignments. 461 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 462 unsigned MaxAlign = MFI->getMaxAlignment(); 463 assert(MaxAlign <= TargetAlign && 464 "Dynamic alloca with large aligns not supported"); 465 466 // Determine the previous frame's address. If FrameSize can't be 467 // represented as 16 bits or we need special alignment, then we load the 468 // previous frame's address from 0(SP). Why not do an addis of the hi? 469 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. 470 // Constructing the constant and adding would take 3 instructions. 471 // Fortunately, a frame greater than 32K is rare. 472 if (MaxAlign < TargetAlign && isInt16(FrameSize)) { 473 BuildMI(MBB, II, TII.get(PPC::ADDI), PPC::R0) 474 .addReg(PPC::R31) 475 .addImm(FrameSize); 476 } else if (LP64) { 477 BuildMI(MBB, II, TII.get(PPC::LD), PPC::X0) 478 .addImm(0) 479 .addReg(PPC::X1); 480 } else { 481 BuildMI(MBB, II, TII.get(PPC::LWZ), PPC::R0) 482 .addImm(0) 483 .addReg(PPC::R1); 484 } 485 486 // Grow the stack and update the stack pointer link, then 487 // determine the address of new allocated space. 488 if (LP64) { 489 BuildMI(MBB, II, TII.get(PPC::STDUX)) 490 .addReg(PPC::X0) 491 .addReg(PPC::X1) 492 .addReg(MI.getOperand(1).getReg()); 493 BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 494 .addReg(PPC::X1) 495 .addImm(maxCallFrameSize); 496 } else { 497 BuildMI(MBB, II, TII.get(PPC::STWUX)) 498 .addReg(PPC::R0) 499 .addReg(PPC::R1) 500 .addReg(MI.getOperand(1).getReg()); 501 BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 502 .addReg(PPC::R1) 503 .addImm(maxCallFrameSize); 504 } 505 506 // Discard the DYNALLOC instruction. 507 MBB.erase(II); 508 } 509 510 void 511 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { 512 // Get the instruction. 513 MachineInstr &MI = *II; 514 // Get the instruction's basic block. 515 MachineBasicBlock &MBB = *MI.getParent(); 516 // Get the basic block's function. 517 MachineFunction &MF = *MBB.getParent(); 518 // Get the frame info. 519 MachineFrameInfo *MFI = MF.getFrameInfo(); 520 521 // Find out which operand is the frame index. 522 unsigned i = 0; 523 while (!MI.getOperand(i).isFrameIndex()) { 524 ++i; 525 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 526 } 527 // Take into account whether it's an add or mem instruction 528 unsigned OffIdx = (i == 2) ? 1 : 2; 529 // Get the frame index. 530 int FrameIndex = MI.getOperand(i).getFrameIndex(); 531 532 // Get the frame pointer save index. Users of this index are primarily 533 // DYNALLOC instructions. 534 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 535 int FPSI = FI->getFramePointerSaveIndex(); 536 // Get the instruction opcode. 537 unsigned OpC = MI.getOpcode(); 538 539 // Special case for dynamic alloca. 540 if (FPSI && FrameIndex == FPSI && 541 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { 542 lowerDynamicAlloc(II); 543 return; 544 } 545 546 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 547 MI.getOperand(i).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1, false); 548 549 // Figure out if the offset in the instruction is shifted right two bits. This 550 // is true for instructions like "STD", which the machine implicitly adds two 551 // low zeros to. 552 bool isIXAddr = false; 553 switch (OpC) { 554 case PPC::LWA: 555 case PPC::LD: 556 case PPC::STD: 557 case PPC::STD_32: 558 isIXAddr = true; 559 break; 560 } 561 562 // Now add the frame object offset to the offset from r1. 563 int Offset = MFI->getObjectOffset(FrameIndex); 564 565 if (!isIXAddr) 566 Offset += MI.getOperand(OffIdx).getImmedValue(); 567 else 568 Offset += MI.getOperand(OffIdx).getImmedValue() << 2; 569 570 // If we're not using a Frame Pointer that has been set to the value of the 571 // SP before having the stack size subtracted from it, then add the stack size 572 // to Offset to get the correct offset. 573 Offset += MFI->getStackSize(); 574 575 if (!isInt16(Offset)) { 576 // Insert a set of r0 with the full offset value before the ld, st, or add 577 BuildMI(MBB, II, TII.get(PPC::LIS), PPC::R0).addImm(Offset >> 16); 578 BuildMI(MBB, II, TII.get(PPC::ORI), PPC::R0).addReg(PPC::R0).addImm(Offset); 579 580 // convert into indexed form of the instruction 581 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 582 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 583 assert(ImmToIdxMap.count(OpC) && 584 "No indexed form of load or store available!"); 585 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; 586 MI.setInstrDescriptor(TII.get(NewOpcode)); 587 MI.getOperand(1).ChangeToRegister(MI.getOperand(i).getReg(), false); 588 MI.getOperand(2).ChangeToRegister(PPC::R0, false); 589 } else { 590 if (isIXAddr) { 591 assert((Offset & 3) == 0 && "Invalid frame offset!"); 592 Offset >>= 2; // The actual encoded value has the low two bits zero. 593 } 594 MI.getOperand(OffIdx).ChangeToImmediate(Offset); 595 } 596 } 597 598 /// VRRegNo - Map from a numbered VR register to its enum value. 599 /// 600 static const unsigned short VRRegNo[] = { 601 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 , 602 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, 603 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, 604 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31 605 }; 606 607 /// RemoveVRSaveCode - We have found that this function does not need any code 608 /// to manipulate the VRSAVE register, even though it uses vector registers. 609 /// This can happen when the only registers used are known to be live in or out 610 /// of the function. Remove all of the VRSAVE related code from the function. 611 static void RemoveVRSaveCode(MachineInstr *MI) { 612 MachineBasicBlock *Entry = MI->getParent(); 613 MachineFunction *MF = Entry->getParent(); 614 615 // We know that the MTVRSAVE instruction immediately follows MI. Remove it. 616 MachineBasicBlock::iterator MBBI = MI; 617 ++MBBI; 618 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE); 619 MBBI->eraseFromParent(); 620 621 bool RemovedAllMTVRSAVEs = true; 622 // See if we can find and remove the MTVRSAVE instruction from all of the 623 // epilog blocks. 624 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); 625 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) { 626 // If last instruction is a return instruction, add an epilogue 627 if (!I->empty() && TII.isReturn(I->back().getOpcode())) { 628 bool FoundIt = false; 629 for (MBBI = I->end(); MBBI != I->begin(); ) { 630 --MBBI; 631 if (MBBI->getOpcode() == PPC::MTVRSAVE) { 632 MBBI->eraseFromParent(); // remove it. 633 FoundIt = true; 634 break; 635 } 636 } 637 RemovedAllMTVRSAVEs &= FoundIt; 638 } 639 } 640 641 // If we found and removed all MTVRSAVE instructions, remove the read of 642 // VRSAVE as well. 643 if (RemovedAllMTVRSAVEs) { 644 MBBI = MI; 645 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?"); 646 --MBBI; 647 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?"); 648 MBBI->eraseFromParent(); 649 } 650 651 // Finally, nuke the UPDATE_VRSAVE. 652 MI->eraseFromParent(); 653 } 654 655 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the 656 // instruction selector. Based on the vector registers that have been used, 657 // transform this into the appropriate ORI instruction. 658 static void HandleVRSaveUpdate(MachineInstr *MI, const bool *UsedRegs, 659 const TargetInstrInfo &TII) { 660 unsigned UsedRegMask = 0; 661 for (unsigned i = 0; i != 32; ++i) 662 if (UsedRegs[VRRegNo[i]]) 663 UsedRegMask |= 1 << (31-i); 664 665 // Live in and live out values already must be in the mask, so don't bother 666 // marking them. 667 MachineFunction *MF = MI->getParent()->getParent(); 668 for (MachineFunction::livein_iterator I = 669 MF->livein_begin(), E = MF->livein_end(); I != E; ++I) { 670 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first); 671 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg. 672 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 673 } 674 for (MachineFunction::liveout_iterator I = 675 MF->liveout_begin(), E = MF->liveout_end(); I != E; ++I) { 676 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I); 677 if (VRRegNo[RegNo] == *I) // If this really is a vector reg. 678 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 679 } 680 681 unsigned SrcReg = MI->getOperand(1).getReg(); 682 unsigned DstReg = MI->getOperand(0).getReg(); 683 // If no registers are used, turn this into a copy. 684 if (UsedRegMask == 0) { 685 // Remove all VRSAVE code. 686 RemoveVRSaveCode(MI); 687 return; 688 } else if ((UsedRegMask & 0xFFFF) == UsedRegMask) { 689 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg) 690 .addReg(SrcReg).addImm(UsedRegMask); 691 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { 692 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) 693 .addReg(SrcReg).addImm(UsedRegMask >> 16); 694 } else { 695 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) 696 .addReg(SrcReg).addImm(UsedRegMask >> 16); 697 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg) 698 .addReg(DstReg).addImm(UsedRegMask & 0xFFFF); 699 } 700 701 // Remove the old UPDATE_VRSAVE instruction. 702 MI->eraseFromParent(); 703 } 704 705 /// determineFrameLayout - Determine the size of the frame and maximum call 706 /// frame size. 707 void PPCRegisterInfo::determineFrameLayout(MachineFunction &MF) const { 708 MachineFrameInfo *MFI = MF.getFrameInfo(); 709 710 // Get the number of bytes to allocate from the FrameInfo 711 unsigned FrameSize = MFI->getStackSize(); 712 713 // Get the alignments provided by the target, and the maximum alignment 714 // (if any) of the fixed frame objects. 715 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 716 unsigned MaxAlign = MFI->getMaxAlignment(); 717 unsigned Align = std::max(TargetAlign, MaxAlign); 718 assert(isPowerOf2_32(Align) && "Alignment is not power of 2"); 719 unsigned AlignMask = Align - 1; // 720 721 // If we are a leaf function, and use up to 224 bytes of stack space, 722 // don't have a frame pointer, calls, or dynamic alloca then we do not need 723 // to adjust the stack pointer (we fit in the Red Zone). 724 if (FrameSize <= 224 && // Fits in red zone. 725 !MFI->hasVarSizedObjects() && // No dynamic alloca. 726 !MFI->hasCalls() && // No calls. 727 MaxAlign <= TargetAlign) { // No special alignment. 728 // No need for frame 729 MFI->setStackSize(0); 730 return; 731 } 732 733 // Get the maximum call frame size of all the calls. 734 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 735 736 // Maximum call frame needs to be at least big enough for linkage and 8 args. 737 unsigned minCallFrameSize = 738 PPCFrameInfo::getMinCallFrameSize(Subtarget.isPPC64()); 739 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize); 740 741 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so 742 // that allocations will be aligned. 743 if (MFI->hasVarSizedObjects()) 744 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask; 745 746 // Update maximum call frame size. 747 MFI->setMaxCallFrameSize(maxCallFrameSize); 748 749 // Include call frame size in total. 750 FrameSize += maxCallFrameSize; 751 752 // Make sure the frame is aligned. 753 FrameSize = (FrameSize + AlignMask) & ~AlignMask; 754 755 // Update frame info. 756 MFI->setStackSize(FrameSize); 757 } 758 759 void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const { 760 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB 761 MachineBasicBlock::iterator MBBI = MBB.begin(); 762 MachineFrameInfo *MFI = MF.getFrameInfo(); 763 MachineDebugInfo *DebugInfo = MFI->getMachineDebugInfo(); 764 765 // Prepare for debug frame info. 766 bool hasInfo = DebugInfo && DebugInfo->hasInfo(); 767 unsigned FrameLabelId = 0; 768 769 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it, 770 // process it. 771 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { 772 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) { 773 HandleVRSaveUpdate(MBBI, MF.getUsedPhysregs(), TII); 774 break; 775 } 776 } 777 778 // Move MBBI back to the beginning of the function. 779 MBBI = MBB.begin(); 780 781 // Work out frame sizes. 782 determineFrameLayout(MF); 783 unsigned FrameSize = MFI->getStackSize(); 784 785 // Skip if a leaf routine. 786 if (!FrameSize) return; 787 788 int NegFrameSize = -FrameSize; 789 790 // Get processor type. 791 bool IsPPC64 = Subtarget.isPPC64(); 792 // Check if the link register (LR) has been used. 793 bool UsesLR = MFI->hasCalls() || usesLR(MF); 794 // Do we have a frame pointer for this function? 795 bool HasFP = hasFP(MF); 796 797 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64); 798 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64); 799 800 if (IsPPC64) { 801 if (UsesLR) 802 BuildMI(MBB, MBBI, TII.get(PPC::MFLR8), PPC::X0); 803 804 if (HasFP) 805 BuildMI(MBB, MBBI, TII.get(PPC::STD)) 806 .addReg(PPC::X31).addImm(FPOffset/4).addReg(PPC::X1); 807 808 if (UsesLR) 809 BuildMI(MBB, MBBI, TII.get(PPC::STD)) 810 .addReg(PPC::X0).addImm(LROffset/4).addReg(PPC::X1); 811 } else { 812 if (UsesLR) 813 BuildMI(MBB, MBBI, TII.get(PPC::MFLR), PPC::R0); 814 815 if (HasFP) 816 BuildMI(MBB, MBBI, TII.get(PPC::STW)) 817 .addReg(PPC::R31).addImm(FPOffset).addReg(PPC::R1); 818 819 if (UsesLR) 820 BuildMI(MBB, MBBI, TII.get(PPC::STW)) 821 .addReg(PPC::R0).addImm(LROffset).addReg(PPC::R1); 822 } 823 824 // Get stack alignments. 825 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 826 unsigned MaxAlign = MFI->getMaxAlignment(); 827 828 if (hasInfo) { 829 // Mark effective beginning of when frame pointer becomes valid. 830 FrameLabelId = DebugInfo->NextLabelID(); 831 BuildMI(MBB, MBBI, TII.get(PPC::DWARF_LABEL)).addImm(FrameLabelId); 832 } 833 834 // Adjust stack pointer: r1 += NegFrameSize. 835 // If there is a preferred stack alignment, align R1 now 836 if (!IsPPC64) { 837 // PPC32. 838 if (MaxAlign > TargetAlign) { 839 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!"); 840 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!"); 841 BuildMI(MBB, MBBI, TII.get(PPC::RLWINM), PPC::R0) 842 .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31); 843 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC) ,PPC::R0).addReg(PPC::R0) 844 .addImm(NegFrameSize); 845 BuildMI(MBB, MBBI, TII.get(PPC::STWUX)) 846 .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0); 847 } else if (isInt16(NegFrameSize)) { 848 BuildMI(MBB, MBBI, TII.get(PPC::STWU), 849 PPC::R1).addReg(PPC::R1).addImm(NegFrameSize).addReg(PPC::R1); 850 } else { 851 BuildMI(MBB, MBBI, TII.get(PPC::LIS), PPC::R0).addImm(NegFrameSize >> 16); 852 BuildMI(MBB, MBBI, TII.get(PPC::ORI), PPC::R0).addReg(PPC::R0) 853 .addImm(NegFrameSize & 0xFFFF); 854 BuildMI(MBB, MBBI, TII.get(PPC::STWUX)).addReg(PPC::R1).addReg(PPC::R1) 855 .addReg(PPC::R0); 856 } 857 } else { // PPC64. 858 if (MaxAlign > TargetAlign) { 859 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!"); 860 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!"); 861 BuildMI(MBB, MBBI, TII.get(PPC::RLDICL), PPC::X0) 862 .addReg(PPC::X1).addImm(0).addImm(64-Log2_32(MaxAlign)); 863 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC8), PPC::X0).addReg(PPC::X0) 864 .addImm(NegFrameSize); 865 BuildMI(MBB, MBBI, TII.get(PPC::STDUX)) 866 .addReg(PPC::X1).addReg(PPC::X1).addReg(PPC::X0); 867 } else if (isInt16(NegFrameSize)) { 868 BuildMI(MBB, MBBI, TII.get(PPC::STDU), PPC::X1) 869 .addReg(PPC::X1).addImm(NegFrameSize/4).addReg(PPC::X1); 870 } else { 871 BuildMI(MBB, MBBI, TII.get(PPC::LIS8), PPC::X0).addImm(NegFrameSize >>16); 872 BuildMI(MBB, MBBI, TII.get(PPC::ORI8), PPC::X0).addReg(PPC::X0) 873 .addImm(NegFrameSize & 0xFFFF); 874 BuildMI(MBB, MBBI, TII.get(PPC::STDUX)).addReg(PPC::X1).addReg(PPC::X1) 875 .addReg(PPC::X0); 876 } 877 } 878 879 if (hasInfo) { 880 std::vector<MachineMove> &Moves = DebugInfo->getFrameMoves(); 881 882 if (NegFrameSize) { 883 // Show update of SP. 884 MachineLocation SPDst(MachineLocation::VirtualFP); 885 MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize); 886 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc)); 887 } else { 888 MachineLocation SP(IsPPC64 ? PPC::X31 : PPC::R31); 889 Moves.push_back(MachineMove(FrameLabelId, SP, SP)); 890 } 891 892 if (HasFP) { 893 MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset); 894 MachineLocation FPSrc(IsPPC64 ? PPC::X31 : PPC::R31); 895 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc)); 896 } 897 898 // Add callee saved registers to move list. 899 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 900 for (unsigned I = 0, E = CSI.size(); I != E; ++I) { 901 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx()); 902 unsigned Reg = CSI[I].getReg(); 903 if (Reg == PPC::LR || Reg == PPC::LR8) continue; 904 MachineLocation CSDst(MachineLocation::VirtualFP, Offset); 905 MachineLocation CSSrc(Reg); 906 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc)); 907 } 908 909 // Mark effective beginning of when frame pointer is ready. 910 unsigned ReadyLabelId = DebugInfo->NextLabelID(); 911 BuildMI(MBB, MBBI, TII.get(PPC::DWARF_LABEL)).addImm(ReadyLabelId); 912 913 MachineLocation FPDst(HasFP ? (IsPPC64 ? PPC::X31 : PPC::R31) : 914 (IsPPC64 ? PPC::X1 : PPC::R1)); 915 MachineLocation FPSrc(MachineLocation::VirtualFP); 916 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc)); 917 } 918 919 // If there is a frame pointer, copy R1 into R31 920 if (HasFP) { 921 if (!IsPPC64) { 922 BuildMI(MBB, MBBI, TII.get(PPC::OR), PPC::R31).addReg(PPC::R1) 923 .addReg(PPC::R1); 924 } else { 925 BuildMI(MBB, MBBI, TII.get(PPC::OR8), PPC::X31).addReg(PPC::X1) 926 .addReg(PPC::X1); 927 } 928 } 929 } 930 931 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF, 932 MachineBasicBlock &MBB) const { 933 MachineBasicBlock::iterator MBBI = prior(MBB.end()); 934 assert(MBBI->getOpcode() == PPC::BLR && 935 "Can only insert epilog into returning blocks"); 936 937 // Get alignment info so we know how to restore r1 938 const MachineFrameInfo *MFI = MF.getFrameInfo(); 939 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 940 unsigned MaxAlign = MFI->getMaxAlignment(); 941 942 // Get the number of bytes allocated from the FrameInfo. 943 unsigned FrameSize = MFI->getStackSize(); 944 945 if (!FrameSize) return; 946 947 // Get processor type. 948 bool IsPPC64 = Subtarget.isPPC64(); 949 // Check if the link register (LR) has been used. 950 bool UsesLR = MFI->hasCalls() || usesLR(MF); 951 // Do we have a frame pointer for this function? 952 bool HasFP = hasFP(MF); 953 954 // The loaded (or persistent) stack pointer value is offset by the 'stwu' 955 // on entry to the function. Add this offset back now. 956 if (!Subtarget.isPPC64()) { 957 if (isInt16(FrameSize) && TargetAlign >= MaxAlign && 958 !MFI->hasVarSizedObjects()) { 959 BuildMI(MBB, MBBI, TII.get(PPC::ADDI), PPC::R1) 960 .addReg(PPC::R1).addImm(FrameSize); 961 } else { 962 BuildMI(MBB, MBBI, TII.get(PPC::LWZ),PPC::R1).addImm(0).addReg(PPC::R1); 963 } 964 } else { 965 if (isInt16(FrameSize) && TargetAlign >= MaxAlign && 966 !MFI->hasVarSizedObjects()) { 967 BuildMI(MBB, MBBI, TII.get(PPC::ADDI8), PPC::X1) 968 .addReg(PPC::X1).addImm(FrameSize); 969 } else { 970 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X1).addImm(0).addReg(PPC::X1); 971 } 972 } 973 974 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64); 975 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64); 976 977 if (IsPPC64) { 978 if (UsesLR) 979 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X0) 980 .addImm(LROffset/4).addReg(PPC::X1); 981 982 if (HasFP) 983 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X31) 984 .addImm(FPOffset/4).addReg(PPC::X1); 985 986 if (UsesLR) 987 BuildMI(MBB, MBBI, TII.get(PPC::MTLR8)).addReg(PPC::X0); 988 } else { 989 if (UsesLR) 990 BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R0) 991 .addImm(LROffset).addReg(PPC::R1); 992 993 if (HasFP) 994 BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R31) 995 .addImm(FPOffset).addReg(PPC::R1); 996 997 if (UsesLR) 998 BuildMI(MBB, MBBI, TII.get(PPC::MTLR)).addReg(PPC::R0); 999 } 1000 } 1001 1002 unsigned PPCRegisterInfo::getRARegister() const { 1003 return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8; 1004 1005 } 1006 1007 unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const { 1008 if (!Subtarget.isPPC64()) 1009 return hasFP(MF) ? PPC::R31 : PPC::R1; 1010 else 1011 return hasFP(MF) ? PPC::X31 : PPC::X1; 1012 } 1013 1014 void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) 1015 const { 1016 // Initial state of the frame pointer is R1. 1017 MachineLocation Dst(MachineLocation::VirtualFP); 1018 MachineLocation Src(PPC::R1, 0); 1019 Moves.push_back(MachineMove(0, Dst, Src)); 1020 } 1021 1022 #include "PPCGenRegisterInfo.inc" 1023 1024