1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the TargetRegisterInfo 11 // class. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #define DEBUG_TYPE "reginfo" 16 #include "PPC.h" 17 #include "PPCInstrBuilder.h" 18 #include "PPCMachineFunctionInfo.h" 19 #include "PPCRegisterInfo.h" 20 #include "PPCFrameInfo.h" 21 #include "PPCSubtarget.h" 22 #include "llvm/Constants.h" 23 #include "llvm/Type.h" 24 #include "llvm/CodeGen/ValueTypes.h" 25 #include "llvm/CodeGen/MachineInstrBuilder.h" 26 #include "llvm/CodeGen/MachineModuleInfo.h" 27 #include "llvm/CodeGen/MachineFunction.h" 28 #include "llvm/CodeGen/MachineFrameInfo.h" 29 #include "llvm/CodeGen/MachineLocation.h" 30 #include "llvm/CodeGen/MachineRegisterInfo.h" 31 #include "llvm/CodeGen/RegisterScavenging.h" 32 #include "llvm/CodeGen/SelectionDAGNodes.h" 33 #include "llvm/Target/TargetFrameInfo.h" 34 #include "llvm/Target/TargetInstrInfo.h" 35 #include "llvm/Target/TargetMachine.h" 36 #include "llvm/Target/TargetOptions.h" 37 #include "llvm/Support/CommandLine.h" 38 #include "llvm/Support/Debug.h" 39 #include "llvm/Support/MathExtras.h" 40 #include "llvm/ADT/BitVector.h" 41 #include "llvm/ADT/STLExtras.h" 42 #include <cstdlib> 43 using namespace llvm; 44 45 // FIXME This disables some code that aligns the stack to a boundary 46 // bigger than the default (16 bytes on Darwin) when there is a stack local 47 // of greater alignment. This does not currently work, because the delta 48 // between old and new stack pointers is added to offsets that reference 49 // incoming parameters after the prolog is generated, and the code that 50 // does that doesn't handle a variable delta. You don't want to do that 51 // anyway; a better approach is to reserve another register that retains 52 // to the incoming stack pointer, and reference parameters relative to that. 53 #define ALIGN_STACK 0 54 55 // FIXME (64-bit): Eventually enable by default. 56 cl::opt<bool> EnablePPC32RS("enable-ppc32-regscavenger", 57 cl::init(false), 58 cl::desc("Enable PPC32 register scavenger"), 59 cl::Hidden); 60 cl::opt<bool> EnablePPC64RS("enable-ppc64-regscavenger", 61 cl::init(false), 62 cl::desc("Enable PPC64 register scavenger"), 63 cl::Hidden); 64 #define EnableRegisterScavenging \ 65 ((EnablePPC32RS && !Subtarget.isPPC64()) || \ 66 (EnablePPC64RS && Subtarget.isPPC64())) 67 68 // FIXME (64-bit): Should be inlined. 69 bool 70 PPCRegisterInfo::requiresRegisterScavenging(const MachineFunction &) const { 71 return EnableRegisterScavenging; 72 } 73 74 /// getRegisterNumbering - Given the enum value for some register, e.g. 75 /// PPC::F14, return the number that it corresponds to (e.g. 14). 76 unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) { 77 using namespace PPC; 78 switch (RegEnum) { 79 case 0: return 0; 80 case R0 : case X0 : case F0 : case V0 : case CR0: case CR0LT: return 0; 81 case R1 : case X1 : case F1 : case V1 : case CR1: case CR0GT: return 1; 82 case R2 : case X2 : case F2 : case V2 : case CR2: case CR0EQ: return 2; 83 case R3 : case X3 : case F3 : case V3 : case CR3: case CR0UN: return 3; 84 case R4 : case X4 : case F4 : case V4 : case CR4: case CR1LT: return 4; 85 case R5 : case X5 : case F5 : case V5 : case CR5: case CR1GT: return 5; 86 case R6 : case X6 : case F6 : case V6 : case CR6: case CR1EQ: return 6; 87 case R7 : case X7 : case F7 : case V7 : case CR7: case CR1UN: return 7; 88 case R8 : case X8 : case F8 : case V8 : case CR2LT: return 8; 89 case R9 : case X9 : case F9 : case V9 : case CR2GT: return 9; 90 case R10: case X10: case F10: case V10: case CR2EQ: return 10; 91 case R11: case X11: case F11: case V11: case CR2UN: return 11; 92 case R12: case X12: case F12: case V12: case CR3LT: return 12; 93 case R13: case X13: case F13: case V13: case CR3GT: return 13; 94 case R14: case X14: case F14: case V14: case CR3EQ: return 14; 95 case R15: case X15: case F15: case V15: case CR3UN: return 15; 96 case R16: case X16: case F16: case V16: case CR4LT: return 16; 97 case R17: case X17: case F17: case V17: case CR4GT: return 17; 98 case R18: case X18: case F18: case V18: case CR4EQ: return 18; 99 case R19: case X19: case F19: case V19: case CR4UN: return 19; 100 case R20: case X20: case F20: case V20: case CR5LT: return 20; 101 case R21: case X21: case F21: case V21: case CR5GT: return 21; 102 case R22: case X22: case F22: case V22: case CR5EQ: return 22; 103 case R23: case X23: case F23: case V23: case CR5UN: return 23; 104 case R24: case X24: case F24: case V24: case CR6LT: return 24; 105 case R25: case X25: case F25: case V25: case CR6GT: return 25; 106 case R26: case X26: case F26: case V26: case CR6EQ: return 26; 107 case R27: case X27: case F27: case V27: case CR6UN: return 27; 108 case R28: case X28: case F28: case V28: case CR7LT: return 28; 109 case R29: case X29: case F29: case V29: case CR7GT: return 29; 110 case R30: case X30: case F30: case V30: case CR7EQ: return 30; 111 case R31: case X31: case F31: case V31: case CR7UN: return 31; 112 default: 113 cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n"; 114 abort(); 115 } 116 } 117 118 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST, 119 const TargetInstrInfo &tii) 120 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP), 121 Subtarget(ST), TII(tii) { 122 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 123 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 124 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 125 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 126 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 127 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 128 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 129 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 130 131 // 64-bit 132 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8; 133 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8; 134 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8; 135 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX; 136 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32; 137 } 138 139 const unsigned* 140 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 141 // 32-bit Darwin calling convention. 142 static const unsigned Macho32_CalleeSavedRegs[] = { 143 PPC::R13, PPC::R14, PPC::R15, 144 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 145 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 146 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 147 PPC::R28, PPC::R29, PPC::R30, PPC::R31, 148 149 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 150 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 151 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 152 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 153 PPC::F30, PPC::F31, 154 155 PPC::CR2, PPC::CR3, PPC::CR4, 156 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 157 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 158 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 159 160 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 161 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 162 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 163 164 PPC::LR, 0 165 }; 166 167 static const unsigned ELF32_CalleeSavedRegs[] = { 168 PPC::R13, PPC::R14, PPC::R15, 169 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 170 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 171 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 172 PPC::R28, PPC::R29, PPC::R30, PPC::R31, 173 174 PPC::F9, 175 PPC::F10, PPC::F11, PPC::F12, PPC::F13, 176 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 177 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 178 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 179 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 180 PPC::F30, PPC::F31, 181 182 PPC::CR2, PPC::CR3, PPC::CR4, 183 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 184 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 185 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 186 187 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 188 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 189 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 190 191 PPC::LR, 0 192 }; 193 // 64-bit Darwin calling convention. 194 static const unsigned Macho64_CalleeSavedRegs[] = { 195 PPC::X14, PPC::X15, 196 PPC::X16, PPC::X17, PPC::X18, PPC::X19, 197 PPC::X20, PPC::X21, PPC::X22, PPC::X23, 198 PPC::X24, PPC::X25, PPC::X26, PPC::X27, 199 PPC::X28, PPC::X29, PPC::X30, PPC::X31, 200 201 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 202 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 203 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 204 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 205 PPC::F30, PPC::F31, 206 207 PPC::CR2, PPC::CR3, PPC::CR4, 208 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 209 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 210 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 211 212 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 213 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 214 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 215 216 PPC::LR8, 0 217 }; 218 219 if (Subtarget.isMachoABI()) 220 return Subtarget.isPPC64() ? Macho64_CalleeSavedRegs : 221 Macho32_CalleeSavedRegs; 222 223 // ELF 32. 224 return ELF32_CalleeSavedRegs; 225 } 226 227 const TargetRegisterClass* const* 228 PPCRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const { 229 // 32-bit Macho calling convention. 230 static const TargetRegisterClass * const Macho32_CalleeSavedRegClasses[] = { 231 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 232 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 233 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 234 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 235 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 236 237 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 238 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 239 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 240 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 241 &PPC::F8RCRegClass,&PPC::F8RCRegClass, 242 243 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, 244 245 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 246 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 247 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 248 249 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 250 &PPC::CRBITRCRegClass, 251 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 252 &PPC::CRBITRCRegClass, 253 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 254 &PPC::CRBITRCRegClass, 255 256 &PPC::GPRCRegClass, 0 257 }; 258 259 static const TargetRegisterClass * const ELF32_CalleeSavedRegClasses[] = { 260 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 261 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 262 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 263 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 264 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 265 266 &PPC::F8RCRegClass, 267 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 268 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 269 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 270 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 271 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 272 &PPC::F8RCRegClass,&PPC::F8RCRegClass, 273 274 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, 275 276 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 277 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 278 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 279 280 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 281 &PPC::CRBITRCRegClass, 282 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 283 &PPC::CRBITRCRegClass, 284 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 285 &PPC::CRBITRCRegClass, 286 287 &PPC::GPRCRegClass, 0 288 }; 289 290 // 64-bit Macho calling convention. 291 static const TargetRegisterClass * const Macho64_CalleeSavedRegClasses[] = { 292 &PPC::G8RCRegClass,&PPC::G8RCRegClass, 293 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 294 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 295 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 296 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 297 298 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 299 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 300 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 301 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 302 &PPC::F8RCRegClass,&PPC::F8RCRegClass, 303 304 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, 305 306 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 307 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 308 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 309 310 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 311 &PPC::CRBITRCRegClass, 312 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 313 &PPC::CRBITRCRegClass, 314 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 315 &PPC::CRBITRCRegClass, 316 317 &PPC::G8RCRegClass, 0 318 }; 319 320 if (Subtarget.isMachoABI()) 321 return Subtarget.isPPC64() ? Macho64_CalleeSavedRegClasses : 322 Macho32_CalleeSavedRegClasses; 323 324 // ELF 32. 325 return ELF32_CalleeSavedRegClasses; 326 } 327 328 // needsFP - Return true if the specified function should have a dedicated frame 329 // pointer register. This is true if the function has variable sized allocas or 330 // if frame pointer elimination is disabled. 331 // 332 static bool needsFP(const MachineFunction &MF) { 333 const MachineFrameInfo *MFI = MF.getFrameInfo(); 334 return NoFramePointerElim || MFI->hasVarSizedObjects(); 335 } 336 337 static bool spillsCR(const MachineFunction &MF) { 338 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 339 return FuncInfo->isCRSpilled(); 340 } 341 342 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 343 BitVector Reserved(getNumRegs()); 344 Reserved.set(PPC::R0); 345 Reserved.set(PPC::R1); 346 Reserved.set(PPC::LR); 347 Reserved.set(PPC::LR8); 348 349 // In Linux, r2 is reserved for the OS. 350 if (!Subtarget.isDarwin()) 351 Reserved.set(PPC::R2); 352 353 // On PPC64, r13 is the thread pointer. Never allocate this register. Note 354 // that this is over conservative, as it also prevents allocation of R31 when 355 // the FP is not needed. 356 if (Subtarget.isPPC64()) { 357 Reserved.set(PPC::R13); 358 Reserved.set(PPC::R31); 359 360 if (!EnableRegisterScavenging) 361 Reserved.set(PPC::R0); // FIXME (64-bit): Remove 362 363 Reserved.set(PPC::X0); 364 Reserved.set(PPC::X1); 365 Reserved.set(PPC::X13); 366 Reserved.set(PPC::X31); 367 } 368 369 if (needsFP(MF)) 370 Reserved.set(PPC::R31); 371 372 return Reserved; 373 } 374 375 //===----------------------------------------------------------------------===// 376 // Stack Frame Processing methods 377 //===----------------------------------------------------------------------===// 378 379 // hasFP - Return true if the specified function actually has a dedicated frame 380 // pointer register. This is true if the function needs a frame pointer and has 381 // a non-zero stack size. 382 bool PPCRegisterInfo::hasFP(const MachineFunction &MF) const { 383 const MachineFrameInfo *MFI = MF.getFrameInfo(); 384 return MFI->getStackSize() && needsFP(MF); 385 } 386 387 /// MustSaveLR - Return true if this function requires that we save the LR 388 /// register onto the stack in the prolog and restore it in the epilog of the 389 /// function. 390 static bool MustSaveLR(const MachineFunction &MF) { 391 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>(); 392 393 // We need an save/restore of LR if there is any use/def of LR explicitly, or 394 // if there is some use of the LR stack slot (e.g. for builtin_return_address. 395 return MFI->usesLR() || MFI->isLRStoreRequired() || 396 // FIXME: Anything that has a call should clobber the LR register, 397 // isn't this redundant?? 398 MF.getFrameInfo()->hasCalls(); 399 } 400 401 void PPCRegisterInfo:: 402 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 403 MachineBasicBlock::iterator I) const { 404 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions. 405 MBB.erase(I); 406 } 407 408 /// findScratchRegister - Find a 'free' PPC register. Try for a call-clobbered 409 /// register first and then a spilled callee-saved register if that fails. 410 static 411 unsigned findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS, 412 const TargetRegisterClass *RC, int SPAdj) { 413 assert(RS && "Register scavenging must be on"); 414 unsigned Reg = RS->FindUnusedReg(RC, true); 415 // FIXME: move ARM callee-saved reg scan to target independent code, then 416 // search for already spilled CS register here. 417 if (Reg == 0) 418 Reg = RS->scavengeRegister(RC, II, SPAdj); 419 return Reg; 420 } 421 422 /// lowerDynamicAlloc - Generate the code for allocating an object in the 423 /// current frame. The sequence of code with be in the general form 424 /// 425 /// addi R0, SP, #frameSize ; get the address of the previous frame 426 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size 427 /// addi Rnew, SP, #maxCalFrameSize ; get the top of the allocation 428 /// 429 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II, 430 int SPAdj, RegScavenger *RS) const { 431 // Get the instruction. 432 MachineInstr &MI = *II; 433 // Get the instruction's basic block. 434 MachineBasicBlock &MBB = *MI.getParent(); 435 // Get the basic block's function. 436 MachineFunction &MF = *MBB.getParent(); 437 // Get the frame info. 438 MachineFrameInfo *MFI = MF.getFrameInfo(); 439 // Determine whether 64-bit pointers are used. 440 bool LP64 = Subtarget.isPPC64(); 441 442 // Get the maximum call stack size. 443 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 444 // Get the total frame size. 445 unsigned FrameSize = MFI->getStackSize(); 446 447 // Get stack alignments. 448 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 449 unsigned MaxAlign = MFI->getMaxAlignment(); 450 assert(MaxAlign <= TargetAlign && 451 "Dynamic alloca with large aligns not supported"); 452 453 // Determine the previous frame's address. If FrameSize can't be 454 // represented as 16 bits or we need special alignment, then we load the 455 // previous frame's address from 0(SP). Why not do an addis of the hi? 456 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. 457 // Constructing the constant and adding would take 3 instructions. 458 // Fortunately, a frame greater than 32K is rare. 459 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 460 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 461 const TargetRegisterClass *RC = LP64 ? G8RC : GPRC; 462 463 // FIXME (64-bit): Use "findScratchRegister" 464 unsigned Reg; 465 if (EnableRegisterScavenging) 466 Reg = findScratchRegister(II, RS, RC, SPAdj); 467 else 468 Reg = PPC::R0; 469 470 if (MaxAlign < TargetAlign && isInt16(FrameSize)) { 471 BuildMI(MBB, II, TII.get(PPC::ADDI), Reg) 472 .addReg(PPC::R31) 473 .addImm(FrameSize); 474 } else if (LP64) { 475 if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part. 476 BuildMI(MBB, II, TII.get(PPC::LD), Reg) 477 .addImm(0) 478 .addReg(PPC::X1); 479 else 480 BuildMI(MBB, II, TII.get(PPC::LD), PPC::X0) 481 .addImm(0) 482 .addReg(PPC::X1); 483 } else { 484 BuildMI(MBB, II, TII.get(PPC::LWZ), Reg) 485 .addImm(0) 486 .addReg(PPC::R1); 487 } 488 489 // Grow the stack and update the stack pointer link, then determine the 490 // address of new allocated space. 491 if (LP64) { 492 if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part. 493 BuildMI(MBB, II, TII.get(PPC::STDUX)) 494 .addReg(Reg, false, false, true) 495 .addReg(PPC::X1) 496 .addReg(MI.getOperand(1).getReg()); 497 else 498 BuildMI(MBB, II, TII.get(PPC::STDUX)) 499 .addReg(PPC::X0, false, false, true) 500 .addReg(PPC::X1) 501 .addReg(MI.getOperand(1).getReg()); 502 503 if (!MI.getOperand(1).isKill()) 504 BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 505 .addReg(PPC::X1) 506 .addImm(maxCallFrameSize); 507 else 508 // Implicitly kill the register. 509 BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 510 .addReg(PPC::X1) 511 .addImm(maxCallFrameSize) 512 .addReg(MI.getOperand(1).getReg(), false, true, true); 513 } else { 514 BuildMI(MBB, II, TII.get(PPC::STWUX)) 515 .addReg(Reg, false, false, true) 516 .addReg(PPC::R1) 517 .addReg(MI.getOperand(1).getReg()); 518 519 if (!MI.getOperand(1).isKill()) 520 BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 521 .addReg(PPC::R1) 522 .addImm(maxCallFrameSize); 523 else 524 // Implicitly kill the register. 525 BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 526 .addReg(PPC::R1) 527 .addImm(maxCallFrameSize) 528 .addReg(MI.getOperand(1).getReg(), false, true, true); 529 } 530 531 // Discard the DYNALLOC instruction. 532 MBB.erase(II); 533 } 534 535 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of 536 /// reserving a whole register (R0), we scrounge for one here. This generates 537 /// code like this: 538 /// 539 /// mfcr rA ; Move the conditional register into GPR rA. 540 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot. 541 /// stw rA, FI ; Store rA to the frame. 542 /// 543 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, 544 unsigned FrameIndex, int SPAdj, 545 RegScavenger *RS) const { 546 // Get the instruction. 547 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>, <FI> 548 // Get the instruction's basic block. 549 MachineBasicBlock &MBB = *MI.getParent(); 550 551 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 552 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 553 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC; 554 unsigned Reg = findScratchRegister(II, RS, RC, SPAdj); 555 556 // We need to store the CR in the low 4-bits of the saved value. First, issue 557 // an MFCR to save all of the CRBits. Add an implicit kill of the CR. 558 if (!MI.getOperand(0).isKill()) 559 BuildMI(MBB, II, TII.get(PPC::MFCR), Reg); 560 else 561 // Implicitly kill the CR register. 562 BuildMI(MBB, II, TII.get(PPC::MFCR), Reg) 563 .addReg(MI.getOperand(0).getReg(), false, true, true); 564 565 // If the saved register wasn't CR0, shift the bits left so that they are in 566 // CR0's slot. 567 unsigned SrcReg = MI.getOperand(0).getReg(); 568 if (SrcReg != PPC::CR0) 569 // rlwinm rA, rA, ShiftBits, 0, 31. 570 BuildMI(MBB, II, TII.get(PPC::RLWINM), Reg) 571 .addReg(Reg, false, false, true) 572 .addImm(PPCRegisterInfo::getRegisterNumbering(SrcReg) * 4) 573 .addImm(0) 574 .addImm(31); 575 576 addFrameReference(BuildMI(MBB, II, TII.get(PPC::STW)) 577 .addReg(Reg, false, false, MI.getOperand(1).getImm()), 578 FrameIndex); 579 580 // Discard the pseudo instruction. 581 MBB.erase(II); 582 } 583 584 void PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 585 int SPAdj, RegScavenger *RS) const { 586 assert(SPAdj == 0 && "Unexpected"); 587 588 // Get the instruction. 589 MachineInstr &MI = *II; 590 // Get the instruction's basic block. 591 MachineBasicBlock &MBB = *MI.getParent(); 592 // Get the basic block's function. 593 MachineFunction &MF = *MBB.getParent(); 594 // Get the frame info. 595 MachineFrameInfo *MFI = MF.getFrameInfo(); 596 597 // Find out which operand is the frame index. 598 unsigned FIOperandNo = 0; 599 while (!MI.getOperand(FIOperandNo).isFrameIndex()) { 600 ++FIOperandNo; 601 assert(FIOperandNo != MI.getNumOperands() && 602 "Instr doesn't have FrameIndex operand!"); 603 } 604 // Take into account whether it's an add or mem instruction 605 unsigned OffsetOperandNo = (FIOperandNo == 2) ? 1 : 2; 606 if (MI.getOpcode() == TargetInstrInfo::INLINEASM) 607 OffsetOperandNo = FIOperandNo-1; 608 609 // Get the frame index. 610 int FrameIndex = MI.getOperand(FIOperandNo).getIndex(); 611 612 // Get the frame pointer save index. Users of this index are primarily 613 // DYNALLOC instructions. 614 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 615 int FPSI = FI->getFramePointerSaveIndex(); 616 // Get the instruction opcode. 617 unsigned OpC = MI.getOpcode(); 618 619 // Special case for dynamic alloca. 620 if (FPSI && FrameIndex == FPSI && 621 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { 622 lowerDynamicAlloc(II, SPAdj, RS); 623 return; 624 } 625 626 // Special case for pseudo-op SPILL_CR. 627 if (EnableRegisterScavenging) // FIXME (64-bit): Enable by default. 628 if (OpC == PPC::SPILL_CR) { 629 lowerCRSpilling(II, FrameIndex, SPAdj, RS); 630 return; 631 } 632 633 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 634 MI.getOperand(FIOperandNo).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1, 635 false); 636 637 // Figure out if the offset in the instruction is shifted right two bits. This 638 // is true for instructions like "STD", which the machine implicitly adds two 639 // low zeros to. 640 bool isIXAddr = false; 641 switch (OpC) { 642 case PPC::LWA: 643 case PPC::LD: 644 case PPC::STD: 645 case PPC::STD_32: 646 isIXAddr = true; 647 break; 648 } 649 650 // Now add the frame object offset to the offset from r1. 651 int Offset = MFI->getObjectOffset(FrameIndex); 652 if (!isIXAddr) 653 Offset += MI.getOperand(OffsetOperandNo).getImm(); 654 else 655 Offset += MI.getOperand(OffsetOperandNo).getImm() << 2; 656 657 // If we're not using a Frame Pointer that has been set to the value of the 658 // SP before having the stack size subtracted from it, then add the stack size 659 // to Offset to get the correct offset. 660 Offset += MFI->getStackSize(); 661 662 // If we can, encode the offset directly into the instruction. If this is a 663 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If 664 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits 665 // clear can be encoded. This is extremely uncommon, because normally you 666 // only "std" to a stack slot that is at least 4-byte aligned, but it can 667 // happen in invalid code. 668 if (isInt16(Offset) && (!isIXAddr || (Offset & 3) == 0)) { 669 if (isIXAddr) 670 Offset >>= 2; // The actual encoded value has the low two bits zero. 671 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 672 return; 673 } 674 675 // The offset doesn't fit into a single register, scavenge one to build the 676 // offset in. 677 // FIXME: figure out what SPAdj is doing here. 678 679 // FIXME (64-bit): Use "findScratchRegister". 680 unsigned SReg; 681 if (EnableRegisterScavenging) 682 SReg = findScratchRegister(II, RS, &PPC::GPRCRegClass, SPAdj); 683 else 684 SReg = PPC::R0; 685 686 // Insert a set of rA with the full offset value before the ld, st, or add 687 BuildMI(MBB, II, TII.get(PPC::LIS), SReg) 688 .addImm(Offset >> 16); 689 BuildMI(MBB, II, TII.get(PPC::ORI), SReg) 690 .addReg(SReg, false, false, true) 691 .addImm(Offset); 692 693 // Convert into indexed form of the instruction: 694 // 695 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 696 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 697 unsigned OperandBase; 698 699 if (OpC != TargetInstrInfo::INLINEASM) { 700 assert(ImmToIdxMap.count(OpC) && 701 "No indexed form of load or store available!"); 702 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; 703 MI.setDesc(TII.get(NewOpcode)); 704 OperandBase = 1; 705 } else { 706 OperandBase = OffsetOperandNo; 707 } 708 709 unsigned StackReg = MI.getOperand(FIOperandNo).getReg(); 710 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false); 711 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false); 712 } 713 714 /// VRRegNo - Map from a numbered VR register to its enum value. 715 /// 716 static const unsigned short VRRegNo[] = { 717 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 , 718 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, 719 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, 720 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31 721 }; 722 723 /// RemoveVRSaveCode - We have found that this function does not need any code 724 /// to manipulate the VRSAVE register, even though it uses vector registers. 725 /// This can happen when the only registers used are known to be live in or out 726 /// of the function. Remove all of the VRSAVE related code from the function. 727 static void RemoveVRSaveCode(MachineInstr *MI) { 728 MachineBasicBlock *Entry = MI->getParent(); 729 MachineFunction *MF = Entry->getParent(); 730 731 // We know that the MTVRSAVE instruction immediately follows MI. Remove it. 732 MachineBasicBlock::iterator MBBI = MI; 733 ++MBBI; 734 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE); 735 MBBI->eraseFromParent(); 736 737 bool RemovedAllMTVRSAVEs = true; 738 // See if we can find and remove the MTVRSAVE instruction from all of the 739 // epilog blocks. 740 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) { 741 // If last instruction is a return instruction, add an epilogue 742 if (!I->empty() && I->back().getDesc().isReturn()) { 743 bool FoundIt = false; 744 for (MBBI = I->end(); MBBI != I->begin(); ) { 745 --MBBI; 746 if (MBBI->getOpcode() == PPC::MTVRSAVE) { 747 MBBI->eraseFromParent(); // remove it. 748 FoundIt = true; 749 break; 750 } 751 } 752 RemovedAllMTVRSAVEs &= FoundIt; 753 } 754 } 755 756 // If we found and removed all MTVRSAVE instructions, remove the read of 757 // VRSAVE as well. 758 if (RemovedAllMTVRSAVEs) { 759 MBBI = MI; 760 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?"); 761 --MBBI; 762 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?"); 763 MBBI->eraseFromParent(); 764 } 765 766 // Finally, nuke the UPDATE_VRSAVE. 767 MI->eraseFromParent(); 768 } 769 770 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the 771 // instruction selector. Based on the vector registers that have been used, 772 // transform this into the appropriate ORI instruction. 773 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) { 774 MachineFunction *MF = MI->getParent()->getParent(); 775 776 unsigned UsedRegMask = 0; 777 for (unsigned i = 0; i != 32; ++i) 778 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i])) 779 UsedRegMask |= 1 << (31-i); 780 781 // Live in and live out values already must be in the mask, so don't bother 782 // marking them. 783 for (MachineRegisterInfo::livein_iterator 784 I = MF->getRegInfo().livein_begin(), 785 E = MF->getRegInfo().livein_end(); I != E; ++I) { 786 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first); 787 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg. 788 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 789 } 790 for (MachineRegisterInfo::liveout_iterator 791 I = MF->getRegInfo().liveout_begin(), 792 E = MF->getRegInfo().liveout_end(); I != E; ++I) { 793 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I); 794 if (VRRegNo[RegNo] == *I) // If this really is a vector reg. 795 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 796 } 797 798 // If no registers are used, turn this into a copy. 799 if (UsedRegMask == 0) { 800 // Remove all VRSAVE code. 801 RemoveVRSaveCode(MI); 802 return; 803 } 804 805 unsigned SrcReg = MI->getOperand(1).getReg(); 806 unsigned DstReg = MI->getOperand(0).getReg(); 807 808 if ((UsedRegMask & 0xFFFF) == UsedRegMask) { 809 if (DstReg != SrcReg) 810 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg) 811 .addReg(SrcReg) 812 .addImm(UsedRegMask); 813 else 814 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg) 815 .addReg(SrcReg, false, false, true) 816 .addImm(UsedRegMask); 817 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { 818 if (DstReg != SrcReg) 819 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) 820 .addReg(SrcReg) 821 .addImm(UsedRegMask >> 16); 822 else 823 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) 824 .addReg(SrcReg, false, false, true) 825 .addImm(UsedRegMask >> 16); 826 } else { 827 if (DstReg != SrcReg) 828 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) 829 .addReg(SrcReg) 830 .addImm(UsedRegMask >> 16); 831 else 832 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) 833 .addReg(SrcReg, false, false, true) 834 .addImm(UsedRegMask >> 16); 835 836 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg) 837 .addReg(DstReg, false, false, true) 838 .addImm(UsedRegMask & 0xFFFF); 839 } 840 841 // Remove the old UPDATE_VRSAVE instruction. 842 MI->eraseFromParent(); 843 } 844 845 /// determineFrameLayout - Determine the size of the frame and maximum call 846 /// frame size. 847 void PPCRegisterInfo::determineFrameLayout(MachineFunction &MF) const { 848 MachineFrameInfo *MFI = MF.getFrameInfo(); 849 850 // Get the number of bytes to allocate from the FrameInfo 851 unsigned FrameSize = MFI->getStackSize(); 852 853 // Get the alignments provided by the target, and the maximum alignment 854 // (if any) of the fixed frame objects. 855 unsigned MaxAlign = MFI->getMaxAlignment(); 856 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 857 unsigned AlignMask = TargetAlign - 1; // 858 859 // If we are a leaf function, and use up to 224 bytes of stack space, 860 // don't have a frame pointer, calls, or dynamic alloca then we do not need 861 // to adjust the stack pointer (we fit in the Red Zone). 862 if (FrameSize <= 224 && // Fits in red zone. 863 !MFI->hasVarSizedObjects() && // No dynamic alloca. 864 !MFI->hasCalls() && // No calls. 865 (!ALIGN_STACK || MaxAlign <= TargetAlign)) { // No special alignment. 866 // No need for frame 867 MFI->setStackSize(0); 868 return; 869 } 870 871 // Get the maximum call frame size of all the calls. 872 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 873 874 // Maximum call frame needs to be at least big enough for linkage and 8 args. 875 unsigned minCallFrameSize = 876 PPCFrameInfo::getMinCallFrameSize(Subtarget.isPPC64(), 877 Subtarget.isMachoABI()); 878 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize); 879 880 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so 881 // that allocations will be aligned. 882 if (MFI->hasVarSizedObjects()) 883 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask; 884 885 // Update maximum call frame size. 886 MFI->setMaxCallFrameSize(maxCallFrameSize); 887 888 // Include call frame size in total. 889 FrameSize += maxCallFrameSize; 890 891 // Make sure the frame is aligned. 892 FrameSize = (FrameSize + AlignMask) & ~AlignMask; 893 894 // Update frame info. 895 MFI->setStackSize(FrameSize); 896 } 897 898 void 899 PPCRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 900 RegScavenger *RS) const { 901 // Save and clear the LR state. 902 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 903 unsigned LR = getRARegister(); 904 FI->setUsesLR(MF.getRegInfo().isPhysRegUsed(LR)); 905 MF.getRegInfo().setPhysRegUnused(LR); 906 907 // Save R31 if necessary 908 int FPSI = FI->getFramePointerSaveIndex(); 909 bool IsPPC64 = Subtarget.isPPC64(); 910 bool IsELF32_ABI = Subtarget.isELF32_ABI(); 911 bool IsMachoABI = Subtarget.isMachoABI(); 912 MachineFrameInfo *MFI = MF.getFrameInfo(); 913 914 // If the frame pointer save index hasn't been defined yet. 915 if (!FPSI && (NoFramePointerElim || MFI->hasVarSizedObjects()) && 916 IsELF32_ABI) { 917 // Find out what the fix offset of the frame pointer save area. 918 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, 919 IsMachoABI); 920 // Allocate the frame index for frame pointer save area. 921 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset); 922 // Save the result. 923 FI->setFramePointerSaveIndex(FPSI); 924 } 925 926 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or 927 // a large stack, which will require scavenging a register to materialize a 928 // large offset. 929 // FIXME: this doesn't actually check stack size, so is a bit pessimistic 930 // FIXME: doesn't detect whether or not we need to spill vXX, which requires 931 // r0 for now. 932 933 if (EnableRegisterScavenging) // FIXME (64-bit): Enable. 934 if (needsFP(MF) || spillsCR(MF)) { 935 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 936 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 937 const TargetRegisterClass *RC = IsPPC64 ? G8RC : GPRC; 938 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 939 RC->getAlignment())); 940 } 941 } 942 943 void 944 PPCRegisterInfo::emitPrologue(MachineFunction &MF) const { 945 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB 946 MachineBasicBlock::iterator MBBI = MBB.begin(); 947 MachineFrameInfo *MFI = MF.getFrameInfo(); 948 MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); 949 950 // Prepare for frame info. 951 unsigned FrameLabelId = 0; 952 953 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it, 954 // process it. 955 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { 956 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) { 957 HandleVRSaveUpdate(MBBI, TII); 958 break; 959 } 960 } 961 962 // Move MBBI back to the beginning of the function. 963 MBBI = MBB.begin(); 964 965 // Work out frame sizes. 966 determineFrameLayout(MF); 967 unsigned FrameSize = MFI->getStackSize(); 968 969 int NegFrameSize = -FrameSize; 970 971 // Get processor type. 972 bool IsPPC64 = Subtarget.isPPC64(); 973 // Get operating system 974 bool IsMachoABI = Subtarget.isMachoABI(); 975 // Check if the link register (LR) has been used. 976 bool UsesLR = MustSaveLR(MF); 977 // Do we have a frame pointer for this function? 978 bool HasFP = hasFP(MF) && FrameSize; 979 980 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI); 981 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI); 982 983 if (IsPPC64) { 984 if (UsesLR) 985 BuildMI(MBB, MBBI, TII.get(PPC::MFLR8), PPC::X0); 986 987 if (HasFP) 988 BuildMI(MBB, MBBI, TII.get(PPC::STD)) 989 .addReg(PPC::X31) 990 .addImm(FPOffset/4) 991 .addReg(PPC::X1); 992 993 if (UsesLR) 994 BuildMI(MBB, MBBI, TII.get(PPC::STD)) 995 .addReg(PPC::X0) 996 .addImm(LROffset / 4) 997 .addReg(PPC::X1); 998 } else { 999 if (UsesLR) 1000 BuildMI(MBB, MBBI, TII.get(PPC::MFLR), PPC::R0); 1001 1002 if (HasFP) 1003 BuildMI(MBB, MBBI, TII.get(PPC::STW)) 1004 .addReg(PPC::R31) 1005 .addImm(FPOffset) 1006 .addReg(PPC::R1); 1007 1008 if (UsesLR) 1009 BuildMI(MBB, MBBI, TII.get(PPC::STW)) 1010 .addReg(PPC::R0) 1011 .addImm(LROffset) 1012 .addReg(PPC::R1); 1013 } 1014 1015 // Skip if a leaf routine. 1016 if (!FrameSize) return; 1017 1018 // Get stack alignments. 1019 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 1020 unsigned MaxAlign = MFI->getMaxAlignment(); 1021 1022 if (MMI && MMI->needsFrameInfo()) { 1023 // Mark effective beginning of when frame pointer becomes valid. 1024 FrameLabelId = MMI->NextLabelID(); 1025 BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(FrameLabelId).addImm(0); 1026 } 1027 1028 // Adjust stack pointer: r1 += NegFrameSize. 1029 // If there is a preferred stack alignment, align R1 now 1030 if (!IsPPC64) { 1031 // PPC32. 1032 if (ALIGN_STACK && MaxAlign > TargetAlign) { 1033 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!"); 1034 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!"); 1035 1036 BuildMI(MBB, MBBI, TII.get(PPC::RLWINM), PPC::R0) 1037 .addReg(PPC::R1) 1038 .addImm(0) 1039 .addImm(32 - Log2_32(MaxAlign)) 1040 .addImm(31); 1041 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC) ,PPC::R0) 1042 .addReg(PPC::R0, false, false, true) 1043 .addImm(NegFrameSize); 1044 BuildMI(MBB, MBBI, TII.get(PPC::STWUX)) 1045 .addReg(PPC::R1) 1046 .addReg(PPC::R1) 1047 .addReg(PPC::R0); 1048 } else if (isInt16(NegFrameSize)) { 1049 BuildMI(MBB, MBBI, TII.get(PPC::STWU), PPC::R1) 1050 .addReg(PPC::R1) 1051 .addImm(NegFrameSize) 1052 .addReg(PPC::R1); 1053 } else { 1054 BuildMI(MBB, MBBI, TII.get(PPC::LIS), PPC::R0) 1055 .addImm(NegFrameSize >> 16); 1056 BuildMI(MBB, MBBI, TII.get(PPC::ORI), PPC::R0) 1057 .addReg(PPC::R0, false, false, true) 1058 .addImm(NegFrameSize & 0xFFFF); 1059 BuildMI(MBB, MBBI, TII.get(PPC::STWUX)) 1060 .addReg(PPC::R1) 1061 .addReg(PPC::R1) 1062 .addReg(PPC::R0); 1063 } 1064 } else { // PPC64. 1065 if (ALIGN_STACK && MaxAlign > TargetAlign) { 1066 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!"); 1067 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!"); 1068 1069 BuildMI(MBB, MBBI, TII.get(PPC::RLDICL), PPC::X0) 1070 .addReg(PPC::X1) 1071 .addImm(0) 1072 .addImm(64 - Log2_32(MaxAlign)); 1073 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC8), PPC::X0) 1074 .addReg(PPC::X0) 1075 .addImm(NegFrameSize); 1076 BuildMI(MBB, MBBI, TII.get(PPC::STDUX)) 1077 .addReg(PPC::X1) 1078 .addReg(PPC::X1) 1079 .addReg(PPC::X0); 1080 } else if (isInt16(NegFrameSize)) { 1081 BuildMI(MBB, MBBI, TII.get(PPC::STDU), PPC::X1) 1082 .addReg(PPC::X1) 1083 .addImm(NegFrameSize / 4) 1084 .addReg(PPC::X1); 1085 } else { 1086 BuildMI(MBB, MBBI, TII.get(PPC::LIS8), PPC::X0) 1087 .addImm(NegFrameSize >> 16); 1088 BuildMI(MBB, MBBI, TII.get(PPC::ORI8), PPC::X0) 1089 .addReg(PPC::X0, false, false, true) 1090 .addImm(NegFrameSize & 0xFFFF); 1091 BuildMI(MBB, MBBI, TII.get(PPC::STDUX)) 1092 .addReg(PPC::X1) 1093 .addReg(PPC::X1) 1094 .addReg(PPC::X0); 1095 } 1096 } 1097 1098 if (MMI && MMI->needsFrameInfo()) { 1099 std::vector<MachineMove> &Moves = MMI->getFrameMoves(); 1100 1101 if (NegFrameSize) { 1102 // Show update of SP. 1103 MachineLocation SPDst(MachineLocation::VirtualFP); 1104 MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize); 1105 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc)); 1106 } else { 1107 MachineLocation SP(IsPPC64 ? PPC::X31 : PPC::R31); 1108 Moves.push_back(MachineMove(FrameLabelId, SP, SP)); 1109 } 1110 1111 if (HasFP) { 1112 MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset); 1113 MachineLocation FPSrc(IsPPC64 ? PPC::X31 : PPC::R31); 1114 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc)); 1115 } 1116 1117 // Add callee saved registers to move list. 1118 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 1119 for (unsigned I = 0, E = CSI.size(); I != E; ++I) { 1120 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx()); 1121 unsigned Reg = CSI[I].getReg(); 1122 if (Reg == PPC::LR || Reg == PPC::LR8) continue; 1123 MachineLocation CSDst(MachineLocation::VirtualFP, Offset); 1124 MachineLocation CSSrc(Reg); 1125 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc)); 1126 } 1127 1128 MachineLocation LRDst(MachineLocation::VirtualFP, LROffset); 1129 MachineLocation LRSrc(IsPPC64 ? PPC::LR8 : PPC::LR); 1130 Moves.push_back(MachineMove(FrameLabelId, LRDst, LRSrc)); 1131 1132 // Mark effective beginning of when frame pointer is ready. 1133 unsigned ReadyLabelId = MMI->NextLabelID(); 1134 BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(ReadyLabelId).addImm(0); 1135 1136 MachineLocation FPDst(HasFP ? (IsPPC64 ? PPC::X31 : PPC::R31) : 1137 (IsPPC64 ? PPC::X1 : PPC::R1)); 1138 MachineLocation FPSrc(MachineLocation::VirtualFP); 1139 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc)); 1140 } 1141 1142 // If there is a frame pointer, copy R1 into R31 1143 if (HasFP) { 1144 if (!IsPPC64) { 1145 BuildMI(MBB, MBBI, TII.get(PPC::OR), PPC::R31) 1146 .addReg(PPC::R1) 1147 .addReg(PPC::R1); 1148 } else { 1149 BuildMI(MBB, MBBI, TII.get(PPC::OR8), PPC::X31) 1150 .addReg(PPC::X1) 1151 .addReg(PPC::X1); 1152 } 1153 } 1154 } 1155 1156 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF, 1157 MachineBasicBlock &MBB) const { 1158 MachineBasicBlock::iterator MBBI = prior(MBB.end()); 1159 assert(MBBI->getOpcode() == PPC::BLR && 1160 "Can only insert epilog into returning blocks"); 1161 1162 // Get alignment info so we know how to restore r1 1163 const MachineFrameInfo *MFI = MF.getFrameInfo(); 1164 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 1165 unsigned MaxAlign = MFI->getMaxAlignment(); 1166 1167 // Get the number of bytes allocated from the FrameInfo. 1168 unsigned FrameSize = MFI->getStackSize(); 1169 1170 // Get processor type. 1171 bool IsPPC64 = Subtarget.isPPC64(); 1172 // Get operating system 1173 bool IsMachoABI = Subtarget.isMachoABI(); 1174 // Check if the link register (LR) has been used. 1175 bool UsesLR = MustSaveLR(MF); 1176 // Do we have a frame pointer for this function? 1177 bool HasFP = hasFP(MF) && FrameSize; 1178 1179 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI); 1180 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI); 1181 1182 if (FrameSize) { 1183 // The loaded (or persistent) stack pointer value is offset by the 'stwu' 1184 // on entry to the function. Add this offset back now. 1185 if (!Subtarget.isPPC64()) { 1186 if (isInt16(FrameSize) && (!ALIGN_STACK || TargetAlign >= MaxAlign) && 1187 !MFI->hasVarSizedObjects()) { 1188 BuildMI(MBB, MBBI, TII.get(PPC::ADDI), PPC::R1) 1189 .addReg(PPC::R1).addImm(FrameSize); 1190 } else { 1191 BuildMI(MBB, MBBI, TII.get(PPC::LWZ),PPC::R1).addImm(0).addReg(PPC::R1); 1192 } 1193 } else { 1194 if (isInt16(FrameSize) && TargetAlign >= MaxAlign && 1195 !MFI->hasVarSizedObjects()) { 1196 BuildMI(MBB, MBBI, TII.get(PPC::ADDI8), PPC::X1) 1197 .addReg(PPC::X1).addImm(FrameSize); 1198 } else { 1199 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X1).addImm(0).addReg(PPC::X1); 1200 } 1201 } 1202 } 1203 1204 if (IsPPC64) { 1205 if (UsesLR) 1206 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X0) 1207 .addImm(LROffset/4).addReg(PPC::X1); 1208 1209 if (HasFP) 1210 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X31) 1211 .addImm(FPOffset/4).addReg(PPC::X1); 1212 1213 if (UsesLR) 1214 BuildMI(MBB, MBBI, TII.get(PPC::MTLR8)).addReg(PPC::X0); 1215 } else { 1216 if (UsesLR) 1217 BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R0) 1218 .addImm(LROffset).addReg(PPC::R1); 1219 1220 if (HasFP) 1221 BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R31) 1222 .addImm(FPOffset).addReg(PPC::R1); 1223 1224 if (UsesLR) 1225 BuildMI(MBB, MBBI, TII.get(PPC::MTLR)).addReg(PPC::R0); 1226 } 1227 } 1228 1229 unsigned PPCRegisterInfo::getRARegister() const { 1230 return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8; 1231 } 1232 1233 unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const { 1234 if (!Subtarget.isPPC64()) 1235 return hasFP(MF) ? PPC::R31 : PPC::R1; 1236 else 1237 return hasFP(MF) ? PPC::X31 : PPC::X1; 1238 } 1239 1240 void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) 1241 const { 1242 // Initial state of the frame pointer is R1. 1243 MachineLocation Dst(MachineLocation::VirtualFP); 1244 MachineLocation Src(PPC::R1, 0); 1245 Moves.push_back(MachineMove(0, Dst, Src)); 1246 } 1247 1248 unsigned PPCRegisterInfo::getEHExceptionRegister() const { 1249 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3; 1250 } 1251 1252 unsigned PPCRegisterInfo::getEHHandlerRegister() const { 1253 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4; 1254 } 1255 1256 int PPCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { 1257 // FIXME: Most probably dwarf numbers differs for Linux and Darwin 1258 return PPCGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); 1259 } 1260 1261 #include "PPCGenRegisterInfo.inc" 1262 1263