1 //===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the TargetRegisterInfo 11 // class. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #define DEBUG_TYPE "reginfo" 16 #include "PPCRegisterInfo.h" 17 #include "PPC.h" 18 #include "PPCFrameLowering.h" 19 #include "PPCInstrBuilder.h" 20 #include "PPCMachineFunctionInfo.h" 21 #include "PPCSubtarget.h" 22 #include "llvm/ADT/BitVector.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/CodeGen/MachineFrameInfo.h" 25 #include "llvm/CodeGen/MachineFunction.h" 26 #include "llvm/CodeGen/MachineInstrBuilder.h" 27 #include "llvm/CodeGen/MachineModuleInfo.h" 28 #include "llvm/CodeGen/MachineRegisterInfo.h" 29 #include "llvm/CodeGen/RegisterScavenging.h" 30 #include "llvm/CodeGen/ValueTypes.h" 31 #include "llvm/IR/CallingConv.h" 32 #include "llvm/IR/Constants.h" 33 #include "llvm/IR/Function.h" 34 #include "llvm/IR/Type.h" 35 #include "llvm/Support/CommandLine.h" 36 #include "llvm/Support/Debug.h" 37 #include "llvm/Support/ErrorHandling.h" 38 #include "llvm/Support/MathExtras.h" 39 #include "llvm/Support/raw_ostream.h" 40 #include "llvm/Target/TargetFrameLowering.h" 41 #include "llvm/Target/TargetInstrInfo.h" 42 #include "llvm/Target/TargetMachine.h" 43 #include "llvm/Target/TargetOptions.h" 44 #include <cstdlib> 45 46 #define GET_REGINFO_TARGET_DESC 47 #include "PPCGenRegisterInfo.inc" 48 49 using namespace llvm; 50 51 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST, 52 const TargetInstrInfo &tii) 53 : PPCGenRegisterInfo(ST.isPPC64() ? PPC::LR8 : PPC::LR, 54 ST.isPPC64() ? 0 : 1, 55 ST.isPPC64() ? 0 : 1), 56 Subtarget(ST), TII(tii) { 57 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 58 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 59 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 60 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 61 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 62 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 63 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 64 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 65 66 // 64-bit 67 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8; 68 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8; 69 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8; 70 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX; 71 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32; 72 } 73 74 bool 75 PPCRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const { 76 return requiresRegisterScavenging(MF); 77 } 78 79 80 /// getPointerRegClass - Return the register class to use to hold pointers. 81 /// This is used for addressing modes. 82 const TargetRegisterClass * 83 PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) 84 const { 85 if (Subtarget.isPPC64()) 86 return &PPC::G8RCRegClass; 87 return &PPC::GPRCRegClass; 88 } 89 90 const uint16_t* 91 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 92 if (Subtarget.isDarwinABI()) 93 return Subtarget.isPPC64() ? CSR_Darwin64_SaveList : 94 CSR_Darwin32_SaveList; 95 96 return Subtarget.isPPC64() ? CSR_SVR464_SaveList : CSR_SVR432_SaveList; 97 } 98 99 const uint32_t* 100 PPCRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const { 101 if (Subtarget.isDarwinABI()) 102 return Subtarget.isPPC64() ? CSR_Darwin64_RegMask : 103 CSR_Darwin32_RegMask; 104 105 return Subtarget.isPPC64() ? CSR_SVR464_RegMask : CSR_SVR432_RegMask; 106 } 107 108 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 109 BitVector Reserved(getNumRegs()); 110 const PPCFrameLowering *PPCFI = 111 static_cast<const PPCFrameLowering*>(MF.getTarget().getFrameLowering()); 112 113 Reserved.set(PPC::R0); 114 Reserved.set(PPC::R1); 115 Reserved.set(PPC::LR); 116 Reserved.set(PPC::LR8); 117 Reserved.set(PPC::RM); 118 119 // The SVR4 ABI reserves r2 and r13 120 if (Subtarget.isSVR4ABI()) { 121 Reserved.set(PPC::R2); // System-reserved register 122 Reserved.set(PPC::R13); // Small Data Area pointer register 123 } 124 // Reserve R2 on Darwin to hack around the problem of save/restore of CR 125 // when the stack frame is too big to address directly; we need two regs. 126 // This is a hack. 127 if (Subtarget.isDarwinABI()) { 128 Reserved.set(PPC::R2); 129 } 130 131 // On PPC64, r13 is the thread pointer. Never allocate this register. 132 // Note that this is over conservative, as it also prevents allocation of R31 133 // when the FP is not needed. 134 if (Subtarget.isPPC64()) { 135 Reserved.set(PPC::R13); 136 Reserved.set(PPC::R31); 137 138 Reserved.set(PPC::X0); 139 Reserved.set(PPC::X1); 140 Reserved.set(PPC::X13); 141 Reserved.set(PPC::X31); 142 143 // The 64-bit SVR4 ABI reserves r2 for the TOC pointer. 144 if (Subtarget.isSVR4ABI()) { 145 Reserved.set(PPC::X2); 146 } 147 // Reserve X2 on Darwin to hack around the problem of save/restore of CR 148 // when the stack frame is too big to address directly; we need two regs. 149 // This is a hack. 150 if (Subtarget.isDarwinABI()) { 151 Reserved.set(PPC::X2); 152 } 153 } 154 155 if (PPCFI->needsFP(MF)) 156 Reserved.set(PPC::R31); 157 158 return Reserved; 159 } 160 161 unsigned 162 PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 163 MachineFunction &MF) const { 164 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 165 const unsigned DefaultSafety = 1; 166 167 switch (RC->getID()) { 168 default: 169 return 0; 170 case PPC::G8RCRegClassID: 171 case PPC::GPRCRegClassID: { 172 unsigned FP = TFI->hasFP(MF) ? 1 : 0; 173 return 32 - FP - DefaultSafety; 174 } 175 case PPC::F8RCRegClassID: 176 case PPC::F4RCRegClassID: 177 case PPC::VRRCRegClassID: 178 return 32 - DefaultSafety; 179 case PPC::CRRCRegClassID: 180 return 8 - DefaultSafety; 181 } 182 } 183 184 bool 185 PPCRegisterInfo::avoidWriteAfterWrite(const TargetRegisterClass *RC) const { 186 switch (RC->getID()) { 187 case PPC::G8RCRegClassID: 188 case PPC::GPRCRegClassID: 189 case PPC::F8RCRegClassID: 190 case PPC::F4RCRegClassID: 191 case PPC::VRRCRegClassID: 192 return true; 193 default: 194 return false; 195 } 196 } 197 198 //===----------------------------------------------------------------------===// 199 // Stack Frame Processing methods 200 //===----------------------------------------------------------------------===// 201 202 /// findScratchRegister - Find a 'free' PPC register. Try for a call-clobbered 203 /// register first and then a spilled callee-saved register if that fails. 204 static 205 unsigned findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS, 206 const TargetRegisterClass *RC, int SPAdj) { 207 assert(RS && "Register scavenging must be on"); 208 unsigned Reg = RS->FindUnusedReg(RC); 209 // FIXME: move ARM callee-saved reg scan to target independent code, then 210 // search for already spilled CS register here. 211 if (Reg == 0) 212 Reg = RS->scavengeRegister(RC, II, SPAdj); 213 return Reg; 214 } 215 216 /// lowerDynamicAlloc - Generate the code for allocating an object in the 217 /// current frame. The sequence of code with be in the general form 218 /// 219 /// addi R0, SP, \#frameSize ; get the address of the previous frame 220 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size 221 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation 222 /// 223 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II, 224 int SPAdj, RegScavenger *RS) const { 225 // Get the instruction. 226 MachineInstr &MI = *II; 227 // Get the instruction's basic block. 228 MachineBasicBlock &MBB = *MI.getParent(); 229 // Get the basic block's function. 230 MachineFunction &MF = *MBB.getParent(); 231 // Get the frame info. 232 MachineFrameInfo *MFI = MF.getFrameInfo(); 233 // Determine whether 64-bit pointers are used. 234 bool LP64 = Subtarget.isPPC64(); 235 DebugLoc dl = MI.getDebugLoc(); 236 237 // Get the maximum call stack size. 238 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 239 // Get the total frame size. 240 unsigned FrameSize = MFI->getStackSize(); 241 242 // Get stack alignments. 243 unsigned TargetAlign = MF.getTarget().getFrameLowering()->getStackAlignment(); 244 unsigned MaxAlign = MFI->getMaxAlignment(); 245 if (MaxAlign > TargetAlign) 246 report_fatal_error("Dynamic alloca with large aligns not supported"); 247 248 // Determine the previous frame's address. If FrameSize can't be 249 // represented as 16 bits or we need special alignment, then we load the 250 // previous frame's address from 0(SP). Why not do an addis of the hi? 251 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. 252 // Constructing the constant and adding would take 3 instructions. 253 // Fortunately, a frame greater than 32K is rare. 254 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 255 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 256 const TargetRegisterClass *RC = LP64 ? G8RC : GPRC; 257 258 unsigned Reg = findScratchRegister(II, RS, RC, SPAdj); 259 260 if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) { 261 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) 262 .addReg(PPC::R31) 263 .addImm(FrameSize); 264 } else if (LP64) { 265 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg) 266 .addImm(0) 267 .addReg(PPC::X1); 268 } else { 269 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) 270 .addImm(0) 271 .addReg(PPC::R1); 272 } 273 274 // Grow the stack and update the stack pointer link, then determine the 275 // address of new allocated space. 276 if (LP64) { 277 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1) 278 .addReg(Reg, RegState::Kill) 279 .addReg(PPC::X1) 280 .addReg(MI.getOperand(1).getReg()); 281 if (!MI.getOperand(1).isKill()) 282 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 283 .addReg(PPC::X1) 284 .addImm(maxCallFrameSize); 285 else 286 // Implicitly kill the register. 287 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 288 .addReg(PPC::X1) 289 .addImm(maxCallFrameSize) 290 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill); 291 } else { 292 BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1) 293 .addReg(Reg, RegState::Kill) 294 .addReg(PPC::R1) 295 .addReg(MI.getOperand(1).getReg()); 296 297 if (!MI.getOperand(1).isKill()) 298 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 299 .addReg(PPC::R1) 300 .addImm(maxCallFrameSize); 301 else 302 // Implicitly kill the register. 303 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 304 .addReg(PPC::R1) 305 .addImm(maxCallFrameSize) 306 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill); 307 } 308 309 // Discard the DYNALLOC instruction. 310 MBB.erase(II); 311 } 312 313 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of 314 /// reserving a whole register (R0), we scrounge for one here. This generates 315 /// code like this: 316 /// 317 /// mfcr rA ; Move the conditional register into GPR rA. 318 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot. 319 /// stw rA, FI ; Store rA to the frame. 320 /// 321 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, 322 unsigned FrameIndex, int SPAdj, 323 RegScavenger *RS) const { 324 // Get the instruction. 325 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset> 326 // Get the instruction's basic block. 327 MachineBasicBlock &MBB = *MI.getParent(); 328 DebugLoc dl = MI.getDebugLoc(); 329 330 // FIXME: Once LLVM supports creating virtual registers here, or the register 331 // scavenger can return multiple registers, stop using reserved registers 332 // here. 333 (void) SPAdj; 334 (void) RS; 335 336 bool LP64 = Subtarget.isPPC64(); 337 unsigned Reg = Subtarget.isDarwinABI() ? (LP64 ? PPC::X2 : PPC::R2) : 338 (LP64 ? PPC::X0 : PPC::R0); 339 unsigned SrcReg = MI.getOperand(0).getReg(); 340 341 // We need to store the CR in the low 4-bits of the saved value. First, issue 342 // an MFCRpsued to save all of the CRBits and, if needed, kill the SrcReg. 343 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFCR8pseud : PPC::MFCRpseud), Reg) 344 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 345 346 // If the saved register wasn't CR0, shift the bits left so that they are in 347 // CR0's slot. 348 if (SrcReg != PPC::CR0) 349 // rlwinm rA, rA, ShiftBits, 0, 31. 350 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 351 .addReg(Reg, RegState::Kill) 352 .addImm(getPPCRegisterNumbering(SrcReg) * 4) 353 .addImm(0) 354 .addImm(31); 355 356 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW)) 357 .addReg(Reg, getKillRegState(MI.getOperand(1).getImm())), 358 FrameIndex); 359 360 // Discard the pseudo instruction. 361 MBB.erase(II); 362 } 363 364 void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II, 365 unsigned FrameIndex, int SPAdj, 366 RegScavenger *RS) const { 367 // Get the instruction. 368 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset> 369 // Get the instruction's basic block. 370 MachineBasicBlock &MBB = *MI.getParent(); 371 DebugLoc dl = MI.getDebugLoc(); 372 373 // FIXME: Once LLVM supports creating virtual registers here, or the register 374 // scavenger can return multiple registers, stop using reserved registers 375 // here. 376 (void) SPAdj; 377 (void) RS; 378 379 bool LP64 = Subtarget.isPPC64(); 380 unsigned Reg = Subtarget.isDarwinABI() ? (LP64 ? PPC::X2 : PPC::R2) : 381 (LP64 ? PPC::X0 : PPC::R0); 382 unsigned DestReg = MI.getOperand(0).getReg(); 383 assert(MI.definesRegister(DestReg) && 384 "RESTORE_CR does not define its destination"); 385 386 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), 387 Reg), FrameIndex); 388 389 // If the reloaded register isn't CR0, shift the bits right so that they are 390 // in the right CR's slot. 391 if (DestReg != PPC::CR0) { 392 unsigned ShiftBits = getPPCRegisterNumbering(DestReg)*4; 393 // rlwinm r11, r11, 32-ShiftBits, 0, 31. 394 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 395 .addReg(Reg).addImm(32-ShiftBits).addImm(0) 396 .addImm(31); 397 } 398 399 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTCRF8 : PPC::MTCRF), DestReg) 400 .addReg(Reg); 401 402 // Discard the pseudo instruction. 403 MBB.erase(II); 404 } 405 406 bool 407 PPCRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF, 408 unsigned Reg, int &FrameIdx) const { 409 410 // For the nonvolatile condition registers (CR2, CR3, CR4) in an SVR4 411 // ABI, return true to prevent allocating an additional frame slot. 412 // For 64-bit, the CR save area is at SP+8; the value of FrameIdx = 0 413 // is arbitrary and will be subsequently ignored. For 32-bit, we have 414 // previously created the stack slot if needed, so return its FrameIdx. 415 if (Subtarget.isSVR4ABI() && PPC::CR2 <= Reg && Reg <= PPC::CR4) { 416 if (Subtarget.isPPC64()) 417 FrameIdx = 0; 418 else { 419 const PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 420 FrameIdx = FI->getCRSpillFrameIndex(); 421 } 422 return true; 423 } 424 return false; 425 } 426 427 void 428 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 429 int SPAdj, unsigned FIOperandNum, 430 RegScavenger *RS) const { 431 assert(SPAdj == 0 && "Unexpected"); 432 433 // Get the instruction. 434 MachineInstr &MI = *II; 435 // Get the instruction's basic block. 436 MachineBasicBlock &MBB = *MI.getParent(); 437 // Get the basic block's function. 438 MachineFunction &MF = *MBB.getParent(); 439 // Get the frame info. 440 MachineFrameInfo *MFI = MF.getFrameInfo(); 441 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 442 DebugLoc dl = MI.getDebugLoc(); 443 444 // Take into account whether it's an add or mem instruction 445 unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2; 446 if (MI.isInlineAsm()) 447 OffsetOperandNo = FIOperandNum-1; 448 449 // Get the frame index. 450 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 451 452 // Get the frame pointer save index. Users of this index are primarily 453 // DYNALLOC instructions. 454 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 455 int FPSI = FI->getFramePointerSaveIndex(); 456 // Get the instruction opcode. 457 unsigned OpC = MI.getOpcode(); 458 459 // Special case for dynamic alloca. 460 if (FPSI && FrameIndex == FPSI && 461 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { 462 lowerDynamicAlloc(II, SPAdj, RS); 463 return; 464 } 465 466 // Special case for pseudo-ops SPILL_CR and RESTORE_CR. 467 if (OpC == PPC::SPILL_CR) { 468 lowerCRSpilling(II, FrameIndex, SPAdj, RS); 469 return; 470 } else if (OpC == PPC::RESTORE_CR) { 471 lowerCRRestore(II, FrameIndex, SPAdj, RS); 472 return; 473 } 474 475 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 476 477 bool is64Bit = Subtarget.isPPC64(); 478 MI.getOperand(FIOperandNum).ChangeToRegister(TFI->hasFP(MF) ? 479 (is64Bit ? PPC::X31 : PPC::R31) : 480 (is64Bit ? PPC::X1 : PPC::R1), 481 false); 482 483 // Figure out if the offset in the instruction is shifted right two bits. This 484 // is true for instructions like "STD", which the machine implicitly adds two 485 // low zeros to. 486 bool isIXAddr = false; 487 switch (OpC) { 488 case PPC::LWA: 489 case PPC::LD: 490 case PPC::STD: 491 case PPC::STD_32: 492 isIXAddr = true; 493 break; 494 } 495 496 // Now add the frame object offset to the offset from r1. 497 int Offset = MFI->getObjectOffset(FrameIndex); 498 if (!isIXAddr) 499 Offset += MI.getOperand(OffsetOperandNo).getImm(); 500 else 501 Offset += MI.getOperand(OffsetOperandNo).getImm() << 2; 502 503 // If we're not using a Frame Pointer that has been set to the value of the 504 // SP before having the stack size subtracted from it, then add the stack size 505 // to Offset to get the correct offset. 506 // Naked functions have stack size 0, although getStackSize may not reflect that 507 // because we didn't call all the pieces that compute it for naked functions. 508 if (!MF.getFunction()->getAttributes(). 509 hasAttribute(AttributeSet::FunctionIndex, Attribute::Naked)) 510 Offset += MFI->getStackSize(); 511 512 // If we can, encode the offset directly into the instruction. If this is a 513 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If 514 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits 515 // clear can be encoded. This is extremely uncommon, because normally you 516 // only "std" to a stack slot that is at least 4-byte aligned, but it can 517 // happen in invalid code. 518 if (OpC == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm 519 (isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0))) { 520 if (isIXAddr) 521 Offset >>= 2; // The actual encoded value has the low two bits zero. 522 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 523 return; 524 } 525 526 // The offset doesn't fit into a single register, scavenge one to build the 527 // offset in. 528 529 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 530 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 531 unsigned SReg = findScratchRegister(II, RS, is64Bit ? G8RC : GPRC, SPAdj); 532 533 // Insert a set of rA with the full offset value before the ld, st, or add 534 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SReg) 535 .addImm(Offset >> 16); 536 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg) 537 .addReg(SReg, RegState::Kill) 538 .addImm(Offset); 539 540 // Convert into indexed form of the instruction: 541 // 542 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 543 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 544 unsigned OperandBase; 545 546 if (OpC != TargetOpcode::INLINEASM) { 547 assert(ImmToIdxMap.count(OpC) && 548 "No indexed form of load or store available!"); 549 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; 550 MI.setDesc(TII.get(NewOpcode)); 551 OperandBase = 1; 552 } else { 553 OperandBase = OffsetOperandNo; 554 } 555 556 unsigned StackReg = MI.getOperand(FIOperandNum).getReg(); 557 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false); 558 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true); 559 } 560 561 unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 562 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 563 564 if (!Subtarget.isPPC64()) 565 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1; 566 else 567 return TFI->hasFP(MF) ? PPC::X31 : PPC::X1; 568 } 569 570 unsigned PPCRegisterInfo::getEHExceptionRegister() const { 571 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3; 572 } 573 574 unsigned PPCRegisterInfo::getEHHandlerRegister() const { 575 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4; 576 } 577