1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file was developed by the LLVM research group and is distributed under 6 // the University of Illinois Open Source License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the MRegisterInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #define DEBUG_TYPE "reginfo" 15 #include "PPC.h" 16 #include "PPCInstrBuilder.h" 17 #include "PPCRegisterInfo.h" 18 #include "PPCSubtarget.h" 19 #include "llvm/Constants.h" 20 #include "llvm/Type.h" 21 #include "llvm/CodeGen/ValueTypes.h" 22 #include "llvm/CodeGen/MachineInstrBuilder.h" 23 #include "llvm/CodeGen/MachineDebugInfo.h" 24 #include "llvm/CodeGen/MachineFunction.h" 25 #include "llvm/CodeGen/MachineFrameInfo.h" 26 #include "llvm/CodeGen/MachineLocation.h" 27 #include "llvm/CodeGen/SelectionDAGNodes.h" 28 #include "llvm/Target/TargetFrameInfo.h" 29 #include "llvm/Target/TargetInstrInfo.h" 30 #include "llvm/Target/TargetMachine.h" 31 #include "llvm/Target/TargetOptions.h" 32 #include "llvm/Support/CommandLine.h" 33 #include "llvm/Support/Debug.h" 34 #include "llvm/Support/MathExtras.h" 35 #include "llvm/ADT/STLExtras.h" 36 #include <cstdlib> 37 #include <iostream> 38 using namespace llvm; 39 40 /// getRegisterNumbering - Given the enum value for some register, e.g. 41 /// PPC::F14, return the number that it corresponds to (e.g. 14). 42 unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) { 43 using namespace PPC; 44 switch (RegEnum) { 45 case R0 : case X0 : case F0 : case V0 : case CR0: return 0; 46 case R1 : case X1 : case F1 : case V1 : case CR1: return 1; 47 case R2 : case X2 : case F2 : case V2 : case CR2: return 2; 48 case R3 : case X3 : case F3 : case V3 : case CR3: return 3; 49 case R4 : case X4 : case F4 : case V4 : case CR4: return 4; 50 case R5 : case X5 : case F5 : case V5 : case CR5: return 5; 51 case R6 : case X6 : case F6 : case V6 : case CR6: return 6; 52 case R7 : case X7 : case F7 : case V7 : case CR7: return 7; 53 case R8 : case X8 : case F8 : case V8 : return 8; 54 case R9 : case X9 : case F9 : case V9 : return 9; 55 case R10: case X10: case F10: case V10: return 10; 56 case R11: case X11: case F11: case V11: return 11; 57 case R12: case X12: case F12: case V12: return 12; 58 case R13: case X13: case F13: case V13: return 13; 59 case R14: case X14: case F14: case V14: return 14; 60 case R15: case X15: case F15: case V15: return 15; 61 case R16: case X16: case F16: case V16: return 16; 62 case R17: case X17: case F17: case V17: return 17; 63 case R18: case X18: case F18: case V18: return 18; 64 case R19: case X19: case F19: case V19: return 19; 65 case R20: case X20: case F20: case V20: return 20; 66 case R21: case X21: case F21: case V21: return 21; 67 case R22: case X22: case F22: case V22: return 22; 68 case R23: case X23: case F23: case V23: return 23; 69 case R24: case X24: case F24: case V24: return 24; 70 case R25: case X25: case F25: case V25: return 25; 71 case R26: case X26: case F26: case V26: return 26; 72 case R27: case X27: case F27: case V27: return 27; 73 case R28: case X28: case F28: case V28: return 28; 74 case R29: case X29: case F29: case V29: return 29; 75 case R30: case X30: case F30: case V30: return 30; 76 case R31: case X31: case F31: case V31: return 31; 77 default: 78 std::cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n"; 79 abort(); 80 } 81 } 82 83 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST, 84 const TargetInstrInfo &tii) 85 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP), 86 Subtarget(ST), TII(tii) { 87 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 88 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 89 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 90 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 91 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 92 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 93 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 94 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 95 } 96 97 void 98 PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 99 MachineBasicBlock::iterator MI, 100 unsigned SrcReg, int FrameIdx, 101 const TargetRegisterClass *RC) const { 102 if (SrcReg == PPC::LR) { 103 // FIXME: this spills LR immediately to memory in one step. To do this, we 104 // use R11, which we know cannot be used in the prolog/epilog. This is a 105 // hack. 106 BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11); 107 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx); 108 } else if (RC == PPC::CRRCRegisterClass) { 109 // FIXME: We use R0 here, because it isn't available for RA. 110 // We need to store the CR in the low 4-bits of the saved value. First, 111 // issue a MFCR to save all of the CRBits. 112 BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R0); 113 114 // If the saved register wasn't CR0, shift the bits left so that they are in 115 // CR0's slot. 116 if (SrcReg != PPC::CR0) { 117 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4; 118 // rlwinm r0, r0, ShiftBits, 0, 31. 119 BuildMI(MBB, MI, PPC::RLWINM, 4, PPC::R0) 120 .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31); 121 } 122 123 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R0), FrameIdx); 124 } else if (RC == PPC::GPRCRegisterClass) { 125 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(SrcReg),FrameIdx); 126 } else if (RC == PPC::G8RCRegisterClass) { 127 addFrameReference(BuildMI(MBB, MI, PPC::STD, 3).addReg(SrcReg),FrameIdx); 128 } else if (RC == PPC::F8RCRegisterClass) { 129 addFrameReference(BuildMI(MBB, MI, PPC::STFD, 3).addReg(SrcReg),FrameIdx); 130 } else if (RC == PPC::F4RCRegisterClass) { 131 addFrameReference(BuildMI(MBB, MI, PPC::STFS, 3).addReg(SrcReg),FrameIdx); 132 } else if (RC == PPC::VRRCRegisterClass) { 133 // We don't have indexed addressing for vector loads. Emit: 134 // R11 = ADDI FI# 135 // Dest = LVX R0, R11 136 // 137 // FIXME: We use R0 here, because it isn't available for RA. 138 addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0); 139 BuildMI(MBB, MI, PPC::STVX, 3) 140 .addReg(SrcReg).addReg(PPC::R0).addReg(PPC::R0); 141 } else { 142 assert(0 && "Unknown regclass!"); 143 abort(); 144 } 145 } 146 147 void 148 PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 149 MachineBasicBlock::iterator MI, 150 unsigned DestReg, int FrameIdx, 151 const TargetRegisterClass *RC) const { 152 if (DestReg == PPC::LR) { 153 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx); 154 BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11); 155 } else if (RC == PPC::CRRCRegisterClass) { 156 // FIXME: We use R0 here, because it isn't available for RA. 157 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R0), FrameIdx); 158 159 // If the reloaded register isn't CR0, shift the bits right so that they are 160 // in the right CR's slot. 161 if (DestReg != PPC::CR0) { 162 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4; 163 // rlwinm r11, r11, 32-ShiftBits, 0, 31. 164 BuildMI(MBB, MI, PPC::RLWINM, 4, PPC::R0) 165 .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31); 166 } 167 168 BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R0); 169 } else if (RC == PPC::GPRCRegisterClass) { 170 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, DestReg), FrameIdx); 171 } else if (RC == PPC::G8RCRegisterClass) { 172 addFrameReference(BuildMI(MBB, MI, PPC::LD, 2, DestReg), FrameIdx); 173 } else if (RC == PPC::F8RCRegisterClass) { 174 addFrameReference(BuildMI(MBB, MI, PPC::LFD, 2, DestReg), FrameIdx); 175 } else if (RC == PPC::F4RCRegisterClass) { 176 addFrameReference(BuildMI(MBB, MI, PPC::LFS, 2, DestReg), FrameIdx); 177 } else if (RC == PPC::VRRCRegisterClass) { 178 // We don't have indexed addressing for vector loads. Emit: 179 // R11 = ADDI FI# 180 // Dest = LVX R0, R11 181 // 182 // FIXME: We use R0 here, because it isn't available for RA. 183 addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0); 184 BuildMI(MBB, MI, PPC::LVX, 2, DestReg).addReg(PPC::R0).addReg(PPC::R0); 185 } else { 186 assert(0 && "Unknown regclass!"); 187 abort(); 188 } 189 } 190 191 void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, 192 MachineBasicBlock::iterator MI, 193 unsigned DestReg, unsigned SrcReg, 194 const TargetRegisterClass *RC) const { 195 if (RC == PPC::GPRCRegisterClass) { 196 BuildMI(MBB, MI, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg); 197 } else if (RC == PPC::G8RCRegisterClass) { 198 BuildMI(MBB, MI, PPC::OR8, 2, DestReg).addReg(SrcReg).addReg(SrcReg); 199 } else if (RC == PPC::F4RCRegisterClass) { 200 BuildMI(MBB, MI, PPC::FMRS, 1, DestReg).addReg(SrcReg); 201 } else if (RC == PPC::F8RCRegisterClass) { 202 BuildMI(MBB, MI, PPC::FMRD, 1, DestReg).addReg(SrcReg); 203 } else if (RC == PPC::CRRCRegisterClass) { 204 BuildMI(MBB, MI, PPC::MCRF, 1, DestReg).addReg(SrcReg); 205 } else if (RC == PPC::VRRCRegisterClass) { 206 BuildMI(MBB, MI, PPC::VOR, 2, DestReg).addReg(SrcReg).addReg(SrcReg); 207 } else { 208 std::cerr << "Attempt to copy register that is not GPR or FPR"; 209 abort(); 210 } 211 } 212 213 const unsigned* PPCRegisterInfo::getCalleeSaveRegs() const { 214 // 32-bit Darwin calling convention. 215 static const unsigned Darwin32_CalleeSaveRegs[] = { 216 PPC::R1 , PPC::R13, PPC::R14, PPC::R15, 217 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 218 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 219 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 220 PPC::R28, PPC::R29, PPC::R30, PPC::R31, 221 222 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 223 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 224 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 225 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 226 PPC::F30, PPC::F31, 227 228 PPC::CR2, PPC::CR3, PPC::CR4, 229 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 230 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 231 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 232 233 PPC::LR, 0 234 }; 235 // 64-bit Darwin calling convention. 236 static const unsigned Darwin64_CalleeSaveRegs[] = { 237 PPC::X1 , PPC::X13, PPC::X14, PPC::X15, 238 PPC::X16, PPC::X17, PPC::X18, PPC::X19, 239 PPC::X20, PPC::X21, PPC::X22, PPC::X23, 240 PPC::X24, PPC::X25, PPC::X26, PPC::X27, 241 PPC::X28, PPC::X29, PPC::X30, PPC::X31, 242 243 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 244 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 245 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 246 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 247 PPC::F30, PPC::F31, 248 249 PPC::CR2, PPC::CR3, PPC::CR4, 250 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 251 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 252 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 253 254 PPC::LR, 0 255 }; 256 257 return Subtarget.isPPC64() ? Darwin64_CalleeSaveRegs : 258 Darwin32_CalleeSaveRegs; 259 } 260 261 const TargetRegisterClass* const* 262 PPCRegisterInfo::getCalleeSaveRegClasses() const { 263 // 32-bit Darwin calling convention. 264 static const TargetRegisterClass * const Darwin32_CalleeSaveRegClasses[] = { 265 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 266 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 267 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 268 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 269 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 270 271 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 272 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 273 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 274 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 275 &PPC::F8RCRegClass,&PPC::F8RCRegClass, 276 277 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, 278 279 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 280 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 281 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 282 283 &PPC::GPRCRegClass, 0 284 }; 285 286 // 64-bit Darwin calling convention. 287 static const TargetRegisterClass * const Darwin64_CalleeSaveRegClasses[] = { 288 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 289 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 290 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 291 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 292 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 293 294 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 295 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 296 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 297 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 298 &PPC::F8RCRegClass,&PPC::F8RCRegClass, 299 300 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, 301 302 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 303 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 304 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 305 306 &PPC::GPRCRegClass, 0 307 }; 308 309 return Subtarget.isPPC64() ? Darwin64_CalleeSaveRegClasses : 310 Darwin32_CalleeSaveRegClasses; 311 } 312 313 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into 314 /// copy instructions, turning them into load/store instructions. 315 MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI, 316 unsigned OpNum, 317 int FrameIndex) const { 318 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because 319 // it takes more than one instruction to store it. 320 unsigned Opc = MI->getOpcode(); 321 322 if ((Opc == PPC::OR && 323 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { 324 if (OpNum == 0) { // move -> store 325 unsigned InReg = MI->getOperand(1).getReg(); 326 return addFrameReference(BuildMI(TII, PPC::STW, 327 3).addReg(InReg), FrameIndex); 328 } else { // move -> load 329 unsigned OutReg = MI->getOperand(0).getReg(); 330 return addFrameReference(BuildMI(TII, PPC::LWZ, 2, OutReg), FrameIndex); 331 } 332 } else if ((Opc == PPC::OR8 && 333 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { 334 if (OpNum == 0) { // move -> store 335 unsigned InReg = MI->getOperand(1).getReg(); 336 return addFrameReference(BuildMI(TII, PPC::STD, 337 3).addReg(InReg), FrameIndex); 338 } else { // move -> load 339 unsigned OutReg = MI->getOperand(0).getReg(); 340 return addFrameReference(BuildMI(TII, PPC::LD, 2, OutReg), FrameIndex); 341 } 342 } else if (Opc == PPC::FMRD) { 343 if (OpNum == 0) { // move -> store 344 unsigned InReg = MI->getOperand(1).getReg(); 345 return addFrameReference(BuildMI(TII, PPC::STFD, 346 3).addReg(InReg), FrameIndex); 347 } else { // move -> load 348 unsigned OutReg = MI->getOperand(0).getReg(); 349 return addFrameReference(BuildMI(TII, PPC::LFD, 2, OutReg), FrameIndex); 350 } 351 } else if (Opc == PPC::FMRS) { 352 if (OpNum == 0) { // move -> store 353 unsigned InReg = MI->getOperand(1).getReg(); 354 return addFrameReference(BuildMI(TII, PPC::STFS, 355 3).addReg(InReg), FrameIndex); 356 } else { // move -> load 357 unsigned OutReg = MI->getOperand(0).getReg(); 358 return addFrameReference(BuildMI(TII, PPC::LFS, 2, OutReg), FrameIndex); 359 } 360 } 361 return 0; 362 } 363 364 //===----------------------------------------------------------------------===// 365 // Stack Frame Processing methods 366 //===----------------------------------------------------------------------===// 367 368 // hasFP - Return true if the specified function should have a dedicated frame 369 // pointer register. This is true if the function has variable sized allocas or 370 // if frame pointer elimination is disabled. 371 // 372 static bool hasFP(const MachineFunction &MF) { 373 const MachineFrameInfo *MFI = MF.getFrameInfo(); 374 375 // If frame pointers are forced, or if there are variable sized stack objects, 376 // use a frame pointer. 377 // 378 return NoFramePointerElim || MFI->hasVarSizedObjects(); 379 } 380 381 void PPCRegisterInfo:: 382 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 383 MachineBasicBlock::iterator I) const { 384 if (hasFP(MF)) { 385 // If we have a frame pointer, convert as follows: 386 // ADJCALLSTACKDOWN -> lwz r0, 0(r31) 387 // stwu, r0, -amount(r1) 388 // ADJCALLSTACKUP -> addi, r1, r1, amount 389 MachineInstr *Old = I; 390 unsigned Amount = Old->getOperand(0).getImmedValue(); 391 if (Amount != 0) { 392 // We need to keep the stack aligned properly. To do this, we round the 393 // amount of space needed for the outgoing arguments up to the next 394 // alignment boundary. 395 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 396 Amount = (Amount+Align-1)/Align*Align; 397 398 // Replace the pseudo instruction with a new instruction... 399 if (Old->getOpcode() == PPC::ADJCALLSTACKDOWN) { 400 if (!Subtarget.isPPC64()) { 401 BuildMI(MBB, I, PPC::LWZ, 2, PPC::R0).addImm(0).addReg(PPC::R31); 402 BuildMI(MBB, I, PPC::STWU, 3) 403 .addReg(PPC::R0).addImm(-Amount).addReg(PPC::R1); 404 } else { 405 BuildMI(MBB, I, PPC::LD, 2, PPC::X0).addImm(0).addReg(PPC::X31); 406 BuildMI(MBB, I, PPC::STDU, 3) 407 .addReg(PPC::X0).addImm(-Amount/4).addReg(PPC::X1); 408 } 409 } else { 410 assert(Old->getOpcode() == PPC::ADJCALLSTACKUP); 411 BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addImm(Amount); 412 } 413 } 414 } 415 MBB.erase(I); 416 } 417 418 void 419 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { 420 unsigned i = 0; 421 MachineInstr &MI = *II; 422 MachineBasicBlock &MBB = *MI.getParent(); 423 MachineFunction &MF = *MBB.getParent(); 424 425 while (!MI.getOperand(i).isFrameIndex()) { 426 ++i; 427 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 428 } 429 430 int FrameIndex = MI.getOperand(i).getFrameIndex(); 431 432 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 433 MI.getOperand(i).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1, false); 434 435 // Take into account whether it's an add or mem instruction 436 unsigned OffIdx = (i == 2) ? 1 : 2; 437 438 // Figure out if the offset in the instruction is shifted right two bits. This 439 // is true for instructions like "STD", which the machine implicitly adds two 440 // low zeros to. 441 bool isIXAddr = false; 442 switch (MI.getOpcode()) { 443 case PPC::LWA: 444 case PPC::LD: 445 case PPC::STD: 446 case PPC::STD_32: 447 isIXAddr = true; 448 break; 449 } 450 451 452 // Now add the frame object offset to the offset from r1. 453 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex); 454 455 if (!isIXAddr) 456 Offset += MI.getOperand(OffIdx).getImmedValue(); 457 else 458 Offset += MI.getOperand(OffIdx).getImmedValue() << 2; 459 460 // If we're not using a Frame Pointer that has been set to the value of the 461 // SP before having the stack size subtracted from it, then add the stack size 462 // to Offset to get the correct offset. 463 Offset += MF.getFrameInfo()->getStackSize(); 464 465 if (Offset > 32767 || Offset < -32768) { 466 // Insert a set of r0 with the full offset value before the ld, st, or add 467 MachineBasicBlock *MBB = MI.getParent(); 468 BuildMI(*MBB, II, PPC::LIS, 1, PPC::R0).addImm(Offset >> 16); 469 BuildMI(*MBB, II, PPC::ORI, 2, PPC::R0).addReg(PPC::R0).addImm(Offset); 470 471 // convert into indexed form of the instruction 472 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 473 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 474 assert(ImmToIdxMap.count(MI.getOpcode()) && 475 "No indexed form of load or store available!"); 476 unsigned NewOpcode = ImmToIdxMap.find(MI.getOpcode())->second; 477 MI.setOpcode(NewOpcode); 478 MI.getOperand(1).ChangeToRegister(MI.getOperand(i).getReg(), false); 479 MI.getOperand(2).ChangeToRegister(PPC::R0, false); 480 } else { 481 if (isIXAddr) { 482 assert((Offset & 3) == 0 && "Invalid frame offset!"); 483 Offset >>= 2; // The actual encoded value has the low two bits zero. 484 } 485 MI.getOperand(OffIdx).ChangeToImmediate(Offset); 486 } 487 } 488 489 /// VRRegNo - Map from a numbered VR register to its enum value. 490 /// 491 static const unsigned short VRRegNo[] = { 492 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 , 493 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, 494 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, 495 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31 496 }; 497 498 /// RemoveVRSaveCode - We have found that this function does not need any code 499 /// to manipulate the VRSAVE register, even though it uses vector registers. 500 /// This can happen when the only registers used are known to be live in or out 501 /// of the function. Remove all of the VRSAVE related code from the function. 502 static void RemoveVRSaveCode(MachineInstr *MI) { 503 MachineBasicBlock *Entry = MI->getParent(); 504 MachineFunction *MF = Entry->getParent(); 505 506 // We know that the MTVRSAVE instruction immediately follows MI. Remove it. 507 MachineBasicBlock::iterator MBBI = MI; 508 ++MBBI; 509 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE); 510 MBBI->eraseFromParent(); 511 512 bool RemovedAllMTVRSAVEs = true; 513 // See if we can find and remove the MTVRSAVE instruction from all of the 514 // epilog blocks. 515 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); 516 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) { 517 // If last instruction is a return instruction, add an epilogue 518 if (!I->empty() && TII.isReturn(I->back().getOpcode())) { 519 bool FoundIt = false; 520 for (MBBI = I->end(); MBBI != I->begin(); ) { 521 --MBBI; 522 if (MBBI->getOpcode() == PPC::MTVRSAVE) { 523 MBBI->eraseFromParent(); // remove it. 524 FoundIt = true; 525 break; 526 } 527 } 528 RemovedAllMTVRSAVEs &= FoundIt; 529 } 530 } 531 532 // If we found and removed all MTVRSAVE instructions, remove the read of 533 // VRSAVE as well. 534 if (RemovedAllMTVRSAVEs) { 535 MBBI = MI; 536 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?"); 537 --MBBI; 538 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?"); 539 MBBI->eraseFromParent(); 540 } 541 542 // Finally, nuke the UPDATE_VRSAVE. 543 MI->eraseFromParent(); 544 } 545 546 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the 547 // instruction selector. Based on the vector registers that have been used, 548 // transform this into the appropriate ORI instruction. 549 static void HandleVRSaveUpdate(MachineInstr *MI, const bool *UsedRegs) { 550 unsigned UsedRegMask = 0; 551 for (unsigned i = 0; i != 32; ++i) 552 if (UsedRegs[VRRegNo[i]]) 553 UsedRegMask |= 1 << (31-i); 554 555 // Live in and live out values already must be in the mask, so don't bother 556 // marking them. 557 MachineFunction *MF = MI->getParent()->getParent(); 558 for (MachineFunction::livein_iterator I = 559 MF->livein_begin(), E = MF->livein_end(); I != E; ++I) { 560 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first); 561 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg. 562 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 563 } 564 for (MachineFunction::liveout_iterator I = 565 MF->liveout_begin(), E = MF->liveout_end(); I != E; ++I) { 566 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I); 567 if (VRRegNo[RegNo] == *I) // If this really is a vector reg. 568 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 569 } 570 571 unsigned SrcReg = MI->getOperand(1).getReg(); 572 unsigned DstReg = MI->getOperand(0).getReg(); 573 // If no registers are used, turn this into a copy. 574 if (UsedRegMask == 0) { 575 // Remove all VRSAVE code. 576 RemoveVRSaveCode(MI); 577 return; 578 } else if ((UsedRegMask & 0xFFFF) == UsedRegMask) { 579 BuildMI(*MI->getParent(), MI, PPC::ORI, 2, DstReg) 580 .addReg(SrcReg).addImm(UsedRegMask); 581 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { 582 BuildMI(*MI->getParent(), MI, PPC::ORIS, 2, DstReg) 583 .addReg(SrcReg).addImm(UsedRegMask >> 16); 584 } else { 585 BuildMI(*MI->getParent(), MI, PPC::ORIS, 2, DstReg) 586 .addReg(SrcReg).addImm(UsedRegMask >> 16); 587 BuildMI(*MI->getParent(), MI, PPC::ORI, 2, DstReg) 588 .addReg(DstReg).addImm(UsedRegMask & 0xFFFF); 589 } 590 591 // Remove the old UPDATE_VRSAVE instruction. 592 MI->eraseFromParent(); 593 } 594 595 596 void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const { 597 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB 598 MachineBasicBlock::iterator MBBI = MBB.begin(); 599 MachineFrameInfo *MFI = MF.getFrameInfo(); 600 MachineDebugInfo *DebugInfo = MFI->getMachineDebugInfo(); 601 602 // Do we have a frame pointer for this function? 603 bool HasFP = hasFP(MF); 604 605 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it, 606 // process it. 607 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { 608 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) { 609 HandleVRSaveUpdate(MBBI, MF.getUsedPhysregs()); 610 break; 611 } 612 } 613 614 // Move MBBI back to the beginning of the function. 615 MBBI = MBB.begin(); 616 617 // Get the number of bytes to allocate from the FrameInfo 618 unsigned NumBytes = MFI->getStackSize(); 619 620 // Get the alignments provided by the target, and the maximum alignment 621 // (if any) of the fixed frame objects. 622 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 623 unsigned MaxAlign = MFI->getMaxAlignment(); 624 625 // If we have calls, we cannot use the red zone to store callee save registers 626 // and we must set up a stack frame, so calculate the necessary size here. 627 if (MFI->hasCalls()) { 628 // We reserve argument space for call sites in the function immediately on 629 // entry to the current function. This eliminates the need for add/sub 630 // brackets around call sites. 631 NumBytes += MFI->getMaxCallFrameSize(); 632 } 633 634 // If we are a leaf function, and use up to 224 bytes of stack space, 635 // and don't have a frame pointer, then we do not need to adjust the stack 636 // pointer (we fit in the Red Zone). 637 if ((NumBytes == 0) || (NumBytes <= 224 && !HasFP && !MFI->hasCalls() && 638 MaxAlign <= TargetAlign)) { 639 MFI->setStackSize(0); 640 return; 641 } 642 643 // Add the size of R1 to NumBytes size for the store of R1 to the bottom 644 // of the stack and round the size to a multiple of the alignment. 645 unsigned Align = std::max(TargetAlign, MaxAlign); 646 unsigned GPRSize = Subtarget.isPPC64() ? 8 : 4; 647 unsigned Size = HasFP ? GPRSize + GPRSize : GPRSize; 648 NumBytes = (NumBytes+Size+Align-1)/Align*Align; 649 650 // Update frame info to pretend that this is part of the stack... 651 MFI->setStackSize(NumBytes); 652 int NegNumbytes = -NumBytes; 653 654 // Adjust stack pointer: r1 -= numbytes. 655 // If there is a preferred stack alignment, align R1 now 656 if (!Subtarget.isPPC64()) { 657 // PPC32. 658 if (MaxAlign > TargetAlign) { 659 assert(isPowerOf2_32(MaxAlign) && MaxAlign < 32767&&"Invalid alignment!"); 660 assert(isInt16(0-NumBytes) && "Unhandled stack size and alignment!"); 661 BuildMI(MBB, MBBI, PPC::RLWINM, 4, PPC::R0) 662 .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31); 663 BuildMI(MBB, MBBI, PPC::SUBFIC,2,PPC::R0).addReg(PPC::R0) 664 .addImm(0-NumBytes); 665 BuildMI(MBB, MBBI, PPC::STWUX, 3) 666 .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0); 667 } else if (NumBytes <= 32768) { 668 BuildMI(MBB, MBBI, PPC::STWU, 3).addReg(PPC::R1).addImm(NegNumbytes) 669 .addReg(PPC::R1); 670 } else { 671 BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addImm(NegNumbytes >> 16); 672 BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0).addReg(PPC::R0) 673 .addImm(NegNumbytes & 0xFFFF); 674 BuildMI(MBB, MBBI, PPC::STWUX, 3).addReg(PPC::R1).addReg(PPC::R1) 675 .addReg(PPC::R0); 676 } 677 } else { // PPC64. 678 if (MaxAlign > TargetAlign) { 679 assert(isPowerOf2_32(MaxAlign) && MaxAlign < 32767&&"Invalid alignment!"); 680 assert(isInt16(0-NumBytes) && "Unhandled stack size and alignment!"); 681 BuildMI(MBB, MBBI, PPC::RLDICL, 3, PPC::X0) 682 .addReg(PPC::X1).addImm(0).addImm(64-Log2_32(MaxAlign)); 683 BuildMI(MBB, MBBI, PPC::SUBFIC8, 2, PPC::X0).addReg(PPC::X0) 684 .addImm(0-NumBytes); 685 BuildMI(MBB, MBBI, PPC::STDUX, 3) 686 .addReg(PPC::X1).addReg(PPC::X1).addReg(PPC::X0); 687 } else if (NumBytes <= 32768*4) { 688 BuildMI(MBB, MBBI, PPC::STDU, 3).addReg(PPC::X1).addImm(NegNumbytes/4) 689 .addReg(PPC::X1); 690 } else { 691 BuildMI(MBB, MBBI, PPC::LIS8, 1, PPC::X0).addImm(NegNumbytes >> 16); 692 BuildMI(MBB, MBBI, PPC::ORI8, 2, PPC::X0).addReg(PPC::X0) 693 .addImm(NegNumbytes & 0xFFFF); 694 BuildMI(MBB, MBBI, PPC::STDUX, 3).addReg(PPC::X1).addReg(PPC::X1) 695 .addReg(PPC::X0); 696 } 697 } 698 699 if (DebugInfo && DebugInfo->hasInfo()) { 700 std::vector<MachineMove *> &Moves = DebugInfo->getFrameMoves(); 701 unsigned LabelID = DebugInfo->NextLabelID(); 702 703 // Mark effective beginning of when frame pointer becomes valid. 704 BuildMI(MBB, MBBI, PPC::DWARF_LABEL, 1).addImm(LabelID); 705 706 // Show update of SP. 707 MachineLocation SPDst(MachineLocation::VirtualFP); 708 MachineLocation SPSrc(MachineLocation::VirtualFP, NegNumbytes); 709 Moves.push_back(new MachineMove(LabelID, SPDst, SPSrc)); 710 711 // Add callee saved registers to move list. 712 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 713 for (unsigned I = 0, E = CSI.size(); I != E; ++I) { 714 MachineLocation CSDst(MachineLocation::VirtualFP, 715 MFI->getObjectOffset(CSI[I].getFrameIdx())); 716 MachineLocation CSSrc(CSI[I].getReg()); 717 Moves.push_back(new MachineMove(LabelID, CSDst, CSSrc)); 718 } 719 } 720 721 // If there is a frame pointer, copy R1 (SP) into R31 (FP) 722 if (HasFP) { 723 if (!Subtarget.isPPC64()) { 724 BuildMI(MBB, MBBI, PPC::STW, 3) 725 .addReg(PPC::R31).addImm(GPRSize).addReg(PPC::R1); 726 BuildMI(MBB, MBBI, PPC::OR, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1); 727 } else { 728 BuildMI(MBB, MBBI, PPC::STD, 3) 729 .addReg(PPC::X31).addImm(GPRSize/4).addReg(PPC::X1); 730 BuildMI(MBB, MBBI, PPC::OR8, 2, PPC::X31).addReg(PPC::X1).addReg(PPC::X1); 731 } 732 } 733 } 734 735 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF, 736 MachineBasicBlock &MBB) const { 737 MachineBasicBlock::iterator MBBI = prior(MBB.end()); 738 assert(MBBI->getOpcode() == PPC::BLR && 739 "Can only insert epilog into returning blocks"); 740 741 // Get alignment info so we know how to restore r1 742 const MachineFrameInfo *MFI = MF.getFrameInfo(); 743 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 744 745 // Get the number of bytes allocated from the FrameInfo. 746 unsigned NumBytes = MFI->getStackSize(); 747 unsigned GPRSize = 4; 748 749 if (NumBytes != 0) { 750 // If this function has a frame pointer, load the saved stack pointer from 751 // its stack slot. 752 if (hasFP(MF)) { 753 if (!Subtarget.isPPC64()) { 754 BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R31) 755 .addImm(GPRSize).addReg(PPC::R31); 756 } else { 757 BuildMI(MBB, MBBI, PPC::LD, 2, PPC::X31) 758 .addImm(GPRSize/4).addReg(PPC::X31); 759 } 760 } 761 762 // The loaded (or persistent) stack pointer value is offset by the 'stwu' 763 // on entry to the function. Add this offset back now. 764 if (!Subtarget.isPPC64()) { 765 if (NumBytes < 32768 && TargetAlign >= MFI->getMaxAlignment()) { 766 BuildMI(MBB, MBBI, PPC::ADDI, 2, PPC::R1) 767 .addReg(PPC::R1).addImm(NumBytes); 768 } else { 769 BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R1).addImm(0).addReg(PPC::R1); 770 } 771 } else { 772 if (NumBytes < 32768 && TargetAlign >= MFI->getMaxAlignment()) { 773 BuildMI(MBB, MBBI, PPC::ADDI8, 2, PPC::X1) 774 .addReg(PPC::X1).addImm(NumBytes); 775 } else { 776 BuildMI(MBB, MBBI, PPC::LD, 2, PPC::X1).addImm(0).addReg(PPC::X1); 777 } 778 } 779 } 780 } 781 782 unsigned PPCRegisterInfo::getRARegister() const { 783 return PPC::LR; 784 } 785 786 unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const { 787 if (!Subtarget.isPPC64()) 788 return hasFP(MF) ? PPC::R31 : PPC::R1; 789 else 790 return hasFP(MF) ? PPC::X31 : PPC::X1; 791 } 792 793 void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove *> &Moves) 794 const { 795 // Initial state of the frame pointer is R1. 796 MachineLocation Dst(MachineLocation::VirtualFP); 797 MachineLocation Src(PPC::R1, 0); 798 Moves.push_back(new MachineMove(0, Dst, Src)); 799 } 800 801 #include "PPCGenRegisterInfo.inc" 802 803