1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file was developed by the LLVM research group and is distributed under 6 // the University of Illinois Open Source License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the MRegisterInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #define DEBUG_TYPE "reginfo" 15 #include "PPC.h" 16 #include "PPCInstrBuilder.h" 17 #include "PPCRegisterInfo.h" 18 #include "llvm/Constants.h" 19 #include "llvm/Type.h" 20 #include "llvm/CodeGen/ValueTypes.h" 21 #include "llvm/CodeGen/MachineInstrBuilder.h" 22 #include "llvm/CodeGen/MachineDebugInfo.h" 23 #include "llvm/CodeGen/MachineFunction.h" 24 #include "llvm/CodeGen/MachineFrameInfo.h" 25 #include "llvm/CodeGen/MachineLocation.h" 26 #include "llvm/CodeGen/SelectionDAGNodes.h" 27 #include "llvm/Target/TargetFrameInfo.h" 28 #include "llvm/Target/TargetInstrInfo.h" 29 #include "llvm/Target/TargetMachine.h" 30 #include "llvm/Target/TargetOptions.h" 31 #include "llvm/Support/CommandLine.h" 32 #include "llvm/Support/Debug.h" 33 #include "llvm/Support/MathExtras.h" 34 #include "llvm/ADT/STLExtras.h" 35 #include <cstdlib> 36 #include <iostream> 37 using namespace llvm; 38 39 /// getRegisterNumbering - Given the enum value for some register, e.g. 40 /// PPC::F14, return the number that it corresponds to (e.g. 14). 41 unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) { 42 switch (RegEnum) { 43 case PPC::R0 : case PPC::F0 : case PPC::V0 : case PPC::CR0: return 0; 44 case PPC::R1 : case PPC::F1 : case PPC::V1 : case PPC::CR1: return 1; 45 case PPC::R2 : case PPC::F2 : case PPC::V2 : case PPC::CR2: return 2; 46 case PPC::R3 : case PPC::F3 : case PPC::V3 : case PPC::CR3: return 3; 47 case PPC::R4 : case PPC::F4 : case PPC::V4 : case PPC::CR4: return 4; 48 case PPC::R5 : case PPC::F5 : case PPC::V5 : case PPC::CR5: return 5; 49 case PPC::R6 : case PPC::F6 : case PPC::V6 : case PPC::CR6: return 6; 50 case PPC::R7 : case PPC::F7 : case PPC::V7 : case PPC::CR7: return 7; 51 case PPC::R8 : case PPC::F8 : case PPC::V8 : return 8; 52 case PPC::R9 : case PPC::F9 : case PPC::V9 : return 9; 53 case PPC::R10: case PPC::F10: case PPC::V10: return 10; 54 case PPC::R11: case PPC::F11: case PPC::V11: return 11; 55 case PPC::R12: case PPC::F12: case PPC::V12: return 12; 56 case PPC::R13: case PPC::F13: case PPC::V13: return 13; 57 case PPC::R14: case PPC::F14: case PPC::V14: return 14; 58 case PPC::R15: case PPC::F15: case PPC::V15: return 15; 59 case PPC::R16: case PPC::F16: case PPC::V16: return 16; 60 case PPC::R17: case PPC::F17: case PPC::V17: return 17; 61 case PPC::R18: case PPC::F18: case PPC::V18: return 18; 62 case PPC::R19: case PPC::F19: case PPC::V19: return 19; 63 case PPC::R20: case PPC::F20: case PPC::V20: return 20; 64 case PPC::R21: case PPC::F21: case PPC::V21: return 21; 65 case PPC::R22: case PPC::F22: case PPC::V22: return 22; 66 case PPC::R23: case PPC::F23: case PPC::V23: return 23; 67 case PPC::R24: case PPC::F24: case PPC::V24: return 24; 68 case PPC::R25: case PPC::F25: case PPC::V25: return 25; 69 case PPC::R26: case PPC::F26: case PPC::V26: return 26; 70 case PPC::R27: case PPC::F27: case PPC::V27: return 27; 71 case PPC::R28: case PPC::F28: case PPC::V28: return 28; 72 case PPC::R29: case PPC::F29: case PPC::V29: return 29; 73 case PPC::R30: case PPC::F30: case PPC::V30: return 30; 74 case PPC::R31: case PPC::F31: case PPC::V31: return 31; 75 default: 76 std::cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n"; 77 abort(); 78 } 79 } 80 81 PPCRegisterInfo::PPCRegisterInfo() 82 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP) { 83 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 84 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 85 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 86 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 87 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 88 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 89 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 90 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 91 } 92 93 void 94 PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 95 MachineBasicBlock::iterator MI, 96 unsigned SrcReg, int FrameIdx, 97 const TargetRegisterClass *RC) const { 98 if (SrcReg == PPC::LR) { 99 // FIXME: this spills LR immediately to memory in one step. To do this, we 100 // use R11, which we know cannot be used in the prolog/epilog. This is a 101 // hack. 102 BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11); 103 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx); 104 } else if (RC == PPC::CRRCRegisterClass) { 105 // FIXME: We use R0 here, because it isn't available for RA. 106 // We need to store the CR in the low 4-bits of the saved value. First, 107 // issue a MFCR to save all of the CRBits. 108 BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R0); 109 110 // If the saved register wasn't CR0, shift the bits left so that they are in 111 // CR0's slot. 112 if (SrcReg != PPC::CR0) { 113 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4; 114 // rlwinm r0, r0, ShiftBits, 0, 31. 115 BuildMI(MBB, MI, PPC::RLWINM, 4, PPC::R0) 116 .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31); 117 } 118 119 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R0), FrameIdx); 120 } else if (RC == PPC::GPRCRegisterClass) { 121 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(SrcReg),FrameIdx); 122 } else if (RC == PPC::G8RCRegisterClass) { 123 addFrameReference(BuildMI(MBB, MI, PPC::STD, 3).addReg(SrcReg),FrameIdx); 124 } else if (RC == PPC::F8RCRegisterClass) { 125 addFrameReference(BuildMI(MBB, MI, PPC::STFD, 3).addReg(SrcReg),FrameIdx); 126 } else if (RC == PPC::F4RCRegisterClass) { 127 addFrameReference(BuildMI(MBB, MI, PPC::STFS, 3).addReg(SrcReg),FrameIdx); 128 } else if (RC == PPC::VRRCRegisterClass) { 129 // We don't have indexed addressing for vector loads. Emit: 130 // R11 = ADDI FI# 131 // Dest = LVX R0, R11 132 // 133 // FIXME: We use R0 here, because it isn't available for RA. 134 addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0); 135 BuildMI(MBB, MI, PPC::STVX, 3) 136 .addReg(SrcReg).addReg(PPC::R0).addReg(PPC::R0); 137 } else { 138 assert(0 && "Unknown regclass!"); 139 abort(); 140 } 141 } 142 143 void 144 PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 145 MachineBasicBlock::iterator MI, 146 unsigned DestReg, int FrameIdx, 147 const TargetRegisterClass *RC) const { 148 if (DestReg == PPC::LR) { 149 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx); 150 BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11); 151 } else if (RC == PPC::CRRCRegisterClass) { 152 // FIXME: We use R0 here, because it isn't available for RA. 153 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R0), FrameIdx); 154 155 // If the reloaded register isn't CR0, shift the bits right so that they are 156 // in the right CR's slot. 157 if (DestReg != PPC::CR0) { 158 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4; 159 // rlwinm r11, r11, 32-ShiftBits, 0, 31. 160 BuildMI(MBB, MI, PPC::RLWINM, 4, PPC::R0) 161 .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31); 162 } 163 164 BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R0); 165 } else if (RC == PPC::GPRCRegisterClass) { 166 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, DestReg), FrameIdx); 167 } else if (RC == PPC::G8RCRegisterClass) { 168 addFrameReference(BuildMI(MBB, MI, PPC::LD, 2, DestReg), FrameIdx); 169 } else if (RC == PPC::F8RCRegisterClass) { 170 addFrameReference(BuildMI(MBB, MI, PPC::LFD, 2, DestReg), FrameIdx); 171 } else if (RC == PPC::F4RCRegisterClass) { 172 addFrameReference(BuildMI(MBB, MI, PPC::LFS, 2, DestReg), FrameIdx); 173 } else if (RC == PPC::VRRCRegisterClass) { 174 // We don't have indexed addressing for vector loads. Emit: 175 // R11 = ADDI FI# 176 // Dest = LVX R0, R11 177 // 178 // FIXME: We use R0 here, because it isn't available for RA. 179 addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0); 180 BuildMI(MBB, MI, PPC::LVX, 2, DestReg).addReg(PPC::R0).addReg(PPC::R0); 181 } else { 182 assert(0 && "Unknown regclass!"); 183 abort(); 184 } 185 } 186 187 void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, 188 MachineBasicBlock::iterator MI, 189 unsigned DestReg, unsigned SrcReg, 190 const TargetRegisterClass *RC) const { 191 if (RC == PPC::GPRCRegisterClass) { 192 BuildMI(MBB, MI, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg); 193 } else if (RC == PPC::G8RCRegisterClass) { 194 BuildMI(MBB, MI, PPC::OR8, 2, DestReg).addReg(SrcReg).addReg(SrcReg); 195 } else if (RC == PPC::F4RCRegisterClass) { 196 BuildMI(MBB, MI, PPC::FMRS, 1, DestReg).addReg(SrcReg); 197 } else if (RC == PPC::F8RCRegisterClass) { 198 BuildMI(MBB, MI, PPC::FMRD, 1, DestReg).addReg(SrcReg); 199 } else if (RC == PPC::CRRCRegisterClass) { 200 BuildMI(MBB, MI, PPC::MCRF, 1, DestReg).addReg(SrcReg); 201 } else if (RC == PPC::VRRCRegisterClass) { 202 BuildMI(MBB, MI, PPC::VOR, 2, DestReg).addReg(SrcReg).addReg(SrcReg); 203 } else { 204 std::cerr << "Attempt to copy register that is not GPR or FPR"; 205 abort(); 206 } 207 } 208 209 const unsigned* PPCRegisterInfo::getCalleeSaveRegs() const { 210 static const unsigned CalleeSaveRegs[] = { 211 PPC::R1, PPC::R13, 212 PPC::R14, PPC::R15, 213 PPC::R16, PPC::R17, 214 PPC::R18, PPC::R19, 215 PPC::R20, PPC::R21, 216 PPC::R22, PPC::R23, 217 PPC::R24, PPC::R25, 218 PPC::R26, PPC::R27, 219 PPC::R28, PPC::R29, 220 PPC::R30, PPC::R31, 221 PPC::F14, PPC::F15, 222 PPC::F16, PPC::F17, 223 PPC::F18, PPC::F19, 224 PPC::F20, PPC::F21, 225 PPC::F22, PPC::F23, 226 PPC::F24, PPC::F25, 227 PPC::F26, PPC::F27, 228 PPC::F28, PPC::F29, 229 PPC::F30, PPC::F31, 230 PPC::CR2, PPC::CR3, 231 PPC::CR4, PPC::V20, 232 PPC::V21, PPC::V22, 233 PPC::V23, PPC::V24, 234 PPC::V25, PPC::V26, 235 PPC::V27, PPC::V28, 236 PPC::V29, PPC::V30, 237 PPC::V31, PPC::LR, 0 238 }; 239 return CalleeSaveRegs; 240 } 241 242 const TargetRegisterClass* const* 243 PPCRegisterInfo::getCalleeSaveRegClasses() const { 244 static const TargetRegisterClass * const CalleeSaveRegClasses[] = { 245 &PPC::GPRCRegClass, &PPC::GPRCRegClass, 246 &PPC::GPRCRegClass, &PPC::GPRCRegClass, 247 &PPC::GPRCRegClass, &PPC::GPRCRegClass, 248 &PPC::GPRCRegClass, &PPC::GPRCRegClass, 249 &PPC::GPRCRegClass, &PPC::GPRCRegClass, 250 &PPC::GPRCRegClass, &PPC::GPRCRegClass, 251 &PPC::GPRCRegClass, &PPC::GPRCRegClass, 252 &PPC::GPRCRegClass, &PPC::GPRCRegClass, 253 &PPC::GPRCRegClass, &PPC::GPRCRegClass, 254 &PPC::GPRCRegClass, &PPC::GPRCRegClass, 255 &PPC::F8RCRegClass, &PPC::F8RCRegClass, 256 &PPC::F8RCRegClass, &PPC::F8RCRegClass, 257 &PPC::F8RCRegClass, &PPC::F8RCRegClass, 258 &PPC::F8RCRegClass, &PPC::F8RCRegClass, 259 &PPC::F8RCRegClass, &PPC::F8RCRegClass, 260 &PPC::F8RCRegClass, &PPC::F8RCRegClass, 261 &PPC::F8RCRegClass, &PPC::F8RCRegClass, 262 &PPC::F8RCRegClass, &PPC::F8RCRegClass, 263 &PPC::F8RCRegClass, &PPC::F8RCRegClass, 264 &PPC::CRRCRegClass, &PPC::CRRCRegClass, 265 &PPC::CRRCRegClass, &PPC::VRRCRegClass, 266 &PPC::VRRCRegClass, &PPC::VRRCRegClass, 267 &PPC::VRRCRegClass, &PPC::VRRCRegClass, 268 &PPC::VRRCRegClass, &PPC::VRRCRegClass, 269 &PPC::VRRCRegClass, &PPC::VRRCRegClass, 270 &PPC::VRRCRegClass, &PPC::VRRCRegClass, 271 &PPC::VRRCRegClass, &PPC::GPRCRegClass, 0 272 }; 273 return CalleeSaveRegClasses; 274 } 275 276 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into 277 /// copy instructions, turning them into load/store instructions. 278 MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI, 279 unsigned OpNum, 280 int FrameIndex) const { 281 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because 282 // it takes more than one instruction to store it. 283 unsigned Opc = MI->getOpcode(); 284 285 if ((Opc == PPC::OR && 286 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { 287 if (OpNum == 0) { // move -> store 288 unsigned InReg = MI->getOperand(1).getReg(); 289 return addFrameReference(BuildMI(PPC::STW, 290 3).addReg(InReg), FrameIndex); 291 } else { // move -> load 292 unsigned OutReg = MI->getOperand(0).getReg(); 293 return addFrameReference(BuildMI(PPC::LWZ, 2, OutReg), FrameIndex); 294 } 295 } else if ((Opc == PPC::OR8 && 296 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { 297 if (OpNum == 0) { // move -> store 298 unsigned InReg = MI->getOperand(1).getReg(); 299 return addFrameReference(BuildMI(PPC::STD, 300 3).addReg(InReg), FrameIndex); 301 } else { // move -> load 302 unsigned OutReg = MI->getOperand(0).getReg(); 303 return addFrameReference(BuildMI(PPC::LD, 2, OutReg), FrameIndex); 304 } 305 } else if (Opc == PPC::FMRD) { 306 if (OpNum == 0) { // move -> store 307 unsigned InReg = MI->getOperand(1).getReg(); 308 return addFrameReference(BuildMI(PPC::STFD, 309 3).addReg(InReg), FrameIndex); 310 } else { // move -> load 311 unsigned OutReg = MI->getOperand(0).getReg(); 312 return addFrameReference(BuildMI(PPC::LFD, 2, OutReg), FrameIndex); 313 } 314 } else if (Opc == PPC::FMRS) { 315 if (OpNum == 0) { // move -> store 316 unsigned InReg = MI->getOperand(1).getReg(); 317 return addFrameReference(BuildMI(PPC::STFS, 318 3).addReg(InReg), FrameIndex); 319 } else { // move -> load 320 unsigned OutReg = MI->getOperand(0).getReg(); 321 return addFrameReference(BuildMI(PPC::LFS, 2, OutReg), FrameIndex); 322 } 323 } 324 return 0; 325 } 326 327 //===----------------------------------------------------------------------===// 328 // Stack Frame Processing methods 329 //===----------------------------------------------------------------------===// 330 331 // hasFP - Return true if the specified function should have a dedicated frame 332 // pointer register. This is true if the function has variable sized allocas or 333 // if frame pointer elimination is disabled. 334 // 335 static bool hasFP(const MachineFunction &MF) { 336 const MachineFrameInfo *MFI = MF.getFrameInfo(); 337 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 338 339 // If frame pointers are forced, or if there are variable sized stack objects, 340 // use a frame pointer. 341 // 342 return NoFramePointerElim || MFI->hasVarSizedObjects(); 343 } 344 345 void PPCRegisterInfo:: 346 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 347 MachineBasicBlock::iterator I) const { 348 if (hasFP(MF)) { 349 // If we have a frame pointer, convert as follows: 350 // ADJCALLSTACKDOWN -> addi, r1, r1, -amount 351 // ADJCALLSTACKUP -> addi, r1, r1, amount 352 MachineInstr *Old = I; 353 unsigned Amount = Old->getOperand(0).getImmedValue(); 354 if (Amount != 0) { 355 // We need to keep the stack aligned properly. To do this, we round the 356 // amount of space needed for the outgoing arguments up to the next 357 // alignment boundary. 358 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 359 Amount = (Amount+Align-1)/Align*Align; 360 361 // Replace the pseudo instruction with a new instruction... 362 if (Old->getOpcode() == PPC::ADJCALLSTACKDOWN) { 363 BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addImm(-Amount); 364 } else { 365 assert(Old->getOpcode() == PPC::ADJCALLSTACKUP); 366 BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addImm(Amount); 367 } 368 } 369 } 370 MBB.erase(I); 371 } 372 373 void 374 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { 375 unsigned i = 0; 376 MachineInstr &MI = *II; 377 MachineBasicBlock &MBB = *MI.getParent(); 378 MachineFunction &MF = *MBB.getParent(); 379 380 while (!MI.getOperand(i).isFrameIndex()) { 381 ++i; 382 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 383 } 384 385 int FrameIndex = MI.getOperand(i).getFrameIndex(); 386 387 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 388 MI.getOperand(i).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1); 389 390 // Take into account whether it's an add or mem instruction 391 unsigned OffIdx = (i == 2) ? 1 : 2; 392 393 // Figure out if the offset in the instruction is shifted right two bits. This 394 // is true for instructions like "STD", which the machine implicitly adds two 395 // low zeros to. 396 bool isIXAddr = false; 397 switch (MI.getOpcode()) { 398 case PPC::LWA: 399 case PPC::LD: 400 case PPC::STD: 401 case PPC::STD_32: 402 isIXAddr = true; 403 break; 404 } 405 406 407 // Now add the frame object offset to the offset from r1. 408 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex); 409 410 if (!isIXAddr) 411 Offset += MI.getOperand(OffIdx).getImmedValue(); 412 else 413 Offset += MI.getOperand(OffIdx).getImmedValue() << 2; 414 415 // If we're not using a Frame Pointer that has been set to the value of the 416 // SP before having the stack size subtracted from it, then add the stack size 417 // to Offset to get the correct offset. 418 Offset += MF.getFrameInfo()->getStackSize(); 419 420 if (Offset > 32767 || Offset < -32768) { 421 // Insert a set of r0 with the full offset value before the ld, st, or add 422 MachineBasicBlock *MBB = MI.getParent(); 423 BuildMI(*MBB, II, PPC::LIS, 1, PPC::R0).addImm(Offset >> 16); 424 BuildMI(*MBB, II, PPC::ORI, 2, PPC::R0).addReg(PPC::R0).addImm(Offset); 425 426 // convert into indexed form of the instruction 427 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 428 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 429 assert(ImmToIdxMap.count(MI.getOpcode()) && 430 "No indexed form of load or store available!"); 431 unsigned NewOpcode = ImmToIdxMap.find(MI.getOpcode())->second; 432 MI.setOpcode(NewOpcode); 433 MI.getOperand(1).ChangeToRegister(MI.getOperand(i).getReg()); 434 MI.getOperand(2).ChangeToRegister(PPC::R0); 435 } else { 436 if (isIXAddr) { 437 assert((Offset & 3) == 0 && "Invalid frame offset!"); 438 Offset >>= 2; // The actual encoded value has the low two bits zero. 439 } 440 MI.getOperand(OffIdx).ChangeToImmediate(Offset); 441 } 442 } 443 444 /// VRRegNo - Map from a numbered VR register to its enum value. 445 /// 446 static const unsigned short VRRegNo[] = { 447 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 , 448 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, 449 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, 450 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31 451 }; 452 453 /// RemoveVRSaveCode - We have found that this function does not need any code 454 /// to manipulate the VRSAVE register, even though it uses vector registers. 455 /// This can happen when the only registers used are known to be live in or out 456 /// of the function. Remove all of the VRSAVE related code from the function. 457 static void RemoveVRSaveCode(MachineInstr *MI) { 458 MachineBasicBlock *Entry = MI->getParent(); 459 MachineFunction *MF = Entry->getParent(); 460 461 // We know that the MTVRSAVE instruction immediately follows MI. Remove it. 462 MachineBasicBlock::iterator MBBI = MI; 463 ++MBBI; 464 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE); 465 MBBI->eraseFromParent(); 466 467 bool RemovedAllMTVRSAVEs = true; 468 // See if we can find and remove the MTVRSAVE instruction from all of the 469 // epilog blocks. 470 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); 471 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) { 472 // If last instruction is a return instruction, add an epilogue 473 if (!I->empty() && TII.isReturn(I->back().getOpcode())) { 474 bool FoundIt = false; 475 for (MBBI = I->end(); MBBI != I->begin(); ) { 476 --MBBI; 477 if (MBBI->getOpcode() == PPC::MTVRSAVE) { 478 MBBI->eraseFromParent(); // remove it. 479 FoundIt = true; 480 break; 481 } 482 } 483 RemovedAllMTVRSAVEs &= FoundIt; 484 } 485 } 486 487 // If we found and removed all MTVRSAVE instructions, remove the read of 488 // VRSAVE as well. 489 if (RemovedAllMTVRSAVEs) { 490 MBBI = MI; 491 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?"); 492 --MBBI; 493 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?"); 494 MBBI->eraseFromParent(); 495 } 496 497 // Finally, nuke the UPDATE_VRSAVE. 498 MI->eraseFromParent(); 499 } 500 501 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the 502 // instruction selector. Based on the vector registers that have been used, 503 // transform this into the appropriate ORI instruction. 504 static void HandleVRSaveUpdate(MachineInstr *MI, const bool *UsedRegs) { 505 unsigned UsedRegMask = 0; 506 for (unsigned i = 0; i != 32; ++i) 507 if (UsedRegs[VRRegNo[i]]) 508 UsedRegMask |= 1 << (31-i); 509 510 // Live in and live out values already must be in the mask, so don't bother 511 // marking them. 512 MachineFunction *MF = MI->getParent()->getParent(); 513 for (MachineFunction::livein_iterator I = 514 MF->livein_begin(), E = MF->livein_end(); I != E; ++I) { 515 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first); 516 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg. 517 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 518 } 519 for (MachineFunction::liveout_iterator I = 520 MF->liveout_begin(), E = MF->liveout_end(); I != E; ++I) { 521 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I); 522 if (VRRegNo[RegNo] == *I) // If this really is a vector reg. 523 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 524 } 525 526 unsigned SrcReg = MI->getOperand(1).getReg(); 527 unsigned DstReg = MI->getOperand(0).getReg(); 528 // If no registers are used, turn this into a copy. 529 if (UsedRegMask == 0) { 530 // Remove all VRSAVE code. 531 RemoveVRSaveCode(MI); 532 return; 533 } else if ((UsedRegMask & 0xFFFF) == UsedRegMask) { 534 BuildMI(*MI->getParent(), MI, PPC::ORI, 2, DstReg) 535 .addReg(SrcReg).addImm(UsedRegMask); 536 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { 537 BuildMI(*MI->getParent(), MI, PPC::ORIS, 2, DstReg) 538 .addReg(SrcReg).addImm(UsedRegMask >> 16); 539 } else { 540 BuildMI(*MI->getParent(), MI, PPC::ORIS, 2, DstReg) 541 .addReg(SrcReg).addImm(UsedRegMask >> 16); 542 BuildMI(*MI->getParent(), MI, PPC::ORI, 2, DstReg) 543 .addReg(DstReg).addImm(UsedRegMask & 0xFFFF); 544 } 545 546 // Remove the old UPDATE_VRSAVE instruction. 547 MI->eraseFromParent(); 548 } 549 550 551 void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const { 552 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB 553 MachineBasicBlock::iterator MBBI = MBB.begin(); 554 MachineFrameInfo *MFI = MF.getFrameInfo(); 555 MachineDebugInfo *DebugInfo = MFI->getMachineDebugInfo(); 556 557 // Do we have a frame pointer for this function? 558 bool HasFP = hasFP(MF); 559 560 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it, 561 // process it. 562 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { 563 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) { 564 HandleVRSaveUpdate(MBBI, MF.getUsedPhysregs()); 565 break; 566 } 567 } 568 569 // Move MBBI back to the beginning of the function. 570 MBBI = MBB.begin(); 571 572 // Get the number of bytes to allocate from the FrameInfo 573 unsigned NumBytes = MFI->getStackSize(); 574 575 // Get the alignments provided by the target, and the maximum alignment 576 // (if any) of the fixed frame objects. 577 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 578 unsigned MaxAlign = MFI->getMaxAlignment(); 579 580 // If we have calls, we cannot use the red zone to store callee save registers 581 // and we must set up a stack frame, so calculate the necessary size here. 582 if (MFI->hasCalls()) { 583 // We reserve argument space for call sites in the function immediately on 584 // entry to the current function. This eliminates the need for add/sub 585 // brackets around call sites. 586 NumBytes += MFI->getMaxCallFrameSize(); 587 } 588 589 // If we are a leaf function, and use up to 224 bytes of stack space, 590 // and don't have a frame pointer, then we do not need to adjust the stack 591 // pointer (we fit in the Red Zone). 592 if ((NumBytes == 0) || (NumBytes <= 224 && !HasFP && !MFI->hasCalls() && 593 MaxAlign <= TargetAlign)) { 594 MFI->setStackSize(0); 595 return; 596 } 597 598 // Add the size of R1 to NumBytes size for the store of R1 to the bottom 599 // of the stack and round the size to a multiple of the alignment. 600 unsigned Align = std::max(TargetAlign, MaxAlign); 601 unsigned GPRSize = 4; 602 unsigned Size = HasFP ? GPRSize + GPRSize : GPRSize; 603 NumBytes = (NumBytes+Size+Align-1)/Align*Align; 604 605 // Update frame info to pretend that this is part of the stack... 606 MFI->setStackSize(NumBytes); 607 int NegNumbytes = -NumBytes; 608 609 // Adjust stack pointer: r1 -= numbytes. 610 // If there is a preferred stack alignment, align R1 now 611 if (MaxAlign > TargetAlign) { 612 assert(isPowerOf2_32(MaxAlign) && MaxAlign < 32767 && "Invalid alignment!"); 613 assert(isInt16(0-NumBytes) && "Unhandled stack size and alignment!"); 614 BuildMI(MBB, MBBI, PPC::RLWINM, 4, PPC::R0) 615 .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31); 616 BuildMI(MBB, MBBI, PPC::SUBFIC,2,PPC::R0).addReg(PPC::R0) 617 .addImm(0-NumBytes); 618 BuildMI(MBB, MBBI, PPC::STWUX, 3) 619 .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0); 620 } else if (NumBytes <= 32768) { 621 BuildMI(MBB, MBBI, PPC::STWU, 3).addReg(PPC::R1).addImm(NegNumbytes) 622 .addReg(PPC::R1); 623 } else { 624 BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addImm(NegNumbytes >> 16); 625 BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0).addReg(PPC::R0) 626 .addImm(NegNumbytes & 0xFFFF); 627 BuildMI(MBB, MBBI, PPC::STWUX, 3).addReg(PPC::R1).addReg(PPC::R1) 628 .addReg(PPC::R0); 629 } 630 631 if (DebugInfo && DebugInfo->hasInfo()) { 632 std::vector<MachineMove *> &Moves = DebugInfo->getFrameMoves(); 633 unsigned LabelID = DebugInfo->NextLabelID(); 634 635 // Show update of SP. 636 MachineLocation Dst(MachineLocation::VirtualFP); 637 MachineLocation Src(MachineLocation::VirtualFP, NegNumbytes); 638 Moves.push_back(new MachineMove(LabelID, Dst, Src)); 639 640 BuildMI(MBB, MBBI, PPC::DWARF_LABEL, 1).addImm(LabelID); 641 } 642 643 // If there is a frame pointer, copy R1 (SP) into R31 (FP) 644 if (HasFP) { 645 BuildMI(MBB, MBBI, PPC::STW, 3) 646 .addReg(PPC::R31).addImm(GPRSize).addReg(PPC::R1); 647 BuildMI(MBB, MBBI, PPC::OR, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1); 648 } 649 } 650 651 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF, 652 MachineBasicBlock &MBB) const { 653 MachineBasicBlock::iterator MBBI = prior(MBB.end()); 654 assert(MBBI->getOpcode() == PPC::BLR && 655 "Can only insert epilog into returning blocks"); 656 657 // Get alignment info so we know how to restore r1 658 const MachineFrameInfo *MFI = MF.getFrameInfo(); 659 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 660 661 // Get the number of bytes allocated from the FrameInfo. 662 unsigned NumBytes = MFI->getStackSize(); 663 unsigned GPRSize = 4; 664 665 if (NumBytes != 0) { 666 // If this function has a frame pointer, load the saved stack pointer from 667 // its stack slot. 668 if (hasFP(MF)) { 669 BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R31) 670 .addImm(GPRSize).addReg(PPC::R31); 671 } 672 673 // The loaded (or persistent) stack pointer value is offseted by the 'stwu' 674 // on entry to the function. Add this offset back now. 675 if (NumBytes < 32768 && TargetAlign >= MFI->getMaxAlignment()) { 676 BuildMI(MBB, MBBI, PPC::ADDI, 2, PPC::R1) 677 .addReg(PPC::R1).addImm(NumBytes); 678 } else { 679 BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R1).addImm(0).addReg(PPC::R1); 680 } 681 } 682 } 683 684 unsigned PPCRegisterInfo::getRARegister() const { 685 return PPC::LR; 686 } 687 688 unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const { 689 return hasFP(MF) ? PPC::R31 : PPC::R1; 690 } 691 692 void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove *> &Moves) 693 const { 694 // Initial state is the frame pointer is R1. 695 MachineLocation Dst(MachineLocation::VirtualFP); 696 MachineLocation Src(PPC::R1, 0); 697 Moves.push_back(new MachineMove(0, Dst, Src)); 698 } 699 700 #include "PPCGenRegisterInfo.inc" 701 702