1 //===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the TargetRegisterInfo 11 // class. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "PPCRegisterInfo.h" 16 #include "PPC.h" 17 #include "PPCFrameLowering.h" 18 #include "PPCInstrBuilder.h" 19 #include "PPCMachineFunctionInfo.h" 20 #include "PPCSubtarget.h" 21 #include "llvm/ADT/BitVector.h" 22 #include "llvm/ADT/STLExtras.h" 23 #include "llvm/CodeGen/MachineFrameInfo.h" 24 #include "llvm/CodeGen/MachineFunction.h" 25 #include "llvm/CodeGen/MachineInstrBuilder.h" 26 #include "llvm/CodeGen/MachineModuleInfo.h" 27 #include "llvm/CodeGen/MachineRegisterInfo.h" 28 #include "llvm/CodeGen/RegisterScavenging.h" 29 #include "llvm/IR/CallingConv.h" 30 #include "llvm/IR/Constants.h" 31 #include "llvm/IR/Function.h" 32 #include "llvm/IR/Type.h" 33 #include "llvm/Support/CommandLine.h" 34 #include "llvm/Support/Debug.h" 35 #include "llvm/Support/ErrorHandling.h" 36 #include "llvm/Support/MathExtras.h" 37 #include "llvm/Support/raw_ostream.h" 38 #include "llvm/Target/TargetFrameLowering.h" 39 #include "llvm/Target/TargetInstrInfo.h" 40 #include "llvm/Target/TargetMachine.h" 41 #include "llvm/Target/TargetOptions.h" 42 #include <cstdlib> 43 44 using namespace llvm; 45 46 #define DEBUG_TYPE "reginfo" 47 48 #define GET_REGINFO_TARGET_DESC 49 #include "PPCGenRegisterInfo.inc" 50 51 static cl::opt<bool> 52 EnableBasePointer("ppc-use-base-pointer", cl::Hidden, cl::init(true), 53 cl::desc("Enable use of a base pointer for complex stack frames")); 54 55 static cl::opt<bool> 56 AlwaysBasePointer("ppc-always-use-base-pointer", cl::Hidden, cl::init(false), 57 cl::desc("Force the use of a base pointer in every function")); 58 59 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST) 60 : PPCGenRegisterInfo(ST.isPPC64() ? PPC::LR8 : PPC::LR, 61 ST.isPPC64() ? 0 : 1, 62 ST.isPPC64() ? 0 : 1), 63 Subtarget(ST) { 64 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 65 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 66 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 67 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 68 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 69 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 70 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 71 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 72 ImmToIdxMap[PPC::LWA_32] = PPC::LWAX_32; 73 74 // 64-bit 75 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8; 76 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8; 77 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8; 78 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX; 79 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; 80 } 81 82 /// getPointerRegClass - Return the register class to use to hold pointers. 83 /// This is used for addressing modes. 84 const TargetRegisterClass * 85 PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) 86 const { 87 // Note that PPCInstrInfo::FoldImmediate also directly uses this Kind value 88 // when it checks for ZERO folding. 89 if (Kind == 1) { 90 if (Subtarget.isPPC64()) 91 return &PPC::G8RC_NOX0RegClass; 92 return &PPC::GPRC_NOR0RegClass; 93 } 94 95 if (Subtarget.isPPC64()) 96 return &PPC::G8RCRegClass; 97 return &PPC::GPRCRegClass; 98 } 99 100 const MCPhysReg* 101 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 102 if (Subtarget.isDarwinABI()) 103 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ? 104 CSR_Darwin64_Altivec_SaveList : 105 CSR_Darwin64_SaveList) : 106 (Subtarget.hasAltivec() ? 107 CSR_Darwin32_Altivec_SaveList : 108 CSR_Darwin32_SaveList); 109 110 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ? 111 CSR_SVR464_Altivec_SaveList : 112 CSR_SVR464_SaveList) : 113 (Subtarget.hasAltivec() ? 114 CSR_SVR432_Altivec_SaveList : 115 CSR_SVR432_SaveList); 116 } 117 118 const uint32_t* 119 PPCRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const { 120 if (Subtarget.isDarwinABI()) 121 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ? 122 CSR_Darwin64_Altivec_RegMask : 123 CSR_Darwin64_RegMask) : 124 (Subtarget.hasAltivec() ? 125 CSR_Darwin32_Altivec_RegMask : 126 CSR_Darwin32_RegMask); 127 128 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ? 129 CSR_SVR464_Altivec_RegMask : 130 CSR_SVR464_RegMask) : 131 (Subtarget.hasAltivec() ? 132 CSR_SVR432_Altivec_RegMask : 133 CSR_SVR432_RegMask); 134 } 135 136 const uint32_t* 137 PPCRegisterInfo::getNoPreservedMask() const { 138 return CSR_NoRegs_RegMask; 139 } 140 141 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 142 BitVector Reserved(getNumRegs()); 143 const PPCFrameLowering *PPCFI = static_cast<const PPCFrameLowering *>( 144 MF.getTarget().getSubtargetImpl()->getFrameLowering()); 145 146 // The ZERO register is not really a register, but the representation of r0 147 // when used in instructions that treat r0 as the constant 0. 148 Reserved.set(PPC::ZERO); 149 Reserved.set(PPC::ZERO8); 150 151 // The FP register is also not really a register, but is the representation 152 // of the frame pointer register used by ISD::FRAMEADDR. 153 Reserved.set(PPC::FP); 154 Reserved.set(PPC::FP8); 155 156 // The BP register is also not really a register, but is the representation 157 // of the base pointer register used by setjmp. 158 Reserved.set(PPC::BP); 159 Reserved.set(PPC::BP8); 160 161 // The counter registers must be reserved so that counter-based loops can 162 // be correctly formed (and the mtctr instructions are not DCE'd). 163 Reserved.set(PPC::CTR); 164 Reserved.set(PPC::CTR8); 165 166 Reserved.set(PPC::R1); 167 Reserved.set(PPC::LR); 168 Reserved.set(PPC::LR8); 169 Reserved.set(PPC::RM); 170 171 if (!Subtarget.isDarwinABI() || !Subtarget.hasAltivec()) 172 Reserved.set(PPC::VRSAVE); 173 174 // The SVR4 ABI reserves r2 and r13 175 if (Subtarget.isSVR4ABI()) { 176 Reserved.set(PPC::R2); // System-reserved register 177 Reserved.set(PPC::R13); // Small Data Area pointer register 178 } 179 180 // On PPC64, r13 is the thread pointer. Never allocate this register. 181 if (Subtarget.isPPC64()) { 182 Reserved.set(PPC::R13); 183 184 Reserved.set(PPC::X1); 185 Reserved.set(PPC::X13); 186 187 if (PPCFI->needsFP(MF)) 188 Reserved.set(PPC::X31); 189 190 if (hasBasePointer(MF)) 191 Reserved.set(PPC::X30); 192 193 // The 64-bit SVR4 ABI reserves r2 for the TOC pointer. 194 if (Subtarget.isSVR4ABI()) { 195 Reserved.set(PPC::X2); 196 } 197 } 198 199 if (PPCFI->needsFP(MF)) 200 Reserved.set(PPC::R31); 201 202 if (hasBasePointer(MF)) { 203 if (Subtarget.isSVR4ABI() && !Subtarget.isPPC64() && 204 MF.getTarget().getRelocationModel() == Reloc::PIC_) 205 Reserved.set(PPC::R29); 206 else 207 Reserved.set(PPC::R30); 208 } 209 210 if (Subtarget.isSVR4ABI() && !Subtarget.isPPC64() && 211 MF.getTarget().getRelocationModel() == Reloc::PIC_) 212 Reserved.set(PPC::R30); 213 214 // Reserve Altivec registers when Altivec is unavailable. 215 if (!Subtarget.hasAltivec()) 216 for (TargetRegisterClass::iterator I = PPC::VRRCRegClass.begin(), 217 IE = PPC::VRRCRegClass.end(); I != IE; ++I) 218 Reserved.set(*I); 219 220 return Reserved; 221 } 222 223 unsigned 224 PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 225 MachineFunction &MF) const { 226 const TargetFrameLowering *TFI = 227 MF.getTarget().getSubtargetImpl()->getFrameLowering(); 228 const unsigned DefaultSafety = 1; 229 230 switch (RC->getID()) { 231 default: 232 return 0; 233 case PPC::G8RC_NOX0RegClassID: 234 case PPC::GPRC_NOR0RegClassID: 235 case PPC::G8RCRegClassID: 236 case PPC::GPRCRegClassID: { 237 unsigned FP = TFI->hasFP(MF) ? 1 : 0; 238 return 32 - FP - DefaultSafety; 239 } 240 case PPC::F8RCRegClassID: 241 case PPC::F4RCRegClassID: 242 case PPC::VRRCRegClassID: 243 case PPC::VFRCRegClassID: 244 case PPC::VSLRCRegClassID: 245 case PPC::VSHRCRegClassID: 246 return 32 - DefaultSafety; 247 case PPC::VSRCRegClassID: 248 case PPC::VSFRCRegClassID: 249 return 64 - DefaultSafety; 250 case PPC::CRRCRegClassID: 251 return 8 - DefaultSafety; 252 } 253 } 254 255 const TargetRegisterClass* 256 PPCRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC)const { 257 if (Subtarget.hasVSX()) { 258 // With VSX, we can inflate various sub-register classes to the full VSX 259 // register set. 260 261 if (RC == &PPC::F8RCRegClass) 262 return &PPC::VSFRCRegClass; 263 else if (RC == &PPC::VRRCRegClass) 264 return &PPC::VSRCRegClass; 265 } 266 267 return TargetRegisterInfo::getLargestLegalSuperClass(RC); 268 } 269 270 //===----------------------------------------------------------------------===// 271 // Stack Frame Processing methods 272 //===----------------------------------------------------------------------===// 273 274 /// lowerDynamicAlloc - Generate the code for allocating an object in the 275 /// current frame. The sequence of code with be in the general form 276 /// 277 /// addi R0, SP, \#frameSize ; get the address of the previous frame 278 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size 279 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation 280 /// 281 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const { 282 // Get the instruction. 283 MachineInstr &MI = *II; 284 // Get the instruction's basic block. 285 MachineBasicBlock &MBB = *MI.getParent(); 286 // Get the basic block's function. 287 MachineFunction &MF = *MBB.getParent(); 288 // Get the frame info. 289 MachineFrameInfo *MFI = MF.getFrameInfo(); 290 // Get the instruction info. 291 const TargetInstrInfo &TII = 292 *MF.getTarget().getSubtargetImpl()->getInstrInfo(); 293 // Determine whether 64-bit pointers are used. 294 bool LP64 = Subtarget.isPPC64(); 295 DebugLoc dl = MI.getDebugLoc(); 296 297 // Get the maximum call stack size. 298 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 299 // Get the total frame size. 300 unsigned FrameSize = MFI->getStackSize(); 301 302 // Get stack alignments. 303 unsigned TargetAlign = MF.getTarget() 304 .getSubtargetImpl() 305 ->getFrameLowering() 306 ->getStackAlignment(); 307 unsigned MaxAlign = MFI->getMaxAlignment(); 308 assert((maxCallFrameSize & (MaxAlign-1)) == 0 && 309 "Maximum call-frame size not sufficiently aligned"); 310 311 // Determine the previous frame's address. If FrameSize can't be 312 // represented as 16 bits or we need special alignment, then we load the 313 // previous frame's address from 0(SP). Why not do an addis of the hi? 314 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. 315 // Constructing the constant and adding would take 3 instructions. 316 // Fortunately, a frame greater than 32K is rare. 317 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 318 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 319 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 320 321 if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) { 322 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) 323 .addReg(PPC::R31) 324 .addImm(FrameSize); 325 } else if (LP64) { 326 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg) 327 .addImm(0) 328 .addReg(PPC::X1); 329 } else { 330 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) 331 .addImm(0) 332 .addReg(PPC::R1); 333 } 334 335 bool KillNegSizeReg = MI.getOperand(1).isKill(); 336 unsigned NegSizeReg = MI.getOperand(1).getReg(); 337 338 // Grow the stack and update the stack pointer link, then determine the 339 // address of new allocated space. 340 if (LP64) { 341 if (MaxAlign > TargetAlign) { 342 unsigned UnalNegSizeReg = NegSizeReg; 343 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC); 344 345 // Unfortunately, there is no andi, only andi., and we can't insert that 346 // here because we might clobber cr0 while it is live. 347 BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg) 348 .addImm(~(MaxAlign-1)); 349 350 unsigned NegSizeReg1 = NegSizeReg; 351 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC); 352 BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg) 353 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg)) 354 .addReg(NegSizeReg1, RegState::Kill); 355 KillNegSizeReg = true; 356 } 357 358 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1) 359 .addReg(Reg, RegState::Kill) 360 .addReg(PPC::X1) 361 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg)); 362 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 363 .addReg(PPC::X1) 364 .addImm(maxCallFrameSize); 365 } else { 366 if (MaxAlign > TargetAlign) { 367 unsigned UnalNegSizeReg = NegSizeReg; 368 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); 369 370 // Unfortunately, there is no andi, only andi., and we can't insert that 371 // here because we might clobber cr0 while it is live. 372 BuildMI(MBB, II, dl, TII.get(PPC::LI), NegSizeReg) 373 .addImm(~(MaxAlign-1)); 374 375 unsigned NegSizeReg1 = NegSizeReg; 376 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); 377 BuildMI(MBB, II, dl, TII.get(PPC::AND), NegSizeReg) 378 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg)) 379 .addReg(NegSizeReg1, RegState::Kill); 380 KillNegSizeReg = true; 381 } 382 383 BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1) 384 .addReg(Reg, RegState::Kill) 385 .addReg(PPC::R1) 386 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg)); 387 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 388 .addReg(PPC::R1) 389 .addImm(maxCallFrameSize); 390 } 391 392 // Discard the DYNALLOC instruction. 393 MBB.erase(II); 394 } 395 396 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of 397 /// reserving a whole register (R0), we scrounge for one here. This generates 398 /// code like this: 399 /// 400 /// mfcr rA ; Move the conditional register into GPR rA. 401 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot. 402 /// stw rA, FI ; Store rA to the frame. 403 /// 404 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, 405 unsigned FrameIndex) const { 406 // Get the instruction. 407 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset> 408 // Get the instruction's basic block. 409 MachineBasicBlock &MBB = *MI.getParent(); 410 MachineFunction &MF = *MBB.getParent(); 411 const TargetInstrInfo &TII = 412 *MF.getTarget().getSubtargetImpl()->getInstrInfo(); 413 DebugLoc dl = MI.getDebugLoc(); 414 415 bool LP64 = Subtarget.isPPC64(); 416 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 417 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 418 419 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 420 unsigned SrcReg = MI.getOperand(0).getReg(); 421 422 // We need to store the CR in the low 4-bits of the saved value. First, issue 423 // an MFOCRF to save all of the CRBits and, if needed, kill the SrcReg. 424 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg) 425 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 426 427 // If the saved register wasn't CR0, shift the bits left so that they are in 428 // CR0's slot. 429 if (SrcReg != PPC::CR0) { 430 unsigned Reg1 = Reg; 431 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 432 433 // rlwinm rA, rA, ShiftBits, 0, 31. 434 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 435 .addReg(Reg1, RegState::Kill) 436 .addImm(getEncodingValue(SrcReg) * 4) 437 .addImm(0) 438 .addImm(31); 439 } 440 441 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW)) 442 .addReg(Reg, RegState::Kill), 443 FrameIndex); 444 445 // Discard the pseudo instruction. 446 MBB.erase(II); 447 } 448 449 void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II, 450 unsigned FrameIndex) const { 451 // Get the instruction. 452 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset> 453 // Get the instruction's basic block. 454 MachineBasicBlock &MBB = *MI.getParent(); 455 MachineFunction &MF = *MBB.getParent(); 456 const TargetInstrInfo &TII = 457 *MF.getTarget().getSubtargetImpl()->getInstrInfo(); 458 DebugLoc dl = MI.getDebugLoc(); 459 460 bool LP64 = Subtarget.isPPC64(); 461 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 462 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 463 464 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 465 unsigned DestReg = MI.getOperand(0).getReg(); 466 assert(MI.definesRegister(DestReg) && 467 "RESTORE_CR does not define its destination"); 468 469 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), 470 Reg), FrameIndex); 471 472 // If the reloaded register isn't CR0, shift the bits right so that they are 473 // in the right CR's slot. 474 if (DestReg != PPC::CR0) { 475 unsigned Reg1 = Reg; 476 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 477 478 unsigned ShiftBits = getEncodingValue(DestReg)*4; 479 // rlwinm r11, r11, 32-ShiftBits, 0, 31. 480 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 481 .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0) 482 .addImm(31); 483 } 484 485 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), DestReg) 486 .addReg(Reg, RegState::Kill); 487 488 // Discard the pseudo instruction. 489 MBB.erase(II); 490 } 491 492 static unsigned getCRFromCRBit(unsigned SrcReg) { 493 unsigned Reg = 0; 494 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT || 495 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN) 496 Reg = PPC::CR0; 497 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT || 498 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN) 499 Reg = PPC::CR1; 500 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT || 501 SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN) 502 Reg = PPC::CR2; 503 else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT || 504 SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN) 505 Reg = PPC::CR3; 506 else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT || 507 SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN) 508 Reg = PPC::CR4; 509 else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT || 510 SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN) 511 Reg = PPC::CR5; 512 else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT || 513 SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN) 514 Reg = PPC::CR6; 515 else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT || 516 SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN) 517 Reg = PPC::CR7; 518 519 assert(Reg != 0 && "Invalid CR bit register"); 520 return Reg; 521 } 522 523 void PPCRegisterInfo::lowerCRBitSpilling(MachineBasicBlock::iterator II, 524 unsigned FrameIndex) const { 525 // Get the instruction. 526 MachineInstr &MI = *II; // ; SPILL_CRBIT <SrcReg>, <offset> 527 // Get the instruction's basic block. 528 MachineBasicBlock &MBB = *MI.getParent(); 529 MachineFunction &MF = *MBB.getParent(); 530 const TargetInstrInfo &TII = 531 *MF.getTarget().getSubtargetImpl()->getInstrInfo(); 532 DebugLoc dl = MI.getDebugLoc(); 533 534 bool LP64 = Subtarget.isPPC64(); 535 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 536 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 537 538 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 539 unsigned SrcReg = MI.getOperand(0).getReg(); 540 541 BuildMI(MBB, II, dl, TII.get(TargetOpcode::KILL), 542 getCRFromCRBit(SrcReg)) 543 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 544 545 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg) 546 .addReg(getCRFromCRBit(SrcReg)); 547 548 // If the saved register wasn't CR0LT, shift the bits left so that the bit to 549 // store is the first one. Mask all but that bit. 550 unsigned Reg1 = Reg; 551 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 552 553 // rlwinm rA, rA, ShiftBits, 0, 0. 554 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 555 .addReg(Reg1, RegState::Kill) 556 .addImm(getEncodingValue(SrcReg)) 557 .addImm(0).addImm(0); 558 559 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW)) 560 .addReg(Reg, RegState::Kill), 561 FrameIndex); 562 563 // Discard the pseudo instruction. 564 MBB.erase(II); 565 } 566 567 void PPCRegisterInfo::lowerCRBitRestore(MachineBasicBlock::iterator II, 568 unsigned FrameIndex) const { 569 // Get the instruction. 570 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CRBIT <offset> 571 // Get the instruction's basic block. 572 MachineBasicBlock &MBB = *MI.getParent(); 573 MachineFunction &MF = *MBB.getParent(); 574 const TargetInstrInfo &TII = 575 *MF.getTarget().getSubtargetImpl()->getInstrInfo(); 576 DebugLoc dl = MI.getDebugLoc(); 577 578 bool LP64 = Subtarget.isPPC64(); 579 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 580 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 581 582 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 583 unsigned DestReg = MI.getOperand(0).getReg(); 584 assert(MI.definesRegister(DestReg) && 585 "RESTORE_CRBIT does not define its destination"); 586 587 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), 588 Reg), FrameIndex); 589 590 BuildMI(MBB, II, dl, TII.get(TargetOpcode::IMPLICIT_DEF), DestReg); 591 592 unsigned RegO = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 593 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), RegO) 594 .addReg(getCRFromCRBit(DestReg)); 595 596 unsigned ShiftBits = getEncodingValue(DestReg); 597 // rlwimi r11, r10, 32-ShiftBits, ..., ... 598 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWIMI8 : PPC::RLWIMI), RegO) 599 .addReg(RegO, RegState::Kill).addReg(Reg, RegState::Kill) 600 .addImm(ShiftBits ? 32-ShiftBits : 0) 601 .addImm(ShiftBits).addImm(ShiftBits); 602 603 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), 604 getCRFromCRBit(DestReg)) 605 .addReg(RegO, RegState::Kill) 606 // Make sure we have a use dependency all the way through this 607 // sequence of instructions. We can't have the other bits in the CR 608 // modified in between the mfocrf and the mtocrf. 609 .addReg(getCRFromCRBit(DestReg), RegState::Implicit); 610 611 // Discard the pseudo instruction. 612 MBB.erase(II); 613 } 614 615 void PPCRegisterInfo::lowerVRSAVESpilling(MachineBasicBlock::iterator II, 616 unsigned FrameIndex) const { 617 // Get the instruction. 618 MachineInstr &MI = *II; // ; SPILL_VRSAVE <SrcReg>, <offset> 619 // Get the instruction's basic block. 620 MachineBasicBlock &MBB = *MI.getParent(); 621 MachineFunction &MF = *MBB.getParent(); 622 const TargetInstrInfo &TII = 623 *MF.getTarget().getSubtargetImpl()->getInstrInfo(); 624 DebugLoc dl = MI.getDebugLoc(); 625 626 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 627 unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC); 628 unsigned SrcReg = MI.getOperand(0).getReg(); 629 630 BuildMI(MBB, II, dl, TII.get(PPC::MFVRSAVEv), Reg) 631 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 632 633 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::STW)) 634 .addReg(Reg, RegState::Kill), 635 FrameIndex); 636 637 // Discard the pseudo instruction. 638 MBB.erase(II); 639 } 640 641 void PPCRegisterInfo::lowerVRSAVERestore(MachineBasicBlock::iterator II, 642 unsigned FrameIndex) const { 643 // Get the instruction. 644 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_VRSAVE <offset> 645 // Get the instruction's basic block. 646 MachineBasicBlock &MBB = *MI.getParent(); 647 MachineFunction &MF = *MBB.getParent(); 648 const TargetInstrInfo &TII = 649 *MF.getTarget().getSubtargetImpl()->getInstrInfo(); 650 DebugLoc dl = MI.getDebugLoc(); 651 652 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 653 unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC); 654 unsigned DestReg = MI.getOperand(0).getReg(); 655 assert(MI.definesRegister(DestReg) && 656 "RESTORE_VRSAVE does not define its destination"); 657 658 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::LWZ), 659 Reg), FrameIndex); 660 661 BuildMI(MBB, II, dl, TII.get(PPC::MTVRSAVEv), DestReg) 662 .addReg(Reg, RegState::Kill); 663 664 // Discard the pseudo instruction. 665 MBB.erase(II); 666 } 667 668 bool 669 PPCRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF, 670 unsigned Reg, int &FrameIdx) const { 671 672 // For the nonvolatile condition registers (CR2, CR3, CR4) in an SVR4 673 // ABI, return true to prevent allocating an additional frame slot. 674 // For 64-bit, the CR save area is at SP+8; the value of FrameIdx = 0 675 // is arbitrary and will be subsequently ignored. For 32-bit, we have 676 // previously created the stack slot if needed, so return its FrameIdx. 677 if (Subtarget.isSVR4ABI() && PPC::CR2 <= Reg && Reg <= PPC::CR4) { 678 if (Subtarget.isPPC64()) 679 FrameIdx = 0; 680 else { 681 const PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 682 FrameIdx = FI->getCRSpillFrameIndex(); 683 } 684 return true; 685 } 686 return false; 687 } 688 689 // Figure out if the offset in the instruction must be a multiple of 4. 690 // This is true for instructions like "STD". 691 static bool usesIXAddr(const MachineInstr &MI) { 692 unsigned OpC = MI.getOpcode(); 693 694 switch (OpC) { 695 default: 696 return false; 697 case PPC::LWA: 698 case PPC::LWA_32: 699 case PPC::LD: 700 case PPC::STD: 701 return true; 702 } 703 } 704 705 // Return the OffsetOperandNo given the FIOperandNum (and the instruction). 706 static unsigned getOffsetONFromFION(const MachineInstr &MI, 707 unsigned FIOperandNum) { 708 // Take into account whether it's an add or mem instruction 709 unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2; 710 if (MI.isInlineAsm()) 711 OffsetOperandNo = FIOperandNum-1; 712 713 return OffsetOperandNo; 714 } 715 716 void 717 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 718 int SPAdj, unsigned FIOperandNum, 719 RegScavenger *RS) const { 720 assert(SPAdj == 0 && "Unexpected"); 721 722 // Get the instruction. 723 MachineInstr &MI = *II; 724 // Get the instruction's basic block. 725 MachineBasicBlock &MBB = *MI.getParent(); 726 // Get the basic block's function. 727 MachineFunction &MF = *MBB.getParent(); 728 // Get the instruction info. 729 const TargetInstrInfo &TII = 730 *MF.getTarget().getSubtargetImpl()->getInstrInfo(); 731 // Get the frame info. 732 MachineFrameInfo *MFI = MF.getFrameInfo(); 733 DebugLoc dl = MI.getDebugLoc(); 734 735 unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum); 736 737 // Get the frame index. 738 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 739 740 // Get the frame pointer save index. Users of this index are primarily 741 // DYNALLOC instructions. 742 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 743 int FPSI = FI->getFramePointerSaveIndex(); 744 // Get the instruction opcode. 745 unsigned OpC = MI.getOpcode(); 746 747 // Special case for dynamic alloca. 748 if (FPSI && FrameIndex == FPSI && 749 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { 750 lowerDynamicAlloc(II); 751 return; 752 } 753 754 // Special case for pseudo-ops SPILL_CR and RESTORE_CR, etc. 755 if (OpC == PPC::SPILL_CR) { 756 lowerCRSpilling(II, FrameIndex); 757 return; 758 } else if (OpC == PPC::RESTORE_CR) { 759 lowerCRRestore(II, FrameIndex); 760 return; 761 } else if (OpC == PPC::SPILL_CRBIT) { 762 lowerCRBitSpilling(II, FrameIndex); 763 return; 764 } else if (OpC == PPC::RESTORE_CRBIT) { 765 lowerCRBitRestore(II, FrameIndex); 766 return; 767 } else if (OpC == PPC::SPILL_VRSAVE) { 768 lowerVRSAVESpilling(II, FrameIndex); 769 return; 770 } else if (OpC == PPC::RESTORE_VRSAVE) { 771 lowerVRSAVERestore(II, FrameIndex); 772 return; 773 } 774 775 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 776 MI.getOperand(FIOperandNum).ChangeToRegister( 777 FrameIndex < 0 ? getBaseRegister(MF) : getFrameRegister(MF), false); 778 779 // Figure out if the offset in the instruction is shifted right two bits. 780 bool isIXAddr = usesIXAddr(MI); 781 782 // If the instruction is not present in ImmToIdxMap, then it has no immediate 783 // form (and must be r+r). 784 bool noImmForm = !MI.isInlineAsm() && !ImmToIdxMap.count(OpC); 785 786 // Now add the frame object offset to the offset from r1. 787 int Offset = MFI->getObjectOffset(FrameIndex); 788 Offset += MI.getOperand(OffsetOperandNo).getImm(); 789 790 // If we're not using a Frame Pointer that has been set to the value of the 791 // SP before having the stack size subtracted from it, then add the stack size 792 // to Offset to get the correct offset. 793 // Naked functions have stack size 0, although getStackSize may not reflect that 794 // because we didn't call all the pieces that compute it for naked functions. 795 if (!MF.getFunction()->getAttributes(). 796 hasAttribute(AttributeSet::FunctionIndex, Attribute::Naked)) { 797 if (!(hasBasePointer(MF) && FrameIndex < 0)) 798 Offset += MFI->getStackSize(); 799 } 800 801 // If we can, encode the offset directly into the instruction. If this is a 802 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If 803 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits 804 // clear can be encoded. This is extremely uncommon, because normally you 805 // only "std" to a stack slot that is at least 4-byte aligned, but it can 806 // happen in invalid code. 807 assert(OpC != PPC::DBG_VALUE && 808 "This should be handle in a target independent way"); 809 if (!noImmForm && isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0)) { 810 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 811 return; 812 } 813 814 // The offset doesn't fit into a single register, scavenge one to build the 815 // offset in. 816 817 bool is64Bit = Subtarget.isPPC64(); 818 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 819 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 820 const TargetRegisterClass *RC = is64Bit ? G8RC : GPRC; 821 unsigned SRegHi = MF.getRegInfo().createVirtualRegister(RC), 822 SReg = MF.getRegInfo().createVirtualRegister(RC); 823 824 // Insert a set of rA with the full offset value before the ld, st, or add 825 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SRegHi) 826 .addImm(Offset >> 16); 827 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg) 828 .addReg(SRegHi, RegState::Kill) 829 .addImm(Offset); 830 831 // Convert into indexed form of the instruction: 832 // 833 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 834 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 835 unsigned OperandBase; 836 837 if (noImmForm) 838 OperandBase = 1; 839 else if (OpC != TargetOpcode::INLINEASM) { 840 assert(ImmToIdxMap.count(OpC) && 841 "No indexed form of load or store available!"); 842 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; 843 MI.setDesc(TII.get(NewOpcode)); 844 OperandBase = 1; 845 } else { 846 OperandBase = OffsetOperandNo; 847 } 848 849 unsigned StackReg = MI.getOperand(FIOperandNum).getReg(); 850 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false); 851 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true); 852 } 853 854 unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 855 const TargetFrameLowering *TFI = 856 MF.getTarget().getSubtargetImpl()->getFrameLowering(); 857 858 if (!Subtarget.isPPC64()) 859 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1; 860 else 861 return TFI->hasFP(MF) ? PPC::X31 : PPC::X1; 862 } 863 864 unsigned PPCRegisterInfo::getBaseRegister(const MachineFunction &MF) const { 865 if (!hasBasePointer(MF)) 866 return getFrameRegister(MF); 867 868 if (Subtarget.isPPC64()) 869 return PPC::X30; 870 871 if (Subtarget.isSVR4ABI() && 872 MF.getTarget().getRelocationModel() == Reloc::PIC_) 873 return PPC::R29; 874 875 return PPC::R30; 876 } 877 878 bool PPCRegisterInfo::hasBasePointer(const MachineFunction &MF) const { 879 if (!EnableBasePointer) 880 return false; 881 if (AlwaysBasePointer) 882 return true; 883 884 // If we need to realign the stack, then the stack pointer can no longer 885 // serve as an offset into the caller's stack space. As a result, we need a 886 // base pointer. 887 return needsStackRealignment(MF); 888 } 889 890 bool PPCRegisterInfo::canRealignStack(const MachineFunction &MF) const { 891 if (MF.getFunction()->hasFnAttribute("no-realign-stack")) 892 return false; 893 894 return true; 895 } 896 897 bool PPCRegisterInfo::needsStackRealignment(const MachineFunction &MF) const { 898 const MachineFrameInfo *MFI = MF.getFrameInfo(); 899 const Function *F = MF.getFunction(); 900 unsigned StackAlign = MF.getTarget() 901 .getSubtargetImpl() 902 ->getFrameLowering() 903 ->getStackAlignment(); 904 bool requiresRealignment = 905 ((MFI->getMaxAlignment() > StackAlign) || 906 F->getAttributes().hasAttribute(AttributeSet::FunctionIndex, 907 Attribute::StackAlignment)); 908 909 return requiresRealignment && canRealignStack(MF); 910 } 911 912 /// Returns true if the instruction's frame index 913 /// reference would be better served by a base register other than FP 914 /// or SP. Used by LocalStackFrameAllocation to determine which frame index 915 /// references it should create new base registers for. 916 bool PPCRegisterInfo:: 917 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { 918 assert(Offset < 0 && "Local offset must be negative"); 919 920 // It's the load/store FI references that cause issues, as it can be difficult 921 // to materialize the offset if it won't fit in the literal field. Estimate 922 // based on the size of the local frame and some conservative assumptions 923 // about the rest of the stack frame (note, this is pre-regalloc, so 924 // we don't know everything for certain yet) whether this offset is likely 925 // to be out of range of the immediate. Return true if so. 926 927 // We only generate virtual base registers for loads and stores that have 928 // an r+i form. Return false for everything else. 929 unsigned OpC = MI->getOpcode(); 930 if (!ImmToIdxMap.count(OpC)) 931 return false; 932 933 // Don't generate a new virtual base register just to add zero to it. 934 if ((OpC == PPC::ADDI || OpC == PPC::ADDI8) && 935 MI->getOperand(2).getImm() == 0) 936 return false; 937 938 MachineBasicBlock &MBB = *MI->getParent(); 939 MachineFunction &MF = *MBB.getParent(); 940 941 const PPCFrameLowering *PPCFI = static_cast<const PPCFrameLowering *>( 942 MF.getTarget().getSubtargetImpl()->getFrameLowering()); 943 unsigned StackEst = 944 PPCFI->determineFrameLayout(MF, false, true); 945 946 // If we likely don't need a stack frame, then we probably don't need a 947 // virtual base register either. 948 if (!StackEst) 949 return false; 950 951 // Estimate an offset from the stack pointer. 952 // The incoming offset is relating to the SP at the start of the function, 953 // but when we access the local it'll be relative to the SP after local 954 // allocation, so adjust our SP-relative offset by that allocation size. 955 Offset += StackEst; 956 957 // The frame pointer will point to the end of the stack, so estimate the 958 // offset as the difference between the object offset and the FP location. 959 return !isFrameOffsetLegal(MI, Offset); 960 } 961 962 /// Insert defining instruction(s) for BaseReg to 963 /// be a pointer to FrameIdx at the beginning of the basic block. 964 void PPCRegisterInfo:: 965 materializeFrameBaseRegister(MachineBasicBlock *MBB, 966 unsigned BaseReg, int FrameIdx, 967 int64_t Offset) const { 968 unsigned ADDriOpc = Subtarget.isPPC64() ? PPC::ADDI8 : PPC::ADDI; 969 970 MachineBasicBlock::iterator Ins = MBB->begin(); 971 DebugLoc DL; // Defaults to "unknown" 972 if (Ins != MBB->end()) 973 DL = Ins->getDebugLoc(); 974 975 const MachineFunction &MF = *MBB->getParent(); 976 const TargetInstrInfo &TII = 977 *MF.getTarget().getSubtargetImpl()->getInstrInfo(); 978 const MCInstrDesc &MCID = TII.get(ADDriOpc); 979 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 980 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); 981 982 BuildMI(*MBB, Ins, DL, MCID, BaseReg) 983 .addFrameIndex(FrameIdx).addImm(Offset); 984 } 985 986 void PPCRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, 987 int64_t Offset) const { 988 unsigned FIOperandNum = 0; 989 while (!MI.getOperand(FIOperandNum).isFI()) { 990 ++FIOperandNum; 991 assert(FIOperandNum < MI.getNumOperands() && 992 "Instr doesn't have FrameIndex operand!"); 993 } 994 995 MI.getOperand(FIOperandNum).ChangeToRegister(BaseReg, false); 996 unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum); 997 Offset += MI.getOperand(OffsetOperandNo).getImm(); 998 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 999 1000 MachineBasicBlock &MBB = *MI.getParent(); 1001 MachineFunction &MF = *MBB.getParent(); 1002 const TargetInstrInfo &TII = 1003 *MF.getTarget().getSubtargetImpl()->getInstrInfo(); 1004 const MCInstrDesc &MCID = MI.getDesc(); 1005 MachineRegisterInfo &MRI = MF.getRegInfo(); 1006 MRI.constrainRegClass(BaseReg, 1007 TII.getRegClass(MCID, FIOperandNum, this, MF)); 1008 } 1009 1010 bool PPCRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, 1011 int64_t Offset) const { 1012 unsigned FIOperandNum = 0; 1013 while (!MI->getOperand(FIOperandNum).isFI()) { 1014 ++FIOperandNum; 1015 assert(FIOperandNum < MI->getNumOperands() && 1016 "Instr doesn't have FrameIndex operand!"); 1017 } 1018 1019 unsigned OffsetOperandNo = getOffsetONFromFION(*MI, FIOperandNum); 1020 Offset += MI->getOperand(OffsetOperandNo).getImm(); 1021 1022 return MI->getOpcode() == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm 1023 (isInt<16>(Offset) && (!usesIXAddr(*MI) || (Offset & 3) == 0)); 1024 } 1025 1026