1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the TargetRegisterInfo 11 // class. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #define DEBUG_TYPE "reginfo" 16 #include "PPC.h" 17 #include "PPCInstrBuilder.h" 18 #include "PPCMachineFunctionInfo.h" 19 #include "PPCRegisterInfo.h" 20 #include "PPCFrameInfo.h" 21 #include "PPCSubtarget.h" 22 #include "llvm/CallingConv.h" 23 #include "llvm/Constants.h" 24 #include "llvm/Function.h" 25 #include "llvm/Type.h" 26 #include "llvm/CodeGen/ValueTypes.h" 27 #include "llvm/CodeGen/MachineInstrBuilder.h" 28 #include "llvm/CodeGen/MachineModuleInfo.h" 29 #include "llvm/CodeGen/MachineFunction.h" 30 #include "llvm/CodeGen/MachineFrameInfo.h" 31 #include "llvm/CodeGen/MachineLocation.h" 32 #include "llvm/CodeGen/MachineRegisterInfo.h" 33 #include "llvm/CodeGen/RegisterScavenging.h" 34 #include "llvm/Target/TargetFrameInfo.h" 35 #include "llvm/Target/TargetInstrInfo.h" 36 #include "llvm/Target/TargetMachine.h" 37 #include "llvm/Target/TargetOptions.h" 38 #include "llvm/Support/CommandLine.h" 39 #include "llvm/Support/Debug.h" 40 #include "llvm/Support/ErrorHandling.h" 41 #include "llvm/Support/MathExtras.h" 42 #include "llvm/Support/raw_ostream.h" 43 #include "llvm/ADT/BitVector.h" 44 #include "llvm/ADT/STLExtras.h" 45 #include <cstdlib> 46 47 // FIXME This disables some code that aligns the stack to a boundary 48 // bigger than the default (16 bytes on Darwin) when there is a stack local 49 // of greater alignment. This does not currently work, because the delta 50 // between old and new stack pointers is added to offsets that reference 51 // incoming parameters after the prolog is generated, and the code that 52 // does that doesn't handle a variable delta. You don't want to do that 53 // anyway; a better approach is to reserve another register that retains 54 // to the incoming stack pointer, and reference parameters relative to that. 55 #define ALIGN_STACK 0 56 57 // FIXME (64-bit): Eventually enable by default. 58 namespace llvm { 59 cl::opt<bool> EnablePPC32RS("enable-ppc32-regscavenger", 60 cl::init(false), 61 cl::desc("Enable PPC32 register scavenger"), 62 cl::Hidden); 63 cl::opt<bool> EnablePPC64RS("enable-ppc64-regscavenger", 64 cl::init(false), 65 cl::desc("Enable PPC64 register scavenger"), 66 cl::Hidden); 67 } 68 69 using namespace llvm; 70 71 #define EnableRegisterScavenging \ 72 ((EnablePPC32RS && !Subtarget.isPPC64()) || \ 73 (EnablePPC64RS && Subtarget.isPPC64())) 74 75 // FIXME (64-bit): Should be inlined. 76 bool 77 PPCRegisterInfo::requiresRegisterScavenging(const MachineFunction &) const { 78 return EnableRegisterScavenging; 79 } 80 81 /// getRegisterNumbering - Given the enum value for some register, e.g. 82 /// PPC::F14, return the number that it corresponds to (e.g. 14). 83 unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) { 84 using namespace PPC; 85 switch (RegEnum) { 86 case 0: return 0; 87 case R0 : case X0 : case F0 : case V0 : case CR0: case CR0LT: return 0; 88 case R1 : case X1 : case F1 : case V1 : case CR1: case CR0GT: return 1; 89 case R2 : case X2 : case F2 : case V2 : case CR2: case CR0EQ: return 2; 90 case R3 : case X3 : case F3 : case V3 : case CR3: case CR0UN: return 3; 91 case R4 : case X4 : case F4 : case V4 : case CR4: case CR1LT: return 4; 92 case R5 : case X5 : case F5 : case V5 : case CR5: case CR1GT: return 5; 93 case R6 : case X6 : case F6 : case V6 : case CR6: case CR1EQ: return 6; 94 case R7 : case X7 : case F7 : case V7 : case CR7: case CR1UN: return 7; 95 case R8 : case X8 : case F8 : case V8 : case CR2LT: return 8; 96 case R9 : case X9 : case F9 : case V9 : case CR2GT: return 9; 97 case R10: case X10: case F10: case V10: case CR2EQ: return 10; 98 case R11: case X11: case F11: case V11: case CR2UN: return 11; 99 case R12: case X12: case F12: case V12: case CR3LT: return 12; 100 case R13: case X13: case F13: case V13: case CR3GT: return 13; 101 case R14: case X14: case F14: case V14: case CR3EQ: return 14; 102 case R15: case X15: case F15: case V15: case CR3UN: return 15; 103 case R16: case X16: case F16: case V16: case CR4LT: return 16; 104 case R17: case X17: case F17: case V17: case CR4GT: return 17; 105 case R18: case X18: case F18: case V18: case CR4EQ: return 18; 106 case R19: case X19: case F19: case V19: case CR4UN: return 19; 107 case R20: case X20: case F20: case V20: case CR5LT: return 20; 108 case R21: case X21: case F21: case V21: case CR5GT: return 21; 109 case R22: case X22: case F22: case V22: case CR5EQ: return 22; 110 case R23: case X23: case F23: case V23: case CR5UN: return 23; 111 case R24: case X24: case F24: case V24: case CR6LT: return 24; 112 case R25: case X25: case F25: case V25: case CR6GT: return 25; 113 case R26: case X26: case F26: case V26: case CR6EQ: return 26; 114 case R27: case X27: case F27: case V27: case CR6UN: return 27; 115 case R28: case X28: case F28: case V28: case CR7LT: return 28; 116 case R29: case X29: case F29: case V29: case CR7GT: return 29; 117 case R30: case X30: case F30: case V30: case CR7EQ: return 30; 118 case R31: case X31: case F31: case V31: case CR7UN: return 31; 119 default: 120 llvm_unreachable("Unhandled reg in PPCRegisterInfo::getRegisterNumbering!"); 121 } 122 } 123 124 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST, 125 const TargetInstrInfo &tii) 126 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP), 127 Subtarget(ST), TII(tii) { 128 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 129 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 130 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 131 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 132 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 133 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 134 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 135 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 136 137 // 64-bit 138 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8; 139 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8; 140 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8; 141 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX; 142 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32; 143 } 144 145 /// getPointerRegClass - Return the register class to use to hold pointers. 146 /// This is used for addressing modes. 147 const TargetRegisterClass * 148 PPCRegisterInfo::getPointerRegClass(unsigned Kind) const { 149 if (Subtarget.isPPC64()) 150 return &PPC::G8RCRegClass; 151 return &PPC::GPRCRegClass; 152 } 153 154 const unsigned* 155 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 156 // 32-bit Darwin calling convention. 157 static const unsigned Darwin32_CalleeSavedRegs[] = { 158 PPC::R13, PPC::R14, PPC::R15, 159 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 160 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 161 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 162 PPC::R28, PPC::R29, PPC::R30, PPC::R31, 163 164 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 165 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 166 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 167 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 168 PPC::F30, PPC::F31, 169 170 PPC::CR2, PPC::CR3, PPC::CR4, 171 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 172 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 173 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 174 175 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 176 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 177 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 178 179 PPC::LR, 0 180 }; 181 182 // 32-bit SVR4 calling convention. 183 static const unsigned SVR4_CalleeSavedRegs[] = { 184 PPC::R14, PPC::R15, 185 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 186 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 187 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 188 PPC::R28, PPC::R29, PPC::R30, PPC::R31, 189 190 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 191 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 192 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 193 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 194 PPC::F30, PPC::F31, 195 196 PPC::CR2, PPC::CR3, PPC::CR4, 197 198 PPC::VRSAVE, 199 200 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 201 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 202 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 203 204 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 205 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 206 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 207 208 0 209 }; 210 // 64-bit Darwin calling convention. 211 static const unsigned Darwin64_CalleeSavedRegs[] = { 212 PPC::X14, PPC::X15, 213 PPC::X16, PPC::X17, PPC::X18, PPC::X19, 214 PPC::X20, PPC::X21, PPC::X22, PPC::X23, 215 PPC::X24, PPC::X25, PPC::X26, PPC::X27, 216 PPC::X28, PPC::X29, PPC::X30, PPC::X31, 217 218 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 219 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 220 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 221 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 222 PPC::F30, PPC::F31, 223 224 PPC::CR2, PPC::CR3, PPC::CR4, 225 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 226 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 227 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 228 229 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 230 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 231 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 232 233 PPC::LR8, 0 234 }; 235 236 // 64-bit SVR4 calling convention. 237 static const unsigned SVR4_64_CalleeSavedRegs[] = { 238 PPC::X14, PPC::X15, 239 PPC::X16, PPC::X17, PPC::X18, PPC::X19, 240 PPC::X20, PPC::X21, PPC::X22, PPC::X23, 241 PPC::X24, PPC::X25, PPC::X26, PPC::X27, 242 PPC::X28, PPC::X29, PPC::X30, PPC::X31, 243 244 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 245 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 246 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 247 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 248 PPC::F30, PPC::F31, 249 250 PPC::CR2, PPC::CR3, PPC::CR4, 251 252 PPC::VRSAVE, 253 254 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 255 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 256 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 257 258 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 259 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 260 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 261 262 0 263 }; 264 265 if (Subtarget.isDarwinABI()) 266 return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegs : 267 Darwin32_CalleeSavedRegs; 268 269 return Subtarget.isPPC64() ? SVR4_64_CalleeSavedRegs : SVR4_CalleeSavedRegs; 270 } 271 272 const TargetRegisterClass* const* 273 PPCRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const { 274 // 32-bit Darwin calling convention. 275 static const TargetRegisterClass * const Darwin32_CalleeSavedRegClasses[] = { 276 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 277 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 278 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 279 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 280 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 281 282 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 283 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 284 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 285 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 286 &PPC::F8RCRegClass,&PPC::F8RCRegClass, 287 288 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, 289 290 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 291 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 292 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 293 294 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 295 &PPC::CRBITRCRegClass, 296 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 297 &PPC::CRBITRCRegClass, 298 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 299 &PPC::CRBITRCRegClass, 300 301 &PPC::GPRCRegClass, 0 302 }; 303 304 // 32-bit SVR4 calling convention. 305 static const TargetRegisterClass * const SVR4_CalleeSavedRegClasses[] = { 306 &PPC::GPRCRegClass,&PPC::GPRCRegClass, 307 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 308 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 309 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 310 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 311 312 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 313 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 314 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 315 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 316 &PPC::F8RCRegClass,&PPC::F8RCRegClass, 317 318 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, 319 320 &PPC::VRSAVERCRegClass, 321 322 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 323 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 324 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 325 326 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 327 &PPC::CRBITRCRegClass, 328 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 329 &PPC::CRBITRCRegClass, 330 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 331 &PPC::CRBITRCRegClass, 332 333 0 334 }; 335 336 // 64-bit Darwin calling convention. 337 static const TargetRegisterClass * const Darwin64_CalleeSavedRegClasses[] = { 338 &PPC::G8RCRegClass,&PPC::G8RCRegClass, 339 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 340 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 341 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 342 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 343 344 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 345 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 346 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 347 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 348 &PPC::F8RCRegClass,&PPC::F8RCRegClass, 349 350 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, 351 352 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 353 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 354 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 355 356 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 357 &PPC::CRBITRCRegClass, 358 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 359 &PPC::CRBITRCRegClass, 360 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 361 &PPC::CRBITRCRegClass, 362 363 &PPC::G8RCRegClass, 0 364 }; 365 366 // 64-bit SVR4 calling convention. 367 static const TargetRegisterClass * const SVR4_64_CalleeSavedRegClasses[] = { 368 &PPC::G8RCRegClass,&PPC::G8RCRegClass, 369 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 370 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 371 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 372 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 373 374 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 375 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 376 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 377 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 378 &PPC::F8RCRegClass,&PPC::F8RCRegClass, 379 380 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, 381 382 &PPC::VRSAVERCRegClass, 383 384 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 385 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 386 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 387 388 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 389 &PPC::CRBITRCRegClass, 390 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 391 &PPC::CRBITRCRegClass, 392 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 393 &PPC::CRBITRCRegClass, 394 395 0 396 }; 397 398 if (Subtarget.isDarwinABI()) 399 return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegClasses : 400 Darwin32_CalleeSavedRegClasses; 401 402 return Subtarget.isPPC64() ? SVR4_64_CalleeSavedRegClasses 403 : SVR4_CalleeSavedRegClasses; 404 } 405 406 // needsFP - Return true if the specified function should have a dedicated frame 407 // pointer register. This is true if the function has variable sized allocas or 408 // if frame pointer elimination is disabled. 409 // 410 static bool needsFP(const MachineFunction &MF) { 411 const MachineFrameInfo *MFI = MF.getFrameInfo(); 412 // Naked functions have no stack frame pushed, so we don't have a frame pointer. 413 if (MF.getFunction()->hasFnAttr(Attribute::Naked)) 414 return false; 415 return DisableFramePointerElim(MF) || MFI->hasVarSizedObjects() || 416 (GuaranteedTailCallOpt && MF.getInfo<PPCFunctionInfo>()->hasFastCall()); 417 } 418 419 static bool spillsCR(const MachineFunction &MF) { 420 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 421 return FuncInfo->isCRSpilled(); 422 } 423 424 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 425 BitVector Reserved(getNumRegs()); 426 Reserved.set(PPC::R0); 427 Reserved.set(PPC::R1); 428 Reserved.set(PPC::LR); 429 Reserved.set(PPC::LR8); 430 Reserved.set(PPC::RM); 431 432 // The SVR4 ABI reserves r2 and r13 433 if (Subtarget.isSVR4ABI()) { 434 Reserved.set(PPC::R2); // System-reserved register 435 Reserved.set(PPC::R13); // Small Data Area pointer register 436 } 437 // Reserve R2 on Darwin to hack around the problem of save/restore of CR 438 // when the stack frame is too big to address directly; we need two regs. 439 // This is a hack. 440 if (Subtarget.isDarwinABI()) { 441 Reserved.set(PPC::R2); 442 } 443 444 // On PPC64, r13 is the thread pointer. Never allocate this register. 445 // Note that this is over conservative, as it also prevents allocation of R31 446 // when the FP is not needed. 447 if (Subtarget.isPPC64()) { 448 Reserved.set(PPC::R13); 449 Reserved.set(PPC::R31); 450 451 if (!EnableRegisterScavenging) 452 Reserved.set(PPC::R0); // FIXME (64-bit): Remove 453 454 Reserved.set(PPC::X0); 455 Reserved.set(PPC::X1); 456 Reserved.set(PPC::X13); 457 Reserved.set(PPC::X31); 458 459 // The 64-bit SVR4 ABI reserves r2 for the TOC pointer. 460 if (Subtarget.isSVR4ABI()) { 461 Reserved.set(PPC::X2); 462 } 463 // Reserve R2 on Darwin to hack around the problem of save/restore of CR 464 // when the stack frame is too big to address directly; we need two regs. 465 // This is a hack. 466 if (Subtarget.isDarwinABI()) { 467 Reserved.set(PPC::X2); 468 } 469 } 470 471 if (needsFP(MF)) 472 Reserved.set(PPC::R31); 473 474 return Reserved; 475 } 476 477 //===----------------------------------------------------------------------===// 478 // Stack Frame Processing methods 479 //===----------------------------------------------------------------------===// 480 481 // hasFP - Return true if the specified function actually has a dedicated frame 482 // pointer register. This is true if the function needs a frame pointer and has 483 // a non-zero stack size. 484 bool PPCRegisterInfo::hasFP(const MachineFunction &MF) const { 485 const MachineFrameInfo *MFI = MF.getFrameInfo(); 486 return MFI->getStackSize() && needsFP(MF); 487 } 488 489 /// MustSaveLR - Return true if this function requires that we save the LR 490 /// register onto the stack in the prolog and restore it in the epilog of the 491 /// function. 492 static bool MustSaveLR(const MachineFunction &MF, unsigned LR) { 493 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>(); 494 495 // We need a save/restore of LR if there is any def of LR (which is 496 // defined by calls, including the PIC setup sequence), or if there is 497 // some use of the LR stack slot (e.g. for builtin_return_address). 498 // (LR comes in 32 and 64 bit versions.) 499 MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR); 500 return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired(); 501 } 502 503 504 505 void PPCRegisterInfo:: 506 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 507 MachineBasicBlock::iterator I) const { 508 if (GuaranteedTailCallOpt && I->getOpcode() == PPC::ADJCALLSTACKUP) { 509 // Add (actually subtract) back the amount the callee popped on return. 510 if (int CalleeAmt = I->getOperand(1).getImm()) { 511 bool is64Bit = Subtarget.isPPC64(); 512 CalleeAmt *= -1; 513 unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1; 514 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0; 515 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI; 516 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4; 517 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS; 518 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI; 519 MachineInstr *MI = I; 520 DebugLoc dl = MI->getDebugLoc(); 521 522 if (isInt<16>(CalleeAmt)) { 523 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg).addReg(StackReg). 524 addImm(CalleeAmt); 525 } else { 526 MachineBasicBlock::iterator MBBI = I; 527 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) 528 .addImm(CalleeAmt >> 16); 529 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) 530 .addReg(TmpReg, RegState::Kill) 531 .addImm(CalleeAmt & 0xFFFF); 532 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr)) 533 .addReg(StackReg) 534 .addReg(StackReg) 535 .addReg(TmpReg); 536 } 537 } 538 } 539 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions. 540 MBB.erase(I); 541 } 542 543 /// findScratchRegister - Find a 'free' PPC register. Try for a call-clobbered 544 /// register first and then a spilled callee-saved register if that fails. 545 static 546 unsigned findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS, 547 const TargetRegisterClass *RC, int SPAdj) { 548 assert(RS && "Register scavenging must be on"); 549 unsigned Reg = RS->FindUnusedReg(RC); 550 // FIXME: move ARM callee-saved reg scan to target independent code, then 551 // search for already spilled CS register here. 552 if (Reg == 0) 553 Reg = RS->scavengeRegister(RC, II, SPAdj); 554 return Reg; 555 } 556 557 /// lowerDynamicAlloc - Generate the code for allocating an object in the 558 /// current frame. The sequence of code with be in the general form 559 /// 560 /// addi R0, SP, \#frameSize ; get the address of the previous frame 561 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size 562 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation 563 /// 564 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II, 565 int SPAdj, RegScavenger *RS) const { 566 // Get the instruction. 567 MachineInstr &MI = *II; 568 // Get the instruction's basic block. 569 MachineBasicBlock &MBB = *MI.getParent(); 570 // Get the basic block's function. 571 MachineFunction &MF = *MBB.getParent(); 572 // Get the frame info. 573 MachineFrameInfo *MFI = MF.getFrameInfo(); 574 // Determine whether 64-bit pointers are used. 575 bool LP64 = Subtarget.isPPC64(); 576 DebugLoc dl = MI.getDebugLoc(); 577 578 // Get the maximum call stack size. 579 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 580 // Get the total frame size. 581 unsigned FrameSize = MFI->getStackSize(); 582 583 // Get stack alignments. 584 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 585 unsigned MaxAlign = MFI->getMaxAlignment(); 586 assert(MaxAlign <= TargetAlign && 587 "Dynamic alloca with large aligns not supported"); 588 589 // Determine the previous frame's address. If FrameSize can't be 590 // represented as 16 bits or we need special alignment, then we load the 591 // previous frame's address from 0(SP). Why not do an addis of the hi? 592 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. 593 // Constructing the constant and adding would take 3 instructions. 594 // Fortunately, a frame greater than 32K is rare. 595 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 596 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 597 const TargetRegisterClass *RC = LP64 ? G8RC : GPRC; 598 599 // FIXME (64-bit): Use "findScratchRegister" 600 unsigned Reg; 601 if (EnableRegisterScavenging) 602 Reg = findScratchRegister(II, RS, RC, SPAdj); 603 else 604 Reg = PPC::R0; 605 606 if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) { 607 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) 608 .addReg(PPC::R31) 609 .addImm(FrameSize); 610 } else if (LP64) { 611 if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part. 612 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg) 613 .addImm(0) 614 .addReg(PPC::X1); 615 else 616 BuildMI(MBB, II, dl, TII.get(PPC::LD), PPC::X0) 617 .addImm(0) 618 .addReg(PPC::X1); 619 } else { 620 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) 621 .addImm(0) 622 .addReg(PPC::R1); 623 } 624 625 // Grow the stack and update the stack pointer link, then determine the 626 // address of new allocated space. 627 if (LP64) { 628 if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part. 629 BuildMI(MBB, II, dl, TII.get(PPC::STDUX)) 630 .addReg(Reg, RegState::Kill) 631 .addReg(PPC::X1) 632 .addReg(MI.getOperand(1).getReg()); 633 else 634 BuildMI(MBB, II, dl, TII.get(PPC::STDUX)) 635 .addReg(PPC::X0, RegState::Kill) 636 .addReg(PPC::X1) 637 .addReg(MI.getOperand(1).getReg()); 638 639 if (!MI.getOperand(1).isKill()) 640 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 641 .addReg(PPC::X1) 642 .addImm(maxCallFrameSize); 643 else 644 // Implicitly kill the register. 645 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 646 .addReg(PPC::X1) 647 .addImm(maxCallFrameSize) 648 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill); 649 } else { 650 BuildMI(MBB, II, dl, TII.get(PPC::STWUX)) 651 .addReg(Reg, RegState::Kill) 652 .addReg(PPC::R1) 653 .addReg(MI.getOperand(1).getReg()); 654 655 if (!MI.getOperand(1).isKill()) 656 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 657 .addReg(PPC::R1) 658 .addImm(maxCallFrameSize); 659 else 660 // Implicitly kill the register. 661 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 662 .addReg(PPC::R1) 663 .addImm(maxCallFrameSize) 664 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill); 665 } 666 667 // Discard the DYNALLOC instruction. 668 MBB.erase(II); 669 } 670 671 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of 672 /// reserving a whole register (R0), we scrounge for one here. This generates 673 /// code like this: 674 /// 675 /// mfcr rA ; Move the conditional register into GPR rA. 676 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot. 677 /// stw rA, FI ; Store rA to the frame. 678 /// 679 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, 680 unsigned FrameIndex, int SPAdj, 681 RegScavenger *RS) const { 682 // Get the instruction. 683 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>, <FI> 684 // Get the instruction's basic block. 685 MachineBasicBlock &MBB = *MI.getParent(); 686 DebugLoc dl = MI.getDebugLoc(); 687 688 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 689 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 690 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC; 691 unsigned Reg = findScratchRegister(II, RS, RC, SPAdj); 692 unsigned SrcReg = MI.getOperand(0).getReg(); 693 694 // We need to store the CR in the low 4-bits of the saved value. First, issue 695 // an MFCRpsued to save all of the CRBits and, if needed, kill the SrcReg. 696 BuildMI(MBB, II, dl, TII.get(PPC::MFCRpseud), Reg) 697 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 698 699 // If the saved register wasn't CR0, shift the bits left so that they are in 700 // CR0's slot. 701 if (SrcReg != PPC::CR0) 702 // rlwinm rA, rA, ShiftBits, 0, 31. 703 BuildMI(MBB, II, dl, TII.get(PPC::RLWINM), Reg) 704 .addReg(Reg, RegState::Kill) 705 .addImm(PPCRegisterInfo::getRegisterNumbering(SrcReg) * 4) 706 .addImm(0) 707 .addImm(31); 708 709 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::STW)) 710 .addReg(Reg, getKillRegState(MI.getOperand(1).getImm())), 711 FrameIndex); 712 713 // Discard the pseudo instruction. 714 MBB.erase(II); 715 } 716 717 unsigned 718 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 719 int SPAdj, FrameIndexValue *Value, 720 RegScavenger *RS) const { 721 assert(SPAdj == 0 && "Unexpected"); 722 723 // Get the instruction. 724 MachineInstr &MI = *II; 725 // Get the instruction's basic block. 726 MachineBasicBlock &MBB = *MI.getParent(); 727 // Get the basic block's function. 728 MachineFunction &MF = *MBB.getParent(); 729 // Get the frame info. 730 MachineFrameInfo *MFI = MF.getFrameInfo(); 731 DebugLoc dl = MI.getDebugLoc(); 732 733 // Find out which operand is the frame index. 734 unsigned FIOperandNo = 0; 735 while (!MI.getOperand(FIOperandNo).isFI()) { 736 ++FIOperandNo; 737 assert(FIOperandNo != MI.getNumOperands() && 738 "Instr doesn't have FrameIndex operand!"); 739 } 740 // Take into account whether it's an add or mem instruction 741 unsigned OffsetOperandNo = (FIOperandNo == 2) ? 1 : 2; 742 if (MI.isInlineAsm()) 743 OffsetOperandNo = FIOperandNo-1; 744 745 // Get the frame index. 746 int FrameIndex = MI.getOperand(FIOperandNo).getIndex(); 747 748 // Get the frame pointer save index. Users of this index are primarily 749 // DYNALLOC instructions. 750 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 751 int FPSI = FI->getFramePointerSaveIndex(); 752 // Get the instruction opcode. 753 unsigned OpC = MI.getOpcode(); 754 755 // Special case for dynamic alloca. 756 if (FPSI && FrameIndex == FPSI && 757 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { 758 lowerDynamicAlloc(II, SPAdj, RS); 759 return 0; 760 } 761 762 // Special case for pseudo-op SPILL_CR. 763 if (EnableRegisterScavenging) // FIXME (64-bit): Enable by default. 764 if (OpC == PPC::SPILL_CR) { 765 lowerCRSpilling(II, FrameIndex, SPAdj, RS); 766 return 0; 767 } 768 769 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 770 MI.getOperand(FIOperandNo).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1, 771 false); 772 773 // Figure out if the offset in the instruction is shifted right two bits. This 774 // is true for instructions like "STD", which the machine implicitly adds two 775 // low zeros to. 776 bool isIXAddr = false; 777 switch (OpC) { 778 case PPC::LWA: 779 case PPC::LD: 780 case PPC::STD: 781 case PPC::STD_32: 782 isIXAddr = true; 783 break; 784 } 785 786 // Now add the frame object offset to the offset from r1. 787 int Offset = MFI->getObjectOffset(FrameIndex); 788 if (!isIXAddr) 789 Offset += MI.getOperand(OffsetOperandNo).getImm(); 790 else 791 Offset += MI.getOperand(OffsetOperandNo).getImm() << 2; 792 793 // If we're not using a Frame Pointer that has been set to the value of the 794 // SP before having the stack size subtracted from it, then add the stack size 795 // to Offset to get the correct offset. 796 // Naked functions have stack size 0, although getStackSize may not reflect that 797 // because we didn't call all the pieces that compute it for naked functions. 798 if (!MF.getFunction()->hasFnAttr(Attribute::Naked)) 799 Offset += MFI->getStackSize(); 800 801 // If we can, encode the offset directly into the instruction. If this is a 802 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If 803 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits 804 // clear can be encoded. This is extremely uncommon, because normally you 805 // only "std" to a stack slot that is at least 4-byte aligned, but it can 806 // happen in invalid code. 807 if (isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0)) { 808 if (isIXAddr) 809 Offset >>= 2; // The actual encoded value has the low two bits zero. 810 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 811 return 0; 812 } 813 814 // The offset doesn't fit into a single register, scavenge one to build the 815 // offset in. 816 // FIXME: figure out what SPAdj is doing here. 817 818 // FIXME (64-bit): Use "findScratchRegister". 819 unsigned SReg; 820 if (EnableRegisterScavenging) 821 SReg = findScratchRegister(II, RS, &PPC::GPRCRegClass, SPAdj); 822 else 823 SReg = PPC::R0; 824 825 // Insert a set of rA with the full offset value before the ld, st, or add 826 BuildMI(MBB, II, dl, TII.get(PPC::LIS), SReg) 827 .addImm(Offset >> 16); 828 BuildMI(MBB, II, dl, TII.get(PPC::ORI), SReg) 829 .addReg(SReg, RegState::Kill) 830 .addImm(Offset); 831 832 // Convert into indexed form of the instruction: 833 // 834 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 835 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 836 unsigned OperandBase; 837 838 if (OpC != TargetOpcode::INLINEASM) { 839 assert(ImmToIdxMap.count(OpC) && 840 "No indexed form of load or store available!"); 841 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; 842 MI.setDesc(TII.get(NewOpcode)); 843 OperandBase = 1; 844 } else { 845 OperandBase = OffsetOperandNo; 846 } 847 848 unsigned StackReg = MI.getOperand(FIOperandNo).getReg(); 849 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false); 850 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false); 851 return 0; 852 } 853 854 /// VRRegNo - Map from a numbered VR register to its enum value. 855 /// 856 static const unsigned short VRRegNo[] = { 857 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 , 858 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, 859 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, 860 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31 861 }; 862 863 /// RemoveVRSaveCode - We have found that this function does not need any code 864 /// to manipulate the VRSAVE register, even though it uses vector registers. 865 /// This can happen when the only registers used are known to be live in or out 866 /// of the function. Remove all of the VRSAVE related code from the function. 867 static void RemoveVRSaveCode(MachineInstr *MI) { 868 MachineBasicBlock *Entry = MI->getParent(); 869 MachineFunction *MF = Entry->getParent(); 870 871 // We know that the MTVRSAVE instruction immediately follows MI. Remove it. 872 MachineBasicBlock::iterator MBBI = MI; 873 ++MBBI; 874 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE); 875 MBBI->eraseFromParent(); 876 877 bool RemovedAllMTVRSAVEs = true; 878 // See if we can find and remove the MTVRSAVE instruction from all of the 879 // epilog blocks. 880 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) { 881 // If last instruction is a return instruction, add an epilogue 882 if (!I->empty() && I->back().getDesc().isReturn()) { 883 bool FoundIt = false; 884 for (MBBI = I->end(); MBBI != I->begin(); ) { 885 --MBBI; 886 if (MBBI->getOpcode() == PPC::MTVRSAVE) { 887 MBBI->eraseFromParent(); // remove it. 888 FoundIt = true; 889 break; 890 } 891 } 892 RemovedAllMTVRSAVEs &= FoundIt; 893 } 894 } 895 896 // If we found and removed all MTVRSAVE instructions, remove the read of 897 // VRSAVE as well. 898 if (RemovedAllMTVRSAVEs) { 899 MBBI = MI; 900 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?"); 901 --MBBI; 902 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?"); 903 MBBI->eraseFromParent(); 904 } 905 906 // Finally, nuke the UPDATE_VRSAVE. 907 MI->eraseFromParent(); 908 } 909 910 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the 911 // instruction selector. Based on the vector registers that have been used, 912 // transform this into the appropriate ORI instruction. 913 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) { 914 MachineFunction *MF = MI->getParent()->getParent(); 915 DebugLoc dl = MI->getDebugLoc(); 916 917 unsigned UsedRegMask = 0; 918 for (unsigned i = 0; i != 32; ++i) 919 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i])) 920 UsedRegMask |= 1 << (31-i); 921 922 // Live in and live out values already must be in the mask, so don't bother 923 // marking them. 924 for (MachineRegisterInfo::livein_iterator 925 I = MF->getRegInfo().livein_begin(), 926 E = MF->getRegInfo().livein_end(); I != E; ++I) { 927 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first); 928 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg. 929 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 930 } 931 for (MachineRegisterInfo::liveout_iterator 932 I = MF->getRegInfo().liveout_begin(), 933 E = MF->getRegInfo().liveout_end(); I != E; ++I) { 934 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I); 935 if (VRRegNo[RegNo] == *I) // If this really is a vector reg. 936 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 937 } 938 939 // If no registers are used, turn this into a copy. 940 if (UsedRegMask == 0) { 941 // Remove all VRSAVE code. 942 RemoveVRSaveCode(MI); 943 return; 944 } 945 946 unsigned SrcReg = MI->getOperand(1).getReg(); 947 unsigned DstReg = MI->getOperand(0).getReg(); 948 949 if ((UsedRegMask & 0xFFFF) == UsedRegMask) { 950 if (DstReg != SrcReg) 951 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 952 .addReg(SrcReg) 953 .addImm(UsedRegMask); 954 else 955 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 956 .addReg(SrcReg, RegState::Kill) 957 .addImm(UsedRegMask); 958 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { 959 if (DstReg != SrcReg) 960 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 961 .addReg(SrcReg) 962 .addImm(UsedRegMask >> 16); 963 else 964 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 965 .addReg(SrcReg, RegState::Kill) 966 .addImm(UsedRegMask >> 16); 967 } else { 968 if (DstReg != SrcReg) 969 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 970 .addReg(SrcReg) 971 .addImm(UsedRegMask >> 16); 972 else 973 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 974 .addReg(SrcReg, RegState::Kill) 975 .addImm(UsedRegMask >> 16); 976 977 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 978 .addReg(DstReg, RegState::Kill) 979 .addImm(UsedRegMask & 0xFFFF); 980 } 981 982 // Remove the old UPDATE_VRSAVE instruction. 983 MI->eraseFromParent(); 984 } 985 986 /// determineFrameLayout - Determine the size of the frame and maximum call 987 /// frame size. 988 void PPCRegisterInfo::determineFrameLayout(MachineFunction &MF) const { 989 MachineFrameInfo *MFI = MF.getFrameInfo(); 990 991 // Get the number of bytes to allocate from the FrameInfo 992 unsigned FrameSize = MFI->getStackSize(); 993 994 // Get the alignments provided by the target, and the maximum alignment 995 // (if any) of the fixed frame objects. 996 unsigned MaxAlign = MFI->getMaxAlignment(); 997 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 998 unsigned AlignMask = TargetAlign - 1; // 999 1000 // If we are a leaf function, and use up to 224 bytes of stack space, 1001 // don't have a frame pointer, calls, or dynamic alloca then we do not need 1002 // to adjust the stack pointer (we fit in the Red Zone). 1003 bool DisableRedZone = MF.getFunction()->hasFnAttr(Attribute::NoRedZone); 1004 // FIXME SVR4 The 32-bit SVR4 ABI has no red zone. 1005 if (!DisableRedZone && 1006 FrameSize <= 224 && // Fits in red zone. 1007 !MFI->hasVarSizedObjects() && // No dynamic alloca. 1008 !MFI->adjustsStack() && // No calls. 1009 (!ALIGN_STACK || MaxAlign <= TargetAlign)) { // No special alignment. 1010 // No need for frame 1011 MFI->setStackSize(0); 1012 return; 1013 } 1014 1015 // Get the maximum call frame size of all the calls. 1016 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 1017 1018 // Maximum call frame needs to be at least big enough for linkage and 8 args. 1019 unsigned minCallFrameSize = 1020 PPCFrameInfo::getMinCallFrameSize(Subtarget.isPPC64(), 1021 Subtarget.isDarwinABI()); 1022 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize); 1023 1024 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so 1025 // that allocations will be aligned. 1026 if (MFI->hasVarSizedObjects()) 1027 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask; 1028 1029 // Update maximum call frame size. 1030 MFI->setMaxCallFrameSize(maxCallFrameSize); 1031 1032 // Include call frame size in total. 1033 FrameSize += maxCallFrameSize; 1034 1035 // Make sure the frame is aligned. 1036 FrameSize = (FrameSize + AlignMask) & ~AlignMask; 1037 1038 // Update frame info. 1039 MFI->setStackSize(FrameSize); 1040 } 1041 1042 void 1043 PPCRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 1044 RegScavenger *RS) const { 1045 // Save and clear the LR state. 1046 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1047 unsigned LR = getRARegister(); 1048 FI->setMustSaveLR(MustSaveLR(MF, LR)); 1049 MF.getRegInfo().setPhysRegUnused(LR); 1050 1051 // Save R31 if necessary 1052 int FPSI = FI->getFramePointerSaveIndex(); 1053 bool isPPC64 = Subtarget.isPPC64(); 1054 bool isDarwinABI = Subtarget.isDarwinABI(); 1055 MachineFrameInfo *MFI = MF.getFrameInfo(); 1056 1057 // If the frame pointer save index hasn't been defined yet. 1058 if (!FPSI && needsFP(MF)) { 1059 // Find out what the fix offset of the frame pointer save area. 1060 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(isPPC64, 1061 isDarwinABI); 1062 // Allocate the frame index for frame pointer save area. 1063 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, 1064 true, false); 1065 // Save the result. 1066 FI->setFramePointerSaveIndex(FPSI); 1067 } 1068 1069 // Reserve stack space to move the linkage area to in case of a tail call. 1070 int TCSPDelta = 0; 1071 if (GuaranteedTailCallOpt && (TCSPDelta = FI->getTailCallSPDelta()) < 0) { 1072 MF.getFrameInfo()->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, 1073 true, false); 1074 } 1075 1076 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or 1077 // a large stack, which will require scavenging a register to materialize a 1078 // large offset. 1079 // FIXME: this doesn't actually check stack size, so is a bit pessimistic 1080 // FIXME: doesn't detect whether or not we need to spill vXX, which requires 1081 // r0 for now. 1082 1083 if (EnableRegisterScavenging) // FIXME (64-bit): Enable. 1084 if (needsFP(MF) || spillsCR(MF)) { 1085 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 1086 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 1087 const TargetRegisterClass *RC = isPPC64 ? G8RC : GPRC; 1088 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 1089 RC->getAlignment(), 1090 false)); 1091 } 1092 } 1093 1094 void 1095 PPCRegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) 1096 const { 1097 // Early exit if not using the SVR4 ABI. 1098 if (!Subtarget.isSVR4ABI()) { 1099 return; 1100 } 1101 1102 // Get callee saved register information. 1103 MachineFrameInfo *FFI = MF.getFrameInfo(); 1104 const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo(); 1105 1106 // Early exit if no callee saved registers are modified! 1107 if (CSI.empty() && !needsFP(MF)) { 1108 return; 1109 } 1110 1111 unsigned MinGPR = PPC::R31; 1112 unsigned MinG8R = PPC::X31; 1113 unsigned MinFPR = PPC::F31; 1114 unsigned MinVR = PPC::V31; 1115 1116 bool HasGPSaveArea = false; 1117 bool HasG8SaveArea = false; 1118 bool HasFPSaveArea = false; 1119 bool HasCRSaveArea = false; 1120 bool HasVRSAVESaveArea = false; 1121 bool HasVRSaveArea = false; 1122 1123 SmallVector<CalleeSavedInfo, 18> GPRegs; 1124 SmallVector<CalleeSavedInfo, 18> G8Regs; 1125 SmallVector<CalleeSavedInfo, 18> FPRegs; 1126 SmallVector<CalleeSavedInfo, 18> VRegs; 1127 1128 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1129 unsigned Reg = CSI[i].getReg(); 1130 const TargetRegisterClass *RC = CSI[i].getRegClass(); 1131 1132 if (RC == PPC::GPRCRegisterClass) { 1133 HasGPSaveArea = true; 1134 1135 GPRegs.push_back(CSI[i]); 1136 1137 if (Reg < MinGPR) { 1138 MinGPR = Reg; 1139 } 1140 } else if (RC == PPC::G8RCRegisterClass) { 1141 HasG8SaveArea = true; 1142 1143 G8Regs.push_back(CSI[i]); 1144 1145 if (Reg < MinG8R) { 1146 MinG8R = Reg; 1147 } 1148 } else if (RC == PPC::F8RCRegisterClass) { 1149 HasFPSaveArea = true; 1150 1151 FPRegs.push_back(CSI[i]); 1152 1153 if (Reg < MinFPR) { 1154 MinFPR = Reg; 1155 } 1156 // FIXME SVR4: Disable CR save area for now. 1157 } else if ( RC == PPC::CRBITRCRegisterClass 1158 || RC == PPC::CRRCRegisterClass) { 1159 // HasCRSaveArea = true; 1160 } else if (RC == PPC::VRSAVERCRegisterClass) { 1161 HasVRSAVESaveArea = true; 1162 } else if (RC == PPC::VRRCRegisterClass) { 1163 HasVRSaveArea = true; 1164 1165 VRegs.push_back(CSI[i]); 1166 1167 if (Reg < MinVR) { 1168 MinVR = Reg; 1169 } 1170 } else { 1171 llvm_unreachable("Unknown RegisterClass!"); 1172 } 1173 } 1174 1175 PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>(); 1176 1177 int64_t LowerBound = 0; 1178 1179 // Take into account stack space reserved for tail calls. 1180 int TCSPDelta = 0; 1181 if (GuaranteedTailCallOpt && (TCSPDelta = PFI->getTailCallSPDelta()) < 0) { 1182 LowerBound = TCSPDelta; 1183 } 1184 1185 // The Floating-point register save area is right below the back chain word 1186 // of the previous stack frame. 1187 if (HasFPSaveArea) { 1188 for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) { 1189 int FI = FPRegs[i].getFrameIdx(); 1190 1191 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1192 } 1193 1194 LowerBound -= (31 - getRegisterNumbering(MinFPR) + 1) * 8; 1195 } 1196 1197 // Check whether the frame pointer register is allocated. If so, make sure it 1198 // is spilled to the correct offset. 1199 if (needsFP(MF)) { 1200 HasGPSaveArea = true; 1201 1202 int FI = PFI->getFramePointerSaveIndex(); 1203 assert(FI && "No Frame Pointer Save Slot!"); 1204 1205 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1206 } 1207 1208 // General register save area starts right below the Floating-point 1209 // register save area. 1210 if (HasGPSaveArea || HasG8SaveArea) { 1211 // Move general register save area spill slots down, taking into account 1212 // the size of the Floating-point register save area. 1213 for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) { 1214 int FI = GPRegs[i].getFrameIdx(); 1215 1216 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1217 } 1218 1219 // Move general register save area spill slots down, taking into account 1220 // the size of the Floating-point register save area. 1221 for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) { 1222 int FI = G8Regs[i].getFrameIdx(); 1223 1224 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1225 } 1226 1227 unsigned MinReg = std::min<unsigned>(getRegisterNumbering(MinGPR), 1228 getRegisterNumbering(MinG8R)); 1229 1230 if (Subtarget.isPPC64()) { 1231 LowerBound -= (31 - MinReg + 1) * 8; 1232 } else { 1233 LowerBound -= (31 - MinReg + 1) * 4; 1234 } 1235 } 1236 1237 // The CR save area is below the general register save area. 1238 if (HasCRSaveArea) { 1239 // FIXME SVR4: Is it actually possible to have multiple elements in CSI 1240 // which have the CR/CRBIT register class? 1241 // Adjust the frame index of the CR spill slot. 1242 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1243 const TargetRegisterClass *RC = CSI[i].getRegClass(); 1244 1245 if (RC == PPC::CRBITRCRegisterClass || RC == PPC::CRRCRegisterClass) { 1246 int FI = CSI[i].getFrameIdx(); 1247 1248 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1249 } 1250 } 1251 1252 LowerBound -= 4; // The CR save area is always 4 bytes long. 1253 } 1254 1255 if (HasVRSAVESaveArea) { 1256 // FIXME SVR4: Is it actually possible to have multiple elements in CSI 1257 // which have the VRSAVE register class? 1258 // Adjust the frame index of the VRSAVE spill slot. 1259 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1260 const TargetRegisterClass *RC = CSI[i].getRegClass(); 1261 1262 if (RC == PPC::VRSAVERCRegisterClass) { 1263 int FI = CSI[i].getFrameIdx(); 1264 1265 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1266 } 1267 } 1268 1269 LowerBound -= 4; // The VRSAVE save area is always 4 bytes long. 1270 } 1271 1272 if (HasVRSaveArea) { 1273 // Insert alignment padding, we need 16-byte alignment. 1274 LowerBound = (LowerBound - 15) & ~(15); 1275 1276 for (unsigned i = 0, e = VRegs.size(); i != e; ++i) { 1277 int FI = VRegs[i].getFrameIdx(); 1278 1279 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1280 } 1281 } 1282 } 1283 1284 void 1285 PPCRegisterInfo::emitPrologue(MachineFunction &MF) const { 1286 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB 1287 MachineBasicBlock::iterator MBBI = MBB.begin(); 1288 MachineFrameInfo *MFI = MF.getFrameInfo(); 1289 MachineModuleInfo &MMI = MF.getMMI(); 1290 DebugLoc dl; 1291 bool needsFrameMoves = MMI.hasDebugInfo() || 1292 !MF.getFunction()->doesNotThrow() || 1293 UnwindTablesMandatory; 1294 1295 // Prepare for frame info. 1296 MCSymbol *FrameLabel = 0; 1297 1298 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it, 1299 // process it. 1300 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { 1301 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) { 1302 HandleVRSaveUpdate(MBBI, TII); 1303 break; 1304 } 1305 } 1306 1307 // Move MBBI back to the beginning of the function. 1308 MBBI = MBB.begin(); 1309 1310 // Work out frame sizes. 1311 determineFrameLayout(MF); 1312 unsigned FrameSize = MFI->getStackSize(); 1313 1314 int NegFrameSize = -FrameSize; 1315 1316 // Get processor type. 1317 bool isPPC64 = Subtarget.isPPC64(); 1318 // Get operating system 1319 bool isDarwinABI = Subtarget.isDarwinABI(); 1320 // Check if the link register (LR) must be saved. 1321 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1322 bool MustSaveLR = FI->mustSaveLR(); 1323 // Do we have a frame pointer for this function? 1324 bool HasFP = hasFP(MF) && FrameSize; 1325 1326 int LROffset = PPCFrameInfo::getReturnSaveOffset(isPPC64, isDarwinABI); 1327 1328 int FPOffset = 0; 1329 if (HasFP) { 1330 if (Subtarget.isSVR4ABI()) { 1331 MachineFrameInfo *FFI = MF.getFrameInfo(); 1332 int FPIndex = FI->getFramePointerSaveIndex(); 1333 assert(FPIndex && "No Frame Pointer Save Slot!"); 1334 FPOffset = FFI->getObjectOffset(FPIndex); 1335 } else { 1336 FPOffset = PPCFrameInfo::getFramePointerSaveOffset(isPPC64, isDarwinABI); 1337 } 1338 } 1339 1340 if (isPPC64) { 1341 if (MustSaveLR) 1342 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR8), PPC::X0); 1343 1344 if (HasFP) 1345 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD)) 1346 .addReg(PPC::X31) 1347 .addImm(FPOffset/4) 1348 .addReg(PPC::X1); 1349 1350 if (MustSaveLR) 1351 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD)) 1352 .addReg(PPC::X0) 1353 .addImm(LROffset / 4) 1354 .addReg(PPC::X1); 1355 } else { 1356 if (MustSaveLR) 1357 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR), PPC::R0); 1358 1359 if (HasFP) 1360 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW)) 1361 .addReg(PPC::R31) 1362 .addImm(FPOffset) 1363 .addReg(PPC::R1); 1364 1365 if (MustSaveLR) 1366 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW)) 1367 .addReg(PPC::R0) 1368 .addImm(LROffset) 1369 .addReg(PPC::R1); 1370 } 1371 1372 // Skip if a leaf routine. 1373 if (!FrameSize) return; 1374 1375 // Get stack alignments. 1376 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 1377 unsigned MaxAlign = MFI->getMaxAlignment(); 1378 1379 // Adjust stack pointer: r1 += NegFrameSize. 1380 // If there is a preferred stack alignment, align R1 now 1381 if (!isPPC64) { 1382 // PPC32. 1383 if (ALIGN_STACK && MaxAlign > TargetAlign) { 1384 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) && 1385 "Invalid alignment!"); 1386 assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!"); 1387 1388 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), PPC::R0) 1389 .addReg(PPC::R1) 1390 .addImm(0) 1391 .addImm(32 - Log2_32(MaxAlign)) 1392 .addImm(31); 1393 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC) ,PPC::R0) 1394 .addReg(PPC::R0, RegState::Kill) 1395 .addImm(NegFrameSize); 1396 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX)) 1397 .addReg(PPC::R1) 1398 .addReg(PPC::R1) 1399 .addReg(PPC::R0); 1400 } else if (isInt<16>(NegFrameSize)) { 1401 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWU), PPC::R1) 1402 .addReg(PPC::R1) 1403 .addImm(NegFrameSize) 1404 .addReg(PPC::R1); 1405 } else { 1406 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0) 1407 .addImm(NegFrameSize >> 16); 1408 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0) 1409 .addReg(PPC::R0, RegState::Kill) 1410 .addImm(NegFrameSize & 0xFFFF); 1411 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX)) 1412 .addReg(PPC::R1) 1413 .addReg(PPC::R1) 1414 .addReg(PPC::R0); 1415 } 1416 } else { // PPC64. 1417 if (ALIGN_STACK && MaxAlign > TargetAlign) { 1418 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) && 1419 "Invalid alignment!"); 1420 assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!"); 1421 1422 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), PPC::X0) 1423 .addReg(PPC::X1) 1424 .addImm(0) 1425 .addImm(64 - Log2_32(MaxAlign)); 1426 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC8), PPC::X0) 1427 .addReg(PPC::X0) 1428 .addImm(NegFrameSize); 1429 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX)) 1430 .addReg(PPC::X1) 1431 .addReg(PPC::X1) 1432 .addReg(PPC::X0); 1433 } else if (isInt<16>(NegFrameSize)) { 1434 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDU), PPC::X1) 1435 .addReg(PPC::X1) 1436 .addImm(NegFrameSize / 4) 1437 .addReg(PPC::X1); 1438 } else { 1439 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0) 1440 .addImm(NegFrameSize >> 16); 1441 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0) 1442 .addReg(PPC::X0, RegState::Kill) 1443 .addImm(NegFrameSize & 0xFFFF); 1444 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX)) 1445 .addReg(PPC::X1) 1446 .addReg(PPC::X1) 1447 .addReg(PPC::X0); 1448 } 1449 } 1450 1451 std::vector<MachineMove> &Moves = MMI.getFrameMoves(); 1452 1453 // Add the "machine moves" for the instructions we generated above, but in 1454 // reverse order. 1455 if (needsFrameMoves) { 1456 // Mark effective beginning of when frame pointer becomes valid. 1457 FrameLabel = MMI.getContext().CreateTempSymbol(); 1458 BuildMI(MBB, MBBI, dl, TII.get(PPC::DBG_LABEL)).addSym(FrameLabel); 1459 1460 // Show update of SP. 1461 if (NegFrameSize) { 1462 MachineLocation SPDst(MachineLocation::VirtualFP); 1463 MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize); 1464 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc)); 1465 } else { 1466 MachineLocation SP(isPPC64 ? PPC::X31 : PPC::R31); 1467 Moves.push_back(MachineMove(FrameLabel, SP, SP)); 1468 } 1469 1470 if (HasFP) { 1471 MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset); 1472 MachineLocation FPSrc(isPPC64 ? PPC::X31 : PPC::R31); 1473 Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc)); 1474 } 1475 1476 if (MustSaveLR) { 1477 MachineLocation LRDst(MachineLocation::VirtualFP, LROffset); 1478 MachineLocation LRSrc(isPPC64 ? PPC::LR8 : PPC::LR); 1479 Moves.push_back(MachineMove(FrameLabel, LRDst, LRSrc)); 1480 } 1481 } 1482 1483 MCSymbol *ReadyLabel = 0; 1484 1485 // If there is a frame pointer, copy R1 into R31 1486 if (HasFP) { 1487 if (!isPPC64) { 1488 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR), PPC::R31) 1489 .addReg(PPC::R1) 1490 .addReg(PPC::R1); 1491 } else { 1492 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR8), PPC::X31) 1493 .addReg(PPC::X1) 1494 .addReg(PPC::X1); 1495 } 1496 1497 if (needsFrameMoves) { 1498 ReadyLabel = MMI.getContext().CreateTempSymbol(); 1499 1500 // Mark effective beginning of when frame pointer is ready. 1501 BuildMI(MBB, MBBI, dl, TII.get(PPC::DBG_LABEL)).addSym(ReadyLabel); 1502 1503 MachineLocation FPDst(HasFP ? (isPPC64 ? PPC::X31 : PPC::R31) : 1504 (isPPC64 ? PPC::X1 : PPC::R1)); 1505 MachineLocation FPSrc(MachineLocation::VirtualFP); 1506 Moves.push_back(MachineMove(ReadyLabel, FPDst, FPSrc)); 1507 } 1508 } 1509 1510 if (needsFrameMoves) { 1511 MCSymbol *Label = HasFP ? ReadyLabel : FrameLabel; 1512 1513 // Add callee saved registers to move list. 1514 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 1515 for (unsigned I = 0, E = CSI.size(); I != E; ++I) { 1516 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx()); 1517 unsigned Reg = CSI[I].getReg(); 1518 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue; 1519 MachineLocation CSDst(MachineLocation::VirtualFP, Offset); 1520 MachineLocation CSSrc(Reg); 1521 Moves.push_back(MachineMove(Label, CSDst, CSSrc)); 1522 } 1523 } 1524 } 1525 1526 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF, 1527 MachineBasicBlock &MBB) const { 1528 MachineBasicBlock::iterator MBBI = prior(MBB.end()); 1529 unsigned RetOpcode = MBBI->getOpcode(); 1530 DebugLoc dl; 1531 1532 assert( (RetOpcode == PPC::BLR || 1533 RetOpcode == PPC::TCRETURNri || 1534 RetOpcode == PPC::TCRETURNdi || 1535 RetOpcode == PPC::TCRETURNai || 1536 RetOpcode == PPC::TCRETURNri8 || 1537 RetOpcode == PPC::TCRETURNdi8 || 1538 RetOpcode == PPC::TCRETURNai8) && 1539 "Can only insert epilog into returning blocks"); 1540 1541 // Get alignment info so we know how to restore r1 1542 const MachineFrameInfo *MFI = MF.getFrameInfo(); 1543 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 1544 unsigned MaxAlign = MFI->getMaxAlignment(); 1545 1546 // Get the number of bytes allocated from the FrameInfo. 1547 int FrameSize = MFI->getStackSize(); 1548 1549 // Get processor type. 1550 bool isPPC64 = Subtarget.isPPC64(); 1551 // Get operating system 1552 bool isDarwinABI = Subtarget.isDarwinABI(); 1553 // Check if the link register (LR) has been saved. 1554 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1555 bool MustSaveLR = FI->mustSaveLR(); 1556 // Do we have a frame pointer for this function? 1557 bool HasFP = hasFP(MF) && FrameSize; 1558 1559 int LROffset = PPCFrameInfo::getReturnSaveOffset(isPPC64, isDarwinABI); 1560 1561 int FPOffset = 0; 1562 if (HasFP) { 1563 if (Subtarget.isSVR4ABI()) { 1564 MachineFrameInfo *FFI = MF.getFrameInfo(); 1565 int FPIndex = FI->getFramePointerSaveIndex(); 1566 assert(FPIndex && "No Frame Pointer Save Slot!"); 1567 FPOffset = FFI->getObjectOffset(FPIndex); 1568 } else { 1569 FPOffset = PPCFrameInfo::getFramePointerSaveOffset(isPPC64, isDarwinABI); 1570 } 1571 } 1572 1573 bool UsesTCRet = RetOpcode == PPC::TCRETURNri || 1574 RetOpcode == PPC::TCRETURNdi || 1575 RetOpcode == PPC::TCRETURNai || 1576 RetOpcode == PPC::TCRETURNri8 || 1577 RetOpcode == PPC::TCRETURNdi8 || 1578 RetOpcode == PPC::TCRETURNai8; 1579 1580 if (UsesTCRet) { 1581 int MaxTCRetDelta = FI->getTailCallSPDelta(); 1582 MachineOperand &StackAdjust = MBBI->getOperand(1); 1583 assert(StackAdjust.isImm() && "Expecting immediate value."); 1584 // Adjust stack pointer. 1585 int StackAdj = StackAdjust.getImm(); 1586 int Delta = StackAdj - MaxTCRetDelta; 1587 assert((Delta >= 0) && "Delta must be positive"); 1588 if (MaxTCRetDelta>0) 1589 FrameSize += (StackAdj +Delta); 1590 else 1591 FrameSize += StackAdj; 1592 } 1593 1594 if (FrameSize) { 1595 // The loaded (or persistent) stack pointer value is offset by the 'stwu' 1596 // on entry to the function. Add this offset back now. 1597 if (!isPPC64) { 1598 // If this function contained a fastcc call and GuaranteedTailCallOpt is 1599 // enabled (=> hasFastCall()==true) the fastcc call might contain a tail 1600 // call which invalidates the stack pointer value in SP(0). So we use the 1601 // value of R31 in this case. 1602 if (FI->hasFastCall() && isInt<16>(FrameSize)) { 1603 assert(hasFP(MF) && "Expecting a valid the frame pointer."); 1604 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1) 1605 .addReg(PPC::R31).addImm(FrameSize); 1606 } else if(FI->hasFastCall()) { 1607 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0) 1608 .addImm(FrameSize >> 16); 1609 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0) 1610 .addReg(PPC::R0, RegState::Kill) 1611 .addImm(FrameSize & 0xFFFF); 1612 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD4)) 1613 .addReg(PPC::R1) 1614 .addReg(PPC::R31) 1615 .addReg(PPC::R0); 1616 } else if (isInt<16>(FrameSize) && 1617 (!ALIGN_STACK || TargetAlign >= MaxAlign) && 1618 !MFI->hasVarSizedObjects()) { 1619 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1) 1620 .addReg(PPC::R1).addImm(FrameSize); 1621 } else { 1622 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ),PPC::R1) 1623 .addImm(0).addReg(PPC::R1); 1624 } 1625 } else { 1626 if (FI->hasFastCall() && isInt<16>(FrameSize)) { 1627 assert(hasFP(MF) && "Expecting a valid the frame pointer."); 1628 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1) 1629 .addReg(PPC::X31).addImm(FrameSize); 1630 } else if(FI->hasFastCall()) { 1631 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0) 1632 .addImm(FrameSize >> 16); 1633 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0) 1634 .addReg(PPC::X0, RegState::Kill) 1635 .addImm(FrameSize & 0xFFFF); 1636 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD8)) 1637 .addReg(PPC::X1) 1638 .addReg(PPC::X31) 1639 .addReg(PPC::X0); 1640 } else if (isInt<16>(FrameSize) && TargetAlign >= MaxAlign && 1641 !MFI->hasVarSizedObjects()) { 1642 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1) 1643 .addReg(PPC::X1).addImm(FrameSize); 1644 } else { 1645 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X1) 1646 .addImm(0).addReg(PPC::X1); 1647 } 1648 } 1649 } 1650 1651 if (isPPC64) { 1652 if (MustSaveLR) 1653 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X0) 1654 .addImm(LROffset/4).addReg(PPC::X1); 1655 1656 if (HasFP) 1657 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X31) 1658 .addImm(FPOffset/4).addReg(PPC::X1); 1659 1660 if (MustSaveLR) 1661 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR8)).addReg(PPC::X0); 1662 } else { 1663 if (MustSaveLR) 1664 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R0) 1665 .addImm(LROffset).addReg(PPC::R1); 1666 1667 if (HasFP) 1668 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R31) 1669 .addImm(FPOffset).addReg(PPC::R1); 1670 1671 if (MustSaveLR) 1672 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR)).addReg(PPC::R0); 1673 } 1674 1675 // Callee pop calling convention. Pop parameter/linkage area. Used for tail 1676 // call optimization 1677 if (GuaranteedTailCallOpt && RetOpcode == PPC::BLR && 1678 MF.getFunction()->getCallingConv() == CallingConv::Fast) { 1679 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1680 unsigned CallerAllocatedAmt = FI->getMinReservedArea(); 1681 unsigned StackReg = isPPC64 ? PPC::X1 : PPC::R1; 1682 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31; 1683 unsigned TmpReg = isPPC64 ? PPC::X0 : PPC::R0; 1684 unsigned ADDIInstr = isPPC64 ? PPC::ADDI8 : PPC::ADDI; 1685 unsigned ADDInstr = isPPC64 ? PPC::ADD8 : PPC::ADD4; 1686 unsigned LISInstr = isPPC64 ? PPC::LIS8 : PPC::LIS; 1687 unsigned ORIInstr = isPPC64 ? PPC::ORI8 : PPC::ORI; 1688 1689 if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) { 1690 BuildMI(MBB, MBBI, dl, TII.get(ADDIInstr), StackReg) 1691 .addReg(StackReg).addImm(CallerAllocatedAmt); 1692 } else { 1693 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) 1694 .addImm(CallerAllocatedAmt >> 16); 1695 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) 1696 .addReg(TmpReg, RegState::Kill) 1697 .addImm(CallerAllocatedAmt & 0xFFFF); 1698 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr)) 1699 .addReg(StackReg) 1700 .addReg(FPReg) 1701 .addReg(TmpReg); 1702 } 1703 } else if (RetOpcode == PPC::TCRETURNdi) { 1704 MBBI = prior(MBB.end()); 1705 MachineOperand &JumpTarget = MBBI->getOperand(0); 1706 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)). 1707 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); 1708 } else if (RetOpcode == PPC::TCRETURNri) { 1709 MBBI = prior(MBB.end()); 1710 assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); 1711 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR)); 1712 } else if (RetOpcode == PPC::TCRETURNai) { 1713 MBBI = prior(MBB.end()); 1714 MachineOperand &JumpTarget = MBBI->getOperand(0); 1715 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm()); 1716 } else if (RetOpcode == PPC::TCRETURNdi8) { 1717 MBBI = prior(MBB.end()); 1718 MachineOperand &JumpTarget = MBBI->getOperand(0); 1719 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)). 1720 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); 1721 } else if (RetOpcode == PPC::TCRETURNri8) { 1722 MBBI = prior(MBB.end()); 1723 assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); 1724 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8)); 1725 } else if (RetOpcode == PPC::TCRETURNai8) { 1726 MBBI = prior(MBB.end()); 1727 MachineOperand &JumpTarget = MBBI->getOperand(0); 1728 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm()); 1729 } 1730 } 1731 1732 unsigned PPCRegisterInfo::getRARegister() const { 1733 return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8; 1734 } 1735 1736 unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 1737 if (!Subtarget.isPPC64()) 1738 return hasFP(MF) ? PPC::R31 : PPC::R1; 1739 else 1740 return hasFP(MF) ? PPC::X31 : PPC::X1; 1741 } 1742 1743 void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) 1744 const { 1745 // Initial state of the frame pointer is R1. 1746 MachineLocation Dst(MachineLocation::VirtualFP); 1747 MachineLocation Src(PPC::R1, 0); 1748 Moves.push_back(MachineMove(0, Dst, Src)); 1749 } 1750 1751 unsigned PPCRegisterInfo::getEHExceptionRegister() const { 1752 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3; 1753 } 1754 1755 unsigned PPCRegisterInfo::getEHHandlerRegister() const { 1756 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4; 1757 } 1758 1759 int PPCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { 1760 // FIXME: Most probably dwarf numbers differs for Linux and Darwin 1761 return PPCGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); 1762 } 1763 1764 #include "PPCGenRegisterInfo.inc" 1765 1766