1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file was developed by the LLVM research group and is distributed under 6 // the University of Illinois Open Source License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the MRegisterInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #define DEBUG_TYPE "reginfo" 15 #include "PPC.h" 16 #include "PPCInstrBuilder.h" 17 #include "PPCRegisterInfo.h" 18 #include "llvm/Constants.h" 19 #include "llvm/Type.h" 20 #include "llvm/CodeGen/ValueTypes.h" 21 #include "llvm/CodeGen/MachineInstrBuilder.h" 22 #include "llvm/CodeGen/MachineFunction.h" 23 #include "llvm/CodeGen/MachineFrameInfo.h" 24 #include "llvm/CodeGen/MachineLocation.h" 25 #include "llvm/Target/TargetFrameInfo.h" 26 #include "llvm/Target/TargetMachine.h" 27 #include "llvm/Target/TargetOptions.h" 28 #include "llvm/Support/CommandLine.h" 29 #include "llvm/Support/Debug.h" 30 #include "llvm/Support/MathExtras.h" 31 #include "llvm/ADT/STLExtras.h" 32 #include <cstdlib> 33 #include <iostream> 34 using namespace llvm; 35 36 PPCRegisterInfo::PPCRegisterInfo() 37 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP) { 38 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 39 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 40 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 41 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 42 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 43 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 44 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 45 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 46 } 47 48 void 49 PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 50 MachineBasicBlock::iterator MI, 51 unsigned SrcReg, int FrameIdx, 52 const TargetRegisterClass *RC) const { 53 if (SrcReg == PPC::LR) { 54 // FIXME: this spills LR immediately to memory in one step. To do this, we 55 // use R11, which we know cannot be used in the prolog/epilog. This is a 56 // hack. 57 BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11); 58 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx); 59 } else if (RC == PPC::CRRCRegisterClass) { 60 BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R11); 61 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx); 62 } else if (RC == PPC::GPRCRegisterClass) { 63 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(SrcReg),FrameIdx); 64 } else if (RC == PPC::G8RCRegisterClass) { 65 addFrameReference(BuildMI(MBB, MI, PPC::STD, 3).addReg(SrcReg),FrameIdx); 66 } else if (RC == PPC::F8RCRegisterClass) { 67 addFrameReference(BuildMI(MBB, MI, PPC::STFD, 3).addReg(SrcReg),FrameIdx); 68 } else if (RC == PPC::F4RCRegisterClass) { 69 addFrameReference(BuildMI(MBB, MI, PPC::STFS, 3).addReg(SrcReg),FrameIdx); 70 } else if (RC == PPC::VRRCRegisterClass) { 71 // We don't have indexed addressing for vector loads. Emit: 72 // R11 = ADDI FI# 73 // Dest = LVX R0, R11 74 // 75 // FIXME: We use R0 here, because it isn't available for RA. 76 addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0); 77 BuildMI(MBB, MI, PPC::STVX, 3) 78 .addReg(SrcReg).addReg(PPC::R0).addReg(PPC::R0); 79 } else { 80 assert(0 && "Unknown regclass!"); 81 abort(); 82 } 83 } 84 85 void 86 PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 87 MachineBasicBlock::iterator MI, 88 unsigned DestReg, int FrameIdx, 89 const TargetRegisterClass *RC) const { 90 if (DestReg == PPC::LR) { 91 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx); 92 BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11); 93 } else if (RC == PPC::CRRCRegisterClass) { 94 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx); 95 BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R11); 96 } else if (RC == PPC::GPRCRegisterClass) { 97 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, DestReg), FrameIdx); 98 } else if (RC == PPC::G8RCRegisterClass) { 99 addFrameReference(BuildMI(MBB, MI, PPC::LD, 2, DestReg), FrameIdx); 100 } else if (RC == PPC::F8RCRegisterClass) { 101 addFrameReference(BuildMI(MBB, MI, PPC::LFD, 2, DestReg), FrameIdx); 102 } else if (RC == PPC::F4RCRegisterClass) { 103 addFrameReference(BuildMI(MBB, MI, PPC::LFS, 2, DestReg), FrameIdx); 104 } else if (RC == PPC::VRRCRegisterClass) { 105 // We don't have indexed addressing for vector loads. Emit: 106 // R11 = ADDI FI# 107 // Dest = LVX R0, R11 108 // 109 // FIXME: We use R0 here, because it isn't available for RA. 110 addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0); 111 BuildMI(MBB, MI, PPC::LVX, 2, DestReg).addReg(PPC::R0).addReg(PPC::R0); 112 } else { 113 assert(0 && "Unknown regclass!"); 114 abort(); 115 } 116 } 117 118 void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, 119 MachineBasicBlock::iterator MI, 120 unsigned DestReg, unsigned SrcReg, 121 const TargetRegisterClass *RC) const { 122 if (RC == PPC::GPRCRegisterClass) { 123 BuildMI(MBB, MI, PPC::OR4, 2, DestReg).addReg(SrcReg).addReg(SrcReg); 124 } else if (RC == PPC::G8RCRegisterClass) { 125 BuildMI(MBB, MI, PPC::OR8, 2, DestReg).addReg(SrcReg).addReg(SrcReg); 126 } else if (RC == PPC::F4RCRegisterClass) { 127 BuildMI(MBB, MI, PPC::FMRS, 1, DestReg).addReg(SrcReg); 128 } else if (RC == PPC::F8RCRegisterClass) { 129 BuildMI(MBB, MI, PPC::FMRD, 1, DestReg).addReg(SrcReg); 130 } else if (RC == PPC::CRRCRegisterClass) { 131 BuildMI(MBB, MI, PPC::MCRF, 1, DestReg).addReg(SrcReg); 132 } else if (RC == PPC::VRRCRegisterClass) { 133 BuildMI(MBB, MI, PPC::VOR, 2, DestReg).addReg(SrcReg).addReg(SrcReg); 134 } else { 135 std::cerr << "Attempt to copy register that is not GPR or FPR"; 136 abort(); 137 } 138 } 139 140 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into 141 /// copy instructions, turning them into load/store instructions. 142 MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI, 143 unsigned OpNum, 144 int FrameIndex) const { 145 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because 146 // it takes more than one instruction to store it. 147 unsigned Opc = MI->getOpcode(); 148 149 if ((Opc == PPC::OR4 && 150 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { 151 if (OpNum == 0) { // move -> store 152 unsigned InReg = MI->getOperand(1).getReg(); 153 return addFrameReference(BuildMI(PPC::STW, 154 3).addReg(InReg), FrameIndex); 155 } else { // move -> load 156 unsigned OutReg = MI->getOperand(0).getReg(); 157 return addFrameReference(BuildMI(PPC::LWZ, 2, OutReg), FrameIndex); 158 } 159 } else if ((Opc == PPC::OR8 && 160 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { 161 if (OpNum == 0) { // move -> store 162 unsigned InReg = MI->getOperand(1).getReg(); 163 return addFrameReference(BuildMI(PPC::STD, 164 3).addReg(InReg), FrameIndex); 165 } else { // move -> load 166 unsigned OutReg = MI->getOperand(0).getReg(); 167 return addFrameReference(BuildMI(PPC::LD, 2, OutReg), FrameIndex); 168 } 169 } else if (Opc == PPC::FMRD) { 170 if (OpNum == 0) { // move -> store 171 unsigned InReg = MI->getOperand(1).getReg(); 172 return addFrameReference(BuildMI(PPC::STFD, 173 3).addReg(InReg), FrameIndex); 174 } else { // move -> load 175 unsigned OutReg = MI->getOperand(0).getReg(); 176 return addFrameReference(BuildMI(PPC::LFD, 2, OutReg), FrameIndex); 177 } 178 } else if (Opc == PPC::FMRS) { 179 if (OpNum == 0) { // move -> store 180 unsigned InReg = MI->getOperand(1).getReg(); 181 return addFrameReference(BuildMI(PPC::STFS, 182 3).addReg(InReg), FrameIndex); 183 } else { // move -> load 184 unsigned OutReg = MI->getOperand(0).getReg(); 185 return addFrameReference(BuildMI(PPC::LFS, 2, OutReg), FrameIndex); 186 } 187 } 188 return 0; 189 } 190 191 //===----------------------------------------------------------------------===// 192 // Stack Frame Processing methods 193 //===----------------------------------------------------------------------===// 194 195 // hasFP - Return true if the specified function should have a dedicated frame 196 // pointer register. This is true if the function has variable sized allocas or 197 // if frame pointer elimination is disabled. 198 // 199 static bool hasFP(MachineFunction &MF) { 200 return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects(); 201 } 202 203 void PPCRegisterInfo:: 204 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 205 MachineBasicBlock::iterator I) const { 206 if (hasFP(MF)) { 207 // If we have a frame pointer, convert as follows: 208 // ADJCALLSTACKDOWN -> addi, r1, r1, -amount 209 // ADJCALLSTACKUP -> addi, r1, r1, amount 210 MachineInstr *Old = I; 211 unsigned Amount = Old->getOperand(0).getImmedValue(); 212 if (Amount != 0) { 213 // We need to keep the stack aligned properly. To do this, we round the 214 // amount of space needed for the outgoing arguments up to the next 215 // alignment boundary. 216 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 217 Amount = (Amount+Align-1)/Align*Align; 218 219 // Replace the pseudo instruction with a new instruction... 220 if (Old->getOpcode() == PPC::ADJCALLSTACKDOWN) { 221 BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addSImm(-Amount); 222 } else { 223 assert(Old->getOpcode() == PPC::ADJCALLSTACKUP); 224 BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addSImm(Amount); 225 } 226 } 227 } 228 MBB.erase(I); 229 } 230 231 void 232 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { 233 unsigned i = 0; 234 MachineInstr &MI = *II; 235 MachineBasicBlock &MBB = *MI.getParent(); 236 MachineFunction &MF = *MBB.getParent(); 237 238 while (!MI.getOperand(i).isFrameIndex()) { 239 ++i; 240 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 241 } 242 243 int FrameIndex = MI.getOperand(i).getFrameIndex(); 244 245 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 246 MI.SetMachineOperandReg(i, hasFP(MF) ? PPC::R31 : PPC::R1); 247 248 // Take into account whether it's an add or mem instruction 249 unsigned OffIdx = (i == 2) ? 1 : 2; 250 251 // Now add the frame object offset to the offset from r1. 252 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + 253 MI.getOperand(OffIdx).getImmedValue(); 254 255 // If we're not using a Frame Pointer that has been set to the value of the 256 // SP before having the stack size subtracted from it, then add the stack size 257 // to Offset to get the correct offset. 258 Offset += MF.getFrameInfo()->getStackSize(); 259 260 if (Offset > 32767 || Offset < -32768) { 261 // Insert a set of r0 with the full offset value before the ld, st, or add 262 MachineBasicBlock *MBB = MI.getParent(); 263 BuildMI(*MBB, II, PPC::LIS, 1, PPC::R0).addSImm(Offset >> 16); 264 BuildMI(*MBB, II, PPC::ORI, 2, PPC::R0).addReg(PPC::R0).addImm(Offset); 265 266 // convert into indexed form of the instruction 267 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 268 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 269 assert(ImmToIdxMap.count(MI.getOpcode()) && 270 "No indexed form of load or store available!"); 271 unsigned NewOpcode = ImmToIdxMap.find(MI.getOpcode())->second; 272 MI.setOpcode(NewOpcode); 273 MI.SetMachineOperandReg(1, MI.getOperand(i).getReg()); 274 MI.SetMachineOperandReg(2, PPC::R0); 275 } else { 276 switch (MI.getOpcode()) { 277 case PPC::LWA: 278 case PPC::LD: 279 case PPC::STD: 280 case PPC::STD_32: 281 assert((Offset & 3) == 0 && "Invalid frame offset!"); 282 Offset >>= 2; // The actual encoded value has the low two bits zero. 283 break; 284 } 285 MI.SetMachineOperandConst(OffIdx, MachineOperand::MO_SignExtendedImmed, 286 Offset); 287 } 288 } 289 290 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the 291 // instruction selector. Based on the vector registers that have been used, 292 // transform this into the appropriate ORI instruction. 293 static void HandleVRSaveUpdate(MachineInstr *MI, const bool *UsedRegs) { 294 unsigned UsedRegMask = 0; 295 #define HANDLEREG(N) if (UsedRegs[PPC::V##N]) UsedRegMask |= 1 << (31-N) 296 HANDLEREG( 0); HANDLEREG( 1); HANDLEREG( 2); HANDLEREG( 3); 297 HANDLEREG( 4); HANDLEREG( 5); HANDLEREG( 6); HANDLEREG( 7); 298 HANDLEREG( 8); HANDLEREG( 9); HANDLEREG(10); HANDLEREG(11); 299 HANDLEREG(12); HANDLEREG(13); HANDLEREG(14); HANDLEREG(15); 300 HANDLEREG(16); HANDLEREG(17); HANDLEREG(18); HANDLEREG(19); 301 HANDLEREG(20); HANDLEREG(21); HANDLEREG(22); HANDLEREG(23); 302 HANDLEREG(24); HANDLEREG(25); HANDLEREG(26); HANDLEREG(27); 303 HANDLEREG(28); HANDLEREG(29); HANDLEREG(30); HANDLEREG(31); 304 #undef HANDLEREG 305 unsigned SrcReg = MI->getOperand(1).getReg(); 306 unsigned DstReg = MI->getOperand(0).getReg(); 307 // If no registers are used, turn this into a copy. 308 if (UsedRegMask == 0) { 309 if (SrcReg != DstReg) 310 BuildMI(*MI->getParent(), MI, PPC::OR4, 2, DstReg) 311 .addReg(SrcReg).addReg(SrcReg); 312 } else if ((UsedRegMask & 0xFFFF) == UsedRegMask) { 313 BuildMI(*MI->getParent(), MI, PPC::ORI, 2, DstReg) 314 .addReg(SrcReg).addImm(UsedRegMask); 315 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { 316 BuildMI(*MI->getParent(), MI, PPC::ORIS, 2, DstReg) 317 .addReg(SrcReg).addImm(UsedRegMask >> 16); 318 } else { 319 BuildMI(*MI->getParent(), MI, PPC::ORIS, 2, DstReg) 320 .addReg(SrcReg).addImm(UsedRegMask >> 16); 321 BuildMI(*MI->getParent(), MI, PPC::ORI, 2, DstReg) 322 .addReg(DstReg).addImm(UsedRegMask & 0xFFFF); 323 } 324 325 // Remove the old UPDATE_VRSAVE instruction. 326 MI->getParent()->erase(MI); 327 } 328 329 330 void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const { 331 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB 332 MachineBasicBlock::iterator MBBI = MBB.begin(); 333 MachineFrameInfo *MFI = MF.getFrameInfo(); 334 335 // Scan the first few instructions of the prolog, looking for an UPDATE_VRSAVE 336 // instruction. If we find it, process it. 337 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { 338 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) { 339 HandleVRSaveUpdate(MBBI, MF.getUsedPhysregs()); 340 break; 341 } 342 } 343 344 // Move MBBI back to the beginning of the function. 345 MBBI = MBB.begin(); 346 347 // Get the number of bytes to allocate from the FrameInfo 348 unsigned NumBytes = MFI->getStackSize(); 349 350 // Get the alignments provided by the target, and the maximum alignment 351 // (if any) of the fixed frame objects. 352 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 353 unsigned MaxAlign = MFI->getMaxAlignment(); 354 355 // If we have calls, we cannot use the red zone to store callee save registers 356 // and we must set up a stack frame, so calculate the necessary size here. 357 if (MFI->hasCalls()) { 358 // We reserve argument space for call sites in the function immediately on 359 // entry to the current function. This eliminates the need for add/sub 360 // brackets around call sites. 361 NumBytes += MFI->getMaxCallFrameSize(); 362 } 363 364 // If we are a leaf function, and use up to 224 bytes of stack space, 365 // and don't have a frame pointer, then we do not need to adjust the stack 366 // pointer (we fit in the Red Zone). 367 if ((NumBytes == 0) || (NumBytes <= 224 && !hasFP(MF) && !MFI->hasCalls() && 368 MaxAlign <= TargetAlign)) { 369 MFI->setStackSize(0); 370 return; 371 } 372 373 // Add the size of R1 to NumBytes size for the store of R1 to the bottom 374 // of the stack and round the size to a multiple of the alignment. 375 unsigned Align = std::max(TargetAlign, MaxAlign); 376 unsigned GPRSize = 4; 377 unsigned Size = hasFP(MF) ? GPRSize + GPRSize : GPRSize; 378 NumBytes = (NumBytes+Size+Align-1)/Align*Align; 379 380 // Update frame info to pretend that this is part of the stack... 381 MFI->setStackSize(NumBytes); 382 383 // Adjust stack pointer: r1 -= numbytes. 384 if (NumBytes <= 32768) { 385 BuildMI(MBB, MBBI, PPC::STWU, 3) 386 .addReg(PPC::R1).addSImm(-NumBytes).addReg(PPC::R1); 387 } else { 388 int NegNumbytes = -NumBytes; 389 BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addSImm(NegNumbytes >> 16); 390 BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0) 391 .addReg(PPC::R0).addImm(NegNumbytes & 0xFFFF); 392 BuildMI(MBB, MBBI, PPC::STWUX, 3) 393 .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0); 394 } 395 396 // If there is a preferred stack alignment, align R1 now 397 // FIXME: If this ever matters, this could be made more efficient by folding 398 // this into the code above, so that we don't issue two store+update 399 // instructions. 400 if (MaxAlign > TargetAlign) { 401 assert(isPowerOf2_32(MaxAlign) && MaxAlign < 32767 && "Invalid alignment!"); 402 BuildMI(MBB, MBBI, PPC::RLWINM, 4, PPC::R0) 403 .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31); 404 BuildMI(MBB, MBBI, PPC::SUBFIC, 2,PPC::R0).addReg(PPC::R0).addImm(MaxAlign); 405 BuildMI(MBB, MBBI, PPC::STWUX, 3) 406 .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0); 407 } 408 409 // If there is a frame pointer, copy R1 (SP) into R31 (FP) 410 if (hasFP(MF)) { 411 BuildMI(MBB, MBBI, PPC::STW, 3) 412 .addReg(PPC::R31).addSImm(GPRSize).addReg(PPC::R1); 413 BuildMI(MBB, MBBI, PPC::OR4, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1); 414 } 415 } 416 417 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF, 418 MachineBasicBlock &MBB) const { 419 MachineBasicBlock::iterator MBBI = prior(MBB.end()); 420 assert(MBBI->getOpcode() == PPC::BLR && 421 "Can only insert epilog into returning blocks"); 422 423 // Get the number of bytes allocated from the FrameInfo. 424 unsigned NumBytes = MF.getFrameInfo()->getStackSize(); 425 unsigned GPRSize = 4; 426 427 if (NumBytes != 0) { 428 // If this function has a frame pointer, load the saved stack pointer from 429 // its stack slot. 430 if (hasFP(MF)) { 431 BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R31) 432 .addSImm(GPRSize).addReg(PPC::R31); 433 } 434 435 // The loaded (or persistent) stack pointer value is offseted by the 'stwu' 436 // on entry to the function. Add this offset back now. 437 if (NumBytes < 32768) { 438 BuildMI(MBB, MBBI, PPC::ADDI, 2, PPC::R1) 439 .addReg(PPC::R1).addSImm(NumBytes); 440 } else { 441 BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addSImm(NumBytes >> 16); 442 BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0) 443 .addReg(PPC::R0).addImm(NumBytes & 0xFFFF); 444 BuildMI(MBB, MBBI, PPC::ADD4, 2, PPC::R1) 445 .addReg(PPC::R0).addReg(PPC::R1); 446 } 447 } 448 } 449 450 unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const { 451 return getDwarfRegNum(hasFP(MF) ? PPC::R31 : PPC::R1); 452 } 453 454 #include "PPCGenRegisterInfo.inc" 455 456