1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the TargetRegisterInfo 11 // class. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #define DEBUG_TYPE "reginfo" 16 #include "PPC.h" 17 #include "PPCInstrBuilder.h" 18 #include "PPCMachineFunctionInfo.h" 19 #include "PPCRegisterInfo.h" 20 #include "PPCFrameLowering.h" 21 #include "PPCSubtarget.h" 22 #include "llvm/CallingConv.h" 23 #include "llvm/Constants.h" 24 #include "llvm/Function.h" 25 #include "llvm/Type.h" 26 #include "llvm/CodeGen/ValueTypes.h" 27 #include "llvm/CodeGen/MachineInstrBuilder.h" 28 #include "llvm/CodeGen/MachineModuleInfo.h" 29 #include "llvm/CodeGen/MachineFunction.h" 30 #include "llvm/CodeGen/MachineFrameInfo.h" 31 #include "llvm/CodeGen/MachineLocation.h" 32 #include "llvm/CodeGen/MachineRegisterInfo.h" 33 #include "llvm/CodeGen/RegisterScavenging.h" 34 #include "llvm/Target/TargetFrameLowering.h" 35 #include "llvm/Target/TargetInstrInfo.h" 36 #include "llvm/Target/TargetMachine.h" 37 #include "llvm/Target/TargetOptions.h" 38 #include "llvm/Support/CommandLine.h" 39 #include "llvm/Support/Debug.h" 40 #include "llvm/Support/ErrorHandling.h" 41 #include "llvm/Support/MathExtras.h" 42 #include "llvm/Support/raw_ostream.h" 43 #include "llvm/ADT/BitVector.h" 44 #include "llvm/ADT/STLExtras.h" 45 #include <cstdlib> 46 47 // FIXME (64-bit): Eventually enable by default. 48 namespace llvm { 49 cl::opt<bool> EnablePPC32RS("enable-ppc32-regscavenger", 50 cl::init(false), 51 cl::desc("Enable PPC32 register scavenger"), 52 cl::Hidden); 53 cl::opt<bool> EnablePPC64RS("enable-ppc64-regscavenger", 54 cl::init(false), 55 cl::desc("Enable PPC64 register scavenger"), 56 cl::Hidden); 57 } 58 59 using namespace llvm; 60 61 // FIXME (64-bit): Should be inlined. 62 bool 63 PPCRegisterInfo::requiresRegisterScavenging(const MachineFunction &) const { 64 return ((EnablePPC32RS && !Subtarget.isPPC64()) || 65 (EnablePPC64RS && Subtarget.isPPC64())); 66 } 67 68 /// getRegisterNumbering - Given the enum value for some register, e.g. 69 /// PPC::F14, return the number that it corresponds to (e.g. 14). 70 unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) { 71 using namespace PPC; 72 switch (RegEnum) { 73 case 0: return 0; 74 case R0 : case X0 : case F0 : case V0 : case CR0: case CR0LT: return 0; 75 case R1 : case X1 : case F1 : case V1 : case CR1: case CR0GT: return 1; 76 case R2 : case X2 : case F2 : case V2 : case CR2: case CR0EQ: return 2; 77 case R3 : case X3 : case F3 : case V3 : case CR3: case CR0UN: return 3; 78 case R4 : case X4 : case F4 : case V4 : case CR4: case CR1LT: return 4; 79 case R5 : case X5 : case F5 : case V5 : case CR5: case CR1GT: return 5; 80 case R6 : case X6 : case F6 : case V6 : case CR6: case CR1EQ: return 6; 81 case R7 : case X7 : case F7 : case V7 : case CR7: case CR1UN: return 7; 82 case R8 : case X8 : case F8 : case V8 : case CR2LT: return 8; 83 case R9 : case X9 : case F9 : case V9 : case CR2GT: return 9; 84 case R10: case X10: case F10: case V10: case CR2EQ: return 10; 85 case R11: case X11: case F11: case V11: case CR2UN: return 11; 86 case R12: case X12: case F12: case V12: case CR3LT: return 12; 87 case R13: case X13: case F13: case V13: case CR3GT: return 13; 88 case R14: case X14: case F14: case V14: case CR3EQ: return 14; 89 case R15: case X15: case F15: case V15: case CR3UN: return 15; 90 case R16: case X16: case F16: case V16: case CR4LT: return 16; 91 case R17: case X17: case F17: case V17: case CR4GT: return 17; 92 case R18: case X18: case F18: case V18: case CR4EQ: return 18; 93 case R19: case X19: case F19: case V19: case CR4UN: return 19; 94 case R20: case X20: case F20: case V20: case CR5LT: return 20; 95 case R21: case X21: case F21: case V21: case CR5GT: return 21; 96 case R22: case X22: case F22: case V22: case CR5EQ: return 22; 97 case R23: case X23: case F23: case V23: case CR5UN: return 23; 98 case R24: case X24: case F24: case V24: case CR6LT: return 24; 99 case R25: case X25: case F25: case V25: case CR6GT: return 25; 100 case R26: case X26: case F26: case V26: case CR6EQ: return 26; 101 case R27: case X27: case F27: case V27: case CR6UN: return 27; 102 case R28: case X28: case F28: case V28: case CR7LT: return 28; 103 case R29: case X29: case F29: case V29: case CR7GT: return 29; 104 case R30: case X30: case F30: case V30: case CR7EQ: return 30; 105 case R31: case X31: case F31: case V31: case CR7UN: return 31; 106 default: 107 llvm_unreachable("Unhandled reg in PPCRegisterInfo::getRegisterNumbering!"); 108 } 109 } 110 111 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST, 112 const TargetInstrInfo &tii) 113 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP), 114 Subtarget(ST), TII(tii) { 115 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 116 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 117 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 118 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 119 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 120 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 121 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 122 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 123 124 // 64-bit 125 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8; 126 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8; 127 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8; 128 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX; 129 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32; 130 } 131 132 /// getPointerRegClass - Return the register class to use to hold pointers. 133 /// This is used for addressing modes. 134 const TargetRegisterClass * 135 PPCRegisterInfo::getPointerRegClass(unsigned Kind) const { 136 if (Subtarget.isPPC64()) 137 return &PPC::G8RCRegClass; 138 return &PPC::GPRCRegClass; 139 } 140 141 const unsigned* 142 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 143 // 32-bit Darwin calling convention. 144 static const unsigned Darwin32_CalleeSavedRegs[] = { 145 PPC::R13, PPC::R14, PPC::R15, 146 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 147 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 148 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 149 PPC::R28, PPC::R29, PPC::R30, PPC::R31, 150 151 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 152 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 153 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 154 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 155 PPC::F30, PPC::F31, 156 157 PPC::CR2, PPC::CR3, PPC::CR4, 158 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 159 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 160 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 161 162 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 163 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 164 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 165 166 PPC::LR, 0 167 }; 168 169 // 32-bit SVR4 calling convention. 170 static const unsigned SVR4_CalleeSavedRegs[] = { 171 PPC::R14, PPC::R15, 172 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 173 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 174 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 175 PPC::R28, PPC::R29, PPC::R30, PPC::R31, 176 177 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 178 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 179 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 180 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 181 PPC::F30, PPC::F31, 182 183 PPC::CR2, PPC::CR3, PPC::CR4, 184 185 PPC::VRSAVE, 186 187 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 188 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 189 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 190 191 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 192 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 193 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 194 195 0 196 }; 197 // 64-bit Darwin calling convention. 198 static const unsigned Darwin64_CalleeSavedRegs[] = { 199 PPC::X14, PPC::X15, 200 PPC::X16, PPC::X17, PPC::X18, PPC::X19, 201 PPC::X20, PPC::X21, PPC::X22, PPC::X23, 202 PPC::X24, PPC::X25, PPC::X26, PPC::X27, 203 PPC::X28, PPC::X29, PPC::X30, PPC::X31, 204 205 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 206 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 207 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 208 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 209 PPC::F30, PPC::F31, 210 211 PPC::CR2, PPC::CR3, PPC::CR4, 212 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 213 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 214 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 215 216 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 217 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 218 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 219 220 PPC::LR8, 0 221 }; 222 223 // 64-bit SVR4 calling convention. 224 static const unsigned SVR4_64_CalleeSavedRegs[] = { 225 PPC::X14, PPC::X15, 226 PPC::X16, PPC::X17, PPC::X18, PPC::X19, 227 PPC::X20, PPC::X21, PPC::X22, PPC::X23, 228 PPC::X24, PPC::X25, PPC::X26, PPC::X27, 229 PPC::X28, PPC::X29, PPC::X30, PPC::X31, 230 231 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 232 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 233 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 234 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 235 PPC::F30, PPC::F31, 236 237 PPC::CR2, PPC::CR3, PPC::CR4, 238 239 PPC::VRSAVE, 240 241 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 242 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 243 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 244 245 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 246 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 247 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 248 249 0 250 }; 251 252 if (Subtarget.isDarwinABI()) 253 return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegs : 254 Darwin32_CalleeSavedRegs; 255 256 return Subtarget.isPPC64() ? SVR4_64_CalleeSavedRegs : SVR4_CalleeSavedRegs; 257 } 258 259 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 260 BitVector Reserved(getNumRegs()); 261 const PPCFrameLowering *PPCFI = 262 static_cast<const PPCFrameLowering*>(MF.getTarget().getFrameLowering()); 263 264 Reserved.set(PPC::R0); 265 Reserved.set(PPC::R1); 266 Reserved.set(PPC::LR); 267 Reserved.set(PPC::LR8); 268 Reserved.set(PPC::RM); 269 270 // The SVR4 ABI reserves r2 and r13 271 if (Subtarget.isSVR4ABI()) { 272 Reserved.set(PPC::R2); // System-reserved register 273 Reserved.set(PPC::R13); // Small Data Area pointer register 274 } 275 // Reserve R2 on Darwin to hack around the problem of save/restore of CR 276 // when the stack frame is too big to address directly; we need two regs. 277 // This is a hack. 278 if (Subtarget.isDarwinABI()) { 279 Reserved.set(PPC::R2); 280 } 281 282 // On PPC64, r13 is the thread pointer. Never allocate this register. 283 // Note that this is over conservative, as it also prevents allocation of R31 284 // when the FP is not needed. 285 if (Subtarget.isPPC64()) { 286 Reserved.set(PPC::R13); 287 Reserved.set(PPC::R31); 288 289 if (!requiresRegisterScavenging(MF)) 290 Reserved.set(PPC::R0); // FIXME (64-bit): Remove 291 292 Reserved.set(PPC::X0); 293 Reserved.set(PPC::X1); 294 Reserved.set(PPC::X13); 295 Reserved.set(PPC::X31); 296 297 // The 64-bit SVR4 ABI reserves r2 for the TOC pointer. 298 if (Subtarget.isSVR4ABI()) { 299 Reserved.set(PPC::X2); 300 } 301 // Reserve R2 on Darwin to hack around the problem of save/restore of CR 302 // when the stack frame is too big to address directly; we need two regs. 303 // This is a hack. 304 if (Subtarget.isDarwinABI()) { 305 Reserved.set(PPC::X2); 306 } 307 } 308 309 if (PPCFI->needsFP(MF)) 310 Reserved.set(PPC::R31); 311 312 return Reserved; 313 } 314 315 //===----------------------------------------------------------------------===// 316 // Stack Frame Processing methods 317 //===----------------------------------------------------------------------===// 318 319 void PPCRegisterInfo:: 320 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 321 MachineBasicBlock::iterator I) const { 322 if (GuaranteedTailCallOpt && I->getOpcode() == PPC::ADJCALLSTACKUP) { 323 // Add (actually subtract) back the amount the callee popped on return. 324 if (int CalleeAmt = I->getOperand(1).getImm()) { 325 bool is64Bit = Subtarget.isPPC64(); 326 CalleeAmt *= -1; 327 unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1; 328 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0; 329 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI; 330 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4; 331 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS; 332 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI; 333 MachineInstr *MI = I; 334 DebugLoc dl = MI->getDebugLoc(); 335 336 if (isInt<16>(CalleeAmt)) { 337 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg).addReg(StackReg). 338 addImm(CalleeAmt); 339 } else { 340 MachineBasicBlock::iterator MBBI = I; 341 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) 342 .addImm(CalleeAmt >> 16); 343 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) 344 .addReg(TmpReg, RegState::Kill) 345 .addImm(CalleeAmt & 0xFFFF); 346 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr)) 347 .addReg(StackReg) 348 .addReg(StackReg) 349 .addReg(TmpReg); 350 } 351 } 352 } 353 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions. 354 MBB.erase(I); 355 } 356 357 /// findScratchRegister - Find a 'free' PPC register. Try for a call-clobbered 358 /// register first and then a spilled callee-saved register if that fails. 359 static 360 unsigned findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS, 361 const TargetRegisterClass *RC, int SPAdj) { 362 assert(RS && "Register scavenging must be on"); 363 unsigned Reg = RS->FindUnusedReg(RC); 364 // FIXME: move ARM callee-saved reg scan to target independent code, then 365 // search for already spilled CS register here. 366 if (Reg == 0) 367 Reg = RS->scavengeRegister(RC, II, SPAdj); 368 return Reg; 369 } 370 371 /// lowerDynamicAlloc - Generate the code for allocating an object in the 372 /// current frame. The sequence of code with be in the general form 373 /// 374 /// addi R0, SP, \#frameSize ; get the address of the previous frame 375 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size 376 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation 377 /// 378 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II, 379 int SPAdj, RegScavenger *RS) const { 380 // Get the instruction. 381 MachineInstr &MI = *II; 382 // Get the instruction's basic block. 383 MachineBasicBlock &MBB = *MI.getParent(); 384 // Get the basic block's function. 385 MachineFunction &MF = *MBB.getParent(); 386 // Get the frame info. 387 MachineFrameInfo *MFI = MF.getFrameInfo(); 388 // Determine whether 64-bit pointers are used. 389 bool LP64 = Subtarget.isPPC64(); 390 DebugLoc dl = MI.getDebugLoc(); 391 392 // Get the maximum call stack size. 393 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 394 // Get the total frame size. 395 unsigned FrameSize = MFI->getStackSize(); 396 397 // Get stack alignments. 398 unsigned TargetAlign = MF.getTarget().getFrameLowering()->getStackAlignment(); 399 unsigned MaxAlign = MFI->getMaxAlignment(); 400 if (MaxAlign > TargetAlign) 401 report_fatal_error("Dynamic alloca with large aligns not supported"); 402 403 // Determine the previous frame's address. If FrameSize can't be 404 // represented as 16 bits or we need special alignment, then we load the 405 // previous frame's address from 0(SP). Why not do an addis of the hi? 406 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. 407 // Constructing the constant and adding would take 3 instructions. 408 // Fortunately, a frame greater than 32K is rare. 409 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 410 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 411 const TargetRegisterClass *RC = LP64 ? G8RC : GPRC; 412 413 // FIXME (64-bit): Use "findScratchRegister" 414 unsigned Reg; 415 if (requiresRegisterScavenging(MF)) 416 Reg = findScratchRegister(II, RS, RC, SPAdj); 417 else 418 Reg = PPC::R0; 419 420 if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) { 421 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) 422 .addReg(PPC::R31) 423 .addImm(FrameSize); 424 } else if (LP64) { 425 if (requiresRegisterScavenging(MF)) // FIXME (64-bit): Use "true" part. 426 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg) 427 .addImm(0) 428 .addReg(PPC::X1); 429 else 430 BuildMI(MBB, II, dl, TII.get(PPC::LD), PPC::X0) 431 .addImm(0) 432 .addReg(PPC::X1); 433 } else { 434 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) 435 .addImm(0) 436 .addReg(PPC::R1); 437 } 438 439 // Grow the stack and update the stack pointer link, then determine the 440 // address of new allocated space. 441 if (LP64) { 442 if (requiresRegisterScavenging(MF)) // FIXME (64-bit): Use "true" part. 443 BuildMI(MBB, II, dl, TII.get(PPC::STDUX)) 444 .addReg(Reg, RegState::Kill) 445 .addReg(PPC::X1) 446 .addReg(MI.getOperand(1).getReg()); 447 else 448 BuildMI(MBB, II, dl, TII.get(PPC::STDUX)) 449 .addReg(PPC::X0, RegState::Kill) 450 .addReg(PPC::X1) 451 .addReg(MI.getOperand(1).getReg()); 452 453 if (!MI.getOperand(1).isKill()) 454 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 455 .addReg(PPC::X1) 456 .addImm(maxCallFrameSize); 457 else 458 // Implicitly kill the register. 459 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 460 .addReg(PPC::X1) 461 .addImm(maxCallFrameSize) 462 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill); 463 } else { 464 BuildMI(MBB, II, dl, TII.get(PPC::STWUX)) 465 .addReg(Reg, RegState::Kill) 466 .addReg(PPC::R1) 467 .addReg(MI.getOperand(1).getReg()); 468 469 if (!MI.getOperand(1).isKill()) 470 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 471 .addReg(PPC::R1) 472 .addImm(maxCallFrameSize); 473 else 474 // Implicitly kill the register. 475 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 476 .addReg(PPC::R1) 477 .addImm(maxCallFrameSize) 478 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill); 479 } 480 481 // Discard the DYNALLOC instruction. 482 MBB.erase(II); 483 } 484 485 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of 486 /// reserving a whole register (R0), we scrounge for one here. This generates 487 /// code like this: 488 /// 489 /// mfcr rA ; Move the conditional register into GPR rA. 490 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot. 491 /// stw rA, FI ; Store rA to the frame. 492 /// 493 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, 494 unsigned FrameIndex, int SPAdj, 495 RegScavenger *RS) const { 496 // Get the instruction. 497 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>, <FI> 498 // Get the instruction's basic block. 499 MachineBasicBlock &MBB = *MI.getParent(); 500 DebugLoc dl = MI.getDebugLoc(); 501 502 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 503 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 504 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC; 505 unsigned Reg = findScratchRegister(II, RS, RC, SPAdj); 506 unsigned SrcReg = MI.getOperand(0).getReg(); 507 bool LP64 = Subtarget.isPPC64(); 508 509 // We need to store the CR in the low 4-bits of the saved value. First, issue 510 // an MFCRpsued to save all of the CRBits and, if needed, kill the SrcReg. 511 BuildMI(MBB, II, dl, TII.get(PPC::MFCRpseud), Reg) 512 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 513 514 // If the saved register wasn't CR0, shift the bits left so that they are in 515 // CR0's slot. 516 if (SrcReg != PPC::CR0) 517 // rlwinm rA, rA, ShiftBits, 0, 31. 518 BuildMI(MBB, II, dl, TII.get(PPC::RLWINM), Reg) 519 .addReg(Reg, RegState::Kill) 520 .addImm(PPCRegisterInfo::getRegisterNumbering(SrcReg) * 4) 521 .addImm(0) 522 .addImm(31); 523 524 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW)) 525 .addReg(Reg, getKillRegState(MI.getOperand(1).getImm())), 526 FrameIndex); 527 528 // Discard the pseudo instruction. 529 MBB.erase(II); 530 } 531 532 void 533 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 534 int SPAdj, RegScavenger *RS) const { 535 assert(SPAdj == 0 && "Unexpected"); 536 537 // Get the instruction. 538 MachineInstr &MI = *II; 539 // Get the instruction's basic block. 540 MachineBasicBlock &MBB = *MI.getParent(); 541 // Get the basic block's function. 542 MachineFunction &MF = *MBB.getParent(); 543 // Get the frame info. 544 MachineFrameInfo *MFI = MF.getFrameInfo(); 545 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 546 DebugLoc dl = MI.getDebugLoc(); 547 548 // Find out which operand is the frame index. 549 unsigned FIOperandNo = 0; 550 while (!MI.getOperand(FIOperandNo).isFI()) { 551 ++FIOperandNo; 552 assert(FIOperandNo != MI.getNumOperands() && 553 "Instr doesn't have FrameIndex operand!"); 554 } 555 // Take into account whether it's an add or mem instruction 556 unsigned OffsetOperandNo = (FIOperandNo == 2) ? 1 : 2; 557 if (MI.isInlineAsm()) 558 OffsetOperandNo = FIOperandNo-1; 559 560 // Get the frame index. 561 int FrameIndex = MI.getOperand(FIOperandNo).getIndex(); 562 563 // Get the frame pointer save index. Users of this index are primarily 564 // DYNALLOC instructions. 565 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 566 int FPSI = FI->getFramePointerSaveIndex(); 567 // Get the instruction opcode. 568 unsigned OpC = MI.getOpcode(); 569 570 // Special case for dynamic alloca. 571 if (FPSI && FrameIndex == FPSI && 572 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { 573 lowerDynamicAlloc(II, SPAdj, RS); 574 return; 575 } 576 577 // Special case for pseudo-op SPILL_CR. 578 if (requiresRegisterScavenging(MF)) // FIXME (64-bit): Enable by default. 579 if (OpC == PPC::SPILL_CR) { 580 lowerCRSpilling(II, FrameIndex, SPAdj, RS); 581 return; 582 } 583 584 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 585 MI.getOperand(FIOperandNo).ChangeToRegister(TFI->hasFP(MF) ? 586 PPC::R31 : PPC::R1, 587 false); 588 589 // Figure out if the offset in the instruction is shifted right two bits. This 590 // is true for instructions like "STD", which the machine implicitly adds two 591 // low zeros to. 592 bool isIXAddr = false; 593 switch (OpC) { 594 case PPC::LWA: 595 case PPC::LD: 596 case PPC::STD: 597 case PPC::STD_32: 598 isIXAddr = true; 599 break; 600 } 601 602 // Now add the frame object offset to the offset from r1. 603 int Offset = MFI->getObjectOffset(FrameIndex); 604 if (!isIXAddr) 605 Offset += MI.getOperand(OffsetOperandNo).getImm(); 606 else 607 Offset += MI.getOperand(OffsetOperandNo).getImm() << 2; 608 609 // If we're not using a Frame Pointer that has been set to the value of the 610 // SP before having the stack size subtracted from it, then add the stack size 611 // to Offset to get the correct offset. 612 // Naked functions have stack size 0, although getStackSize may not reflect that 613 // because we didn't call all the pieces that compute it for naked functions. 614 if (!MF.getFunction()->hasFnAttr(Attribute::Naked)) 615 Offset += MFI->getStackSize(); 616 617 // If we can, encode the offset directly into the instruction. If this is a 618 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If 619 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits 620 // clear can be encoded. This is extremely uncommon, because normally you 621 // only "std" to a stack slot that is at least 4-byte aligned, but it can 622 // happen in invalid code. 623 if (isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0)) { 624 if (isIXAddr) 625 Offset >>= 2; // The actual encoded value has the low two bits zero. 626 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 627 return; 628 } 629 630 // The offset doesn't fit into a single register, scavenge one to build the 631 // offset in. 632 // FIXME: figure out what SPAdj is doing here. 633 634 // FIXME (64-bit): Use "findScratchRegister". 635 unsigned SReg; 636 if (requiresRegisterScavenging(MF)) 637 SReg = findScratchRegister(II, RS, &PPC::GPRCRegClass, SPAdj); 638 else 639 SReg = PPC::R0; 640 641 // Insert a set of rA with the full offset value before the ld, st, or add 642 BuildMI(MBB, II, dl, TII.get(PPC::LIS), SReg) 643 .addImm(Offset >> 16); 644 BuildMI(MBB, II, dl, TII.get(PPC::ORI), SReg) 645 .addReg(SReg, RegState::Kill) 646 .addImm(Offset); 647 648 // Convert into indexed form of the instruction: 649 // 650 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 651 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 652 unsigned OperandBase; 653 654 if (OpC != TargetOpcode::INLINEASM) { 655 assert(ImmToIdxMap.count(OpC) && 656 "No indexed form of load or store available!"); 657 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; 658 MI.setDesc(TII.get(NewOpcode)); 659 OperandBase = 1; 660 } else { 661 OperandBase = OffsetOperandNo; 662 } 663 664 unsigned StackReg = MI.getOperand(FIOperandNo).getReg(); 665 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false); 666 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false); 667 } 668 669 unsigned PPCRegisterInfo::getRARegister() const { 670 return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8; 671 } 672 673 unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 674 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 675 676 if (!Subtarget.isPPC64()) 677 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1; 678 else 679 return TFI->hasFP(MF) ? PPC::X31 : PPC::X1; 680 } 681 682 unsigned PPCRegisterInfo::getEHExceptionRegister() const { 683 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3; 684 } 685 686 unsigned PPCRegisterInfo::getEHHandlerRegister() const { 687 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4; 688 } 689 690 /// DWARFFlavour - Flavour of dwarf regnumbers 691 /// 692 namespace DWARFFlavour { 693 enum { 694 PPC64 = 0, PPC32 = 1 695 }; 696 } 697 698 int PPCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { 699 // FIXME: Most probably dwarf numbers differs for Linux and Darwin 700 unsigned Flavour = Subtarget.isPPC64() ? 701 DWARFFlavour::PPC64 : DWARFFlavour::PPC32; 702 703 return PPCGenRegisterInfo::getDwarfRegNumFull(RegNum, Flavour); 704 } 705 706 int PPCRegisterInfo::getLLVMRegNum(unsigned RegNum, bool isEH) const { 707 // FIXME: Most probably dwarf numbers differs for Linux and Darwin 708 unsigned Flavour = Subtarget.isPPC64() ? 709 DWARFFlavour::PPC64 : DWARFFlavour::PPC32; 710 711 return PPCGenRegisterInfo::getLLVMRegNumFull(RegNum, Flavour); 712 } 713 714 #include "PPCGenRegisterInfo.inc" 715