1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the TargetRegisterInfo 11 // class. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #define DEBUG_TYPE "reginfo" 16 #include "PPC.h" 17 #include "PPCInstrBuilder.h" 18 #include "PPCMachineFunctionInfo.h" 19 #include "PPCRegisterInfo.h" 20 #include "PPCFrameInfo.h" 21 #include "PPCSubtarget.h" 22 #include "llvm/CallingConv.h" 23 #include "llvm/Constants.h" 24 #include "llvm/Function.h" 25 #include "llvm/Type.h" 26 #include "llvm/CodeGen/ValueTypes.h" 27 #include "llvm/CodeGen/MachineInstrBuilder.h" 28 #include "llvm/CodeGen/MachineModuleInfo.h" 29 #include "llvm/CodeGen/MachineFunction.h" 30 #include "llvm/CodeGen/MachineFrameInfo.h" 31 #include "llvm/CodeGen/MachineLocation.h" 32 #include "llvm/CodeGen/MachineRegisterInfo.h" 33 #include "llvm/CodeGen/RegisterScavenging.h" 34 #include "llvm/Target/TargetFrameInfo.h" 35 #include "llvm/Target/TargetInstrInfo.h" 36 #include "llvm/Target/TargetMachine.h" 37 #include "llvm/Target/TargetOptions.h" 38 #include "llvm/Support/CommandLine.h" 39 #include "llvm/Support/Debug.h" 40 #include "llvm/Support/ErrorHandling.h" 41 #include "llvm/Support/MathExtras.h" 42 #include "llvm/Support/raw_ostream.h" 43 #include "llvm/ADT/BitVector.h" 44 #include "llvm/ADT/STLExtras.h" 45 #include <cstdlib> 46 47 // FIXME This disables some code that aligns the stack to a boundary 48 // bigger than the default (16 bytes on Darwin) when there is a stack local 49 // of greater alignment. This does not currently work, because the delta 50 // between old and new stack pointers is added to offsets that reference 51 // incoming parameters after the prolog is generated, and the code that 52 // does that doesn't handle a variable delta. You don't want to do that 53 // anyway; a better approach is to reserve another register that retains 54 // to the incoming stack pointer, and reference parameters relative to that. 55 #define ALIGN_STACK 0 56 57 // FIXME (64-bit): Eventually enable by default. 58 namespace llvm { 59 cl::opt<bool> EnablePPC32RS("enable-ppc32-regscavenger", 60 cl::init(false), 61 cl::desc("Enable PPC32 register scavenger"), 62 cl::Hidden); 63 cl::opt<bool> EnablePPC64RS("enable-ppc64-regscavenger", 64 cl::init(false), 65 cl::desc("Enable PPC64 register scavenger"), 66 cl::Hidden); 67 } 68 69 using namespace llvm; 70 71 #define EnableRegisterScavenging \ 72 ((EnablePPC32RS && !Subtarget.isPPC64()) || \ 73 (EnablePPC64RS && Subtarget.isPPC64())) 74 75 // FIXME (64-bit): Should be inlined. 76 bool 77 PPCRegisterInfo::requiresRegisterScavenging(const MachineFunction &) const { 78 return EnableRegisterScavenging; 79 } 80 81 /// getRegisterNumbering - Given the enum value for some register, e.g. 82 /// PPC::F14, return the number that it corresponds to (e.g. 14). 83 unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) { 84 using namespace PPC; 85 switch (RegEnum) { 86 case 0: return 0; 87 case R0 : case X0 : case F0 : case V0 : case CR0: case CR0LT: return 0; 88 case R1 : case X1 : case F1 : case V1 : case CR1: case CR0GT: return 1; 89 case R2 : case X2 : case F2 : case V2 : case CR2: case CR0EQ: return 2; 90 case R3 : case X3 : case F3 : case V3 : case CR3: case CR0UN: return 3; 91 case R4 : case X4 : case F4 : case V4 : case CR4: case CR1LT: return 4; 92 case R5 : case X5 : case F5 : case V5 : case CR5: case CR1GT: return 5; 93 case R6 : case X6 : case F6 : case V6 : case CR6: case CR1EQ: return 6; 94 case R7 : case X7 : case F7 : case V7 : case CR7: case CR1UN: return 7; 95 case R8 : case X8 : case F8 : case V8 : case CR2LT: return 8; 96 case R9 : case X9 : case F9 : case V9 : case CR2GT: return 9; 97 case R10: case X10: case F10: case V10: case CR2EQ: return 10; 98 case R11: case X11: case F11: case V11: case CR2UN: return 11; 99 case R12: case X12: case F12: case V12: case CR3LT: return 12; 100 case R13: case X13: case F13: case V13: case CR3GT: return 13; 101 case R14: case X14: case F14: case V14: case CR3EQ: return 14; 102 case R15: case X15: case F15: case V15: case CR3UN: return 15; 103 case R16: case X16: case F16: case V16: case CR4LT: return 16; 104 case R17: case X17: case F17: case V17: case CR4GT: return 17; 105 case R18: case X18: case F18: case V18: case CR4EQ: return 18; 106 case R19: case X19: case F19: case V19: case CR4UN: return 19; 107 case R20: case X20: case F20: case V20: case CR5LT: return 20; 108 case R21: case X21: case F21: case V21: case CR5GT: return 21; 109 case R22: case X22: case F22: case V22: case CR5EQ: return 22; 110 case R23: case X23: case F23: case V23: case CR5UN: return 23; 111 case R24: case X24: case F24: case V24: case CR6LT: return 24; 112 case R25: case X25: case F25: case V25: case CR6GT: return 25; 113 case R26: case X26: case F26: case V26: case CR6EQ: return 26; 114 case R27: case X27: case F27: case V27: case CR6UN: return 27; 115 case R28: case X28: case F28: case V28: case CR7LT: return 28; 116 case R29: case X29: case F29: case V29: case CR7GT: return 29; 117 case R30: case X30: case F30: case V30: case CR7EQ: return 30; 118 case R31: case X31: case F31: case V31: case CR7UN: return 31; 119 default: 120 llvm_unreachable("Unhandled reg in PPCRegisterInfo::getRegisterNumbering!"); 121 } 122 } 123 124 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST, 125 const TargetInstrInfo &tii) 126 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP), 127 Subtarget(ST), TII(tii) { 128 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 129 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 130 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 131 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 132 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 133 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 134 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 135 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 136 137 // 64-bit 138 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8; 139 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8; 140 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8; 141 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX; 142 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32; 143 } 144 145 /// getPointerRegClass - Return the register class to use to hold pointers. 146 /// This is used for addressing modes. 147 const TargetRegisterClass * 148 PPCRegisterInfo::getPointerRegClass(unsigned Kind) const { 149 if (Subtarget.isPPC64()) 150 return &PPC::G8RCRegClass; 151 return &PPC::GPRCRegClass; 152 } 153 154 const unsigned* 155 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 156 // 32-bit Darwin calling convention. 157 static const unsigned Darwin32_CalleeSavedRegs[] = { 158 PPC::R13, PPC::R14, PPC::R15, 159 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 160 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 161 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 162 PPC::R28, PPC::R29, PPC::R30, PPC::R31, 163 164 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 165 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 166 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 167 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 168 PPC::F30, PPC::F31, 169 170 PPC::CR2, PPC::CR3, PPC::CR4, 171 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 172 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 173 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 174 175 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 176 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 177 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 178 179 PPC::LR, 0 180 }; 181 182 // 32-bit SVR4 calling convention. 183 static const unsigned SVR4_CalleeSavedRegs[] = { 184 PPC::R14, PPC::R15, 185 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 186 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 187 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 188 PPC::R28, PPC::R29, PPC::R30, PPC::R31, 189 190 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 191 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 192 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 193 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 194 PPC::F30, PPC::F31, 195 196 PPC::CR2, PPC::CR3, PPC::CR4, 197 198 PPC::VRSAVE, 199 200 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 201 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 202 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 203 204 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 205 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 206 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 207 208 0 209 }; 210 // 64-bit Darwin calling convention. 211 static const unsigned Darwin64_CalleeSavedRegs[] = { 212 PPC::X14, PPC::X15, 213 PPC::X16, PPC::X17, PPC::X18, PPC::X19, 214 PPC::X20, PPC::X21, PPC::X22, PPC::X23, 215 PPC::X24, PPC::X25, PPC::X26, PPC::X27, 216 PPC::X28, PPC::X29, PPC::X30, PPC::X31, 217 218 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 219 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 220 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 221 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 222 PPC::F30, PPC::F31, 223 224 PPC::CR2, PPC::CR3, PPC::CR4, 225 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 226 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 227 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 228 229 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 230 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 231 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 232 233 PPC::LR8, 0 234 }; 235 236 // 64-bit SVR4 calling convention. 237 static const unsigned SVR4_64_CalleeSavedRegs[] = { 238 PPC::X14, PPC::X15, 239 PPC::X16, PPC::X17, PPC::X18, PPC::X19, 240 PPC::X20, PPC::X21, PPC::X22, PPC::X23, 241 PPC::X24, PPC::X25, PPC::X26, PPC::X27, 242 PPC::X28, PPC::X29, PPC::X30, PPC::X31, 243 244 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 245 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 246 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 247 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 248 PPC::F30, PPC::F31, 249 250 PPC::CR2, PPC::CR3, PPC::CR4, 251 252 PPC::VRSAVE, 253 254 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 255 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 256 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 257 258 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 259 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 260 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 261 262 0 263 }; 264 265 if (Subtarget.isDarwinABI()) 266 return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegs : 267 Darwin32_CalleeSavedRegs; 268 269 return Subtarget.isPPC64() ? SVR4_64_CalleeSavedRegs : SVR4_CalleeSavedRegs; 270 } 271 272 // needsFP - Return true if the specified function should have a dedicated frame 273 // pointer register. This is true if the function has variable sized allocas or 274 // if frame pointer elimination is disabled. 275 // 276 static bool needsFP(const MachineFunction &MF) { 277 const MachineFrameInfo *MFI = MF.getFrameInfo(); 278 // Naked functions have no stack frame pushed, so we don't have a frame pointer. 279 if (MF.getFunction()->hasFnAttr(Attribute::Naked)) 280 return false; 281 return DisableFramePointerElim(MF) || MFI->hasVarSizedObjects() || 282 (GuaranteedTailCallOpt && MF.getInfo<PPCFunctionInfo>()->hasFastCall()); 283 } 284 285 static bool spillsCR(const MachineFunction &MF) { 286 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 287 return FuncInfo->isCRSpilled(); 288 } 289 290 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 291 BitVector Reserved(getNumRegs()); 292 Reserved.set(PPC::R0); 293 Reserved.set(PPC::R1); 294 Reserved.set(PPC::LR); 295 Reserved.set(PPC::LR8); 296 Reserved.set(PPC::RM); 297 298 // The SVR4 ABI reserves r2 and r13 299 if (Subtarget.isSVR4ABI()) { 300 Reserved.set(PPC::R2); // System-reserved register 301 Reserved.set(PPC::R13); // Small Data Area pointer register 302 } 303 // Reserve R2 on Darwin to hack around the problem of save/restore of CR 304 // when the stack frame is too big to address directly; we need two regs. 305 // This is a hack. 306 if (Subtarget.isDarwinABI()) { 307 Reserved.set(PPC::R2); 308 } 309 310 // On PPC64, r13 is the thread pointer. Never allocate this register. 311 // Note that this is over conservative, as it also prevents allocation of R31 312 // when the FP is not needed. 313 if (Subtarget.isPPC64()) { 314 Reserved.set(PPC::R13); 315 Reserved.set(PPC::R31); 316 317 if (!EnableRegisterScavenging) 318 Reserved.set(PPC::R0); // FIXME (64-bit): Remove 319 320 Reserved.set(PPC::X0); 321 Reserved.set(PPC::X1); 322 Reserved.set(PPC::X13); 323 Reserved.set(PPC::X31); 324 325 // The 64-bit SVR4 ABI reserves r2 for the TOC pointer. 326 if (Subtarget.isSVR4ABI()) { 327 Reserved.set(PPC::X2); 328 } 329 // Reserve R2 on Darwin to hack around the problem of save/restore of CR 330 // when the stack frame is too big to address directly; we need two regs. 331 // This is a hack. 332 if (Subtarget.isDarwinABI()) { 333 Reserved.set(PPC::X2); 334 } 335 } 336 337 if (needsFP(MF)) 338 Reserved.set(PPC::R31); 339 340 return Reserved; 341 } 342 343 //===----------------------------------------------------------------------===// 344 // Stack Frame Processing methods 345 //===----------------------------------------------------------------------===// 346 347 // hasFP - Return true if the specified function actually has a dedicated frame 348 // pointer register. This is true if the function needs a frame pointer and has 349 // a non-zero stack size. 350 bool PPCRegisterInfo::hasFP(const MachineFunction &MF) const { 351 const MachineFrameInfo *MFI = MF.getFrameInfo(); 352 return MFI->getStackSize() && needsFP(MF); 353 } 354 355 /// MustSaveLR - Return true if this function requires that we save the LR 356 /// register onto the stack in the prolog and restore it in the epilog of the 357 /// function. 358 static bool MustSaveLR(const MachineFunction &MF, unsigned LR) { 359 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>(); 360 361 // We need a save/restore of LR if there is any def of LR (which is 362 // defined by calls, including the PIC setup sequence), or if there is 363 // some use of the LR stack slot (e.g. for builtin_return_address). 364 // (LR comes in 32 and 64 bit versions.) 365 MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR); 366 return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired(); 367 } 368 369 370 371 void PPCRegisterInfo:: 372 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 373 MachineBasicBlock::iterator I) const { 374 if (GuaranteedTailCallOpt && I->getOpcode() == PPC::ADJCALLSTACKUP) { 375 // Add (actually subtract) back the amount the callee popped on return. 376 if (int CalleeAmt = I->getOperand(1).getImm()) { 377 bool is64Bit = Subtarget.isPPC64(); 378 CalleeAmt *= -1; 379 unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1; 380 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0; 381 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI; 382 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4; 383 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS; 384 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI; 385 MachineInstr *MI = I; 386 DebugLoc dl = MI->getDebugLoc(); 387 388 if (isInt<16>(CalleeAmt)) { 389 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg).addReg(StackReg). 390 addImm(CalleeAmt); 391 } else { 392 MachineBasicBlock::iterator MBBI = I; 393 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) 394 .addImm(CalleeAmt >> 16); 395 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) 396 .addReg(TmpReg, RegState::Kill) 397 .addImm(CalleeAmt & 0xFFFF); 398 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr)) 399 .addReg(StackReg) 400 .addReg(StackReg) 401 .addReg(TmpReg); 402 } 403 } 404 } 405 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions. 406 MBB.erase(I); 407 } 408 409 /// findScratchRegister - Find a 'free' PPC register. Try for a call-clobbered 410 /// register first and then a spilled callee-saved register if that fails. 411 static 412 unsigned findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS, 413 const TargetRegisterClass *RC, int SPAdj) { 414 assert(RS && "Register scavenging must be on"); 415 unsigned Reg = RS->FindUnusedReg(RC); 416 // FIXME: move ARM callee-saved reg scan to target independent code, then 417 // search for already spilled CS register here. 418 if (Reg == 0) 419 Reg = RS->scavengeRegister(RC, II, SPAdj); 420 return Reg; 421 } 422 423 /// lowerDynamicAlloc - Generate the code for allocating an object in the 424 /// current frame. The sequence of code with be in the general form 425 /// 426 /// addi R0, SP, \#frameSize ; get the address of the previous frame 427 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size 428 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation 429 /// 430 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II, 431 int SPAdj, RegScavenger *RS) const { 432 // Get the instruction. 433 MachineInstr &MI = *II; 434 // Get the instruction's basic block. 435 MachineBasicBlock &MBB = *MI.getParent(); 436 // Get the basic block's function. 437 MachineFunction &MF = *MBB.getParent(); 438 // Get the frame info. 439 MachineFrameInfo *MFI = MF.getFrameInfo(); 440 // Determine whether 64-bit pointers are used. 441 bool LP64 = Subtarget.isPPC64(); 442 DebugLoc dl = MI.getDebugLoc(); 443 444 // Get the maximum call stack size. 445 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 446 // Get the total frame size. 447 unsigned FrameSize = MFI->getStackSize(); 448 449 // Get stack alignments. 450 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 451 unsigned MaxAlign = MFI->getMaxAlignment(); 452 if (MaxAlign > TargetAlign) 453 report_fatal_error("Dynamic alloca with large aligns not supported"); 454 455 // Determine the previous frame's address. If FrameSize can't be 456 // represented as 16 bits or we need special alignment, then we load the 457 // previous frame's address from 0(SP). Why not do an addis of the hi? 458 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. 459 // Constructing the constant and adding would take 3 instructions. 460 // Fortunately, a frame greater than 32K is rare. 461 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 462 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 463 const TargetRegisterClass *RC = LP64 ? G8RC : GPRC; 464 465 // FIXME (64-bit): Use "findScratchRegister" 466 unsigned Reg; 467 if (EnableRegisterScavenging) 468 Reg = findScratchRegister(II, RS, RC, SPAdj); 469 else 470 Reg = PPC::R0; 471 472 if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) { 473 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) 474 .addReg(PPC::R31) 475 .addImm(FrameSize); 476 } else if (LP64) { 477 if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part. 478 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg) 479 .addImm(0) 480 .addReg(PPC::X1); 481 else 482 BuildMI(MBB, II, dl, TII.get(PPC::LD), PPC::X0) 483 .addImm(0) 484 .addReg(PPC::X1); 485 } else { 486 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) 487 .addImm(0) 488 .addReg(PPC::R1); 489 } 490 491 // Grow the stack and update the stack pointer link, then determine the 492 // address of new allocated space. 493 if (LP64) { 494 if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part. 495 BuildMI(MBB, II, dl, TII.get(PPC::STDUX)) 496 .addReg(Reg, RegState::Kill) 497 .addReg(PPC::X1) 498 .addReg(MI.getOperand(1).getReg()); 499 else 500 BuildMI(MBB, II, dl, TII.get(PPC::STDUX)) 501 .addReg(PPC::X0, RegState::Kill) 502 .addReg(PPC::X1) 503 .addReg(MI.getOperand(1).getReg()); 504 505 if (!MI.getOperand(1).isKill()) 506 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 507 .addReg(PPC::X1) 508 .addImm(maxCallFrameSize); 509 else 510 // Implicitly kill the register. 511 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 512 .addReg(PPC::X1) 513 .addImm(maxCallFrameSize) 514 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill); 515 } else { 516 BuildMI(MBB, II, dl, TII.get(PPC::STWUX)) 517 .addReg(Reg, RegState::Kill) 518 .addReg(PPC::R1) 519 .addReg(MI.getOperand(1).getReg()); 520 521 if (!MI.getOperand(1).isKill()) 522 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 523 .addReg(PPC::R1) 524 .addImm(maxCallFrameSize); 525 else 526 // Implicitly kill the register. 527 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 528 .addReg(PPC::R1) 529 .addImm(maxCallFrameSize) 530 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill); 531 } 532 533 // Discard the DYNALLOC instruction. 534 MBB.erase(II); 535 } 536 537 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of 538 /// reserving a whole register (R0), we scrounge for one here. This generates 539 /// code like this: 540 /// 541 /// mfcr rA ; Move the conditional register into GPR rA. 542 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot. 543 /// stw rA, FI ; Store rA to the frame. 544 /// 545 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, 546 unsigned FrameIndex, int SPAdj, 547 RegScavenger *RS) const { 548 // Get the instruction. 549 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>, <FI> 550 // Get the instruction's basic block. 551 MachineBasicBlock &MBB = *MI.getParent(); 552 DebugLoc dl = MI.getDebugLoc(); 553 554 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 555 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 556 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC; 557 unsigned Reg = findScratchRegister(II, RS, RC, SPAdj); 558 unsigned SrcReg = MI.getOperand(0).getReg(); 559 560 // We need to store the CR in the low 4-bits of the saved value. First, issue 561 // an MFCRpsued to save all of the CRBits and, if needed, kill the SrcReg. 562 BuildMI(MBB, II, dl, TII.get(PPC::MFCRpseud), Reg) 563 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 564 565 // If the saved register wasn't CR0, shift the bits left so that they are in 566 // CR0's slot. 567 if (SrcReg != PPC::CR0) 568 // rlwinm rA, rA, ShiftBits, 0, 31. 569 BuildMI(MBB, II, dl, TII.get(PPC::RLWINM), Reg) 570 .addReg(Reg, RegState::Kill) 571 .addImm(PPCRegisterInfo::getRegisterNumbering(SrcReg) * 4) 572 .addImm(0) 573 .addImm(31); 574 575 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::STW)) 576 .addReg(Reg, getKillRegState(MI.getOperand(1).getImm())), 577 FrameIndex); 578 579 // Discard the pseudo instruction. 580 MBB.erase(II); 581 } 582 583 unsigned 584 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 585 int SPAdj, FrameIndexValue *Value, 586 RegScavenger *RS) const { 587 assert(SPAdj == 0 && "Unexpected"); 588 589 // Get the instruction. 590 MachineInstr &MI = *II; 591 // Get the instruction's basic block. 592 MachineBasicBlock &MBB = *MI.getParent(); 593 // Get the basic block's function. 594 MachineFunction &MF = *MBB.getParent(); 595 // Get the frame info. 596 MachineFrameInfo *MFI = MF.getFrameInfo(); 597 DebugLoc dl = MI.getDebugLoc(); 598 599 // Find out which operand is the frame index. 600 unsigned FIOperandNo = 0; 601 while (!MI.getOperand(FIOperandNo).isFI()) { 602 ++FIOperandNo; 603 assert(FIOperandNo != MI.getNumOperands() && 604 "Instr doesn't have FrameIndex operand!"); 605 } 606 // Take into account whether it's an add or mem instruction 607 unsigned OffsetOperandNo = (FIOperandNo == 2) ? 1 : 2; 608 if (MI.isInlineAsm()) 609 OffsetOperandNo = FIOperandNo-1; 610 611 // Get the frame index. 612 int FrameIndex = MI.getOperand(FIOperandNo).getIndex(); 613 614 // Get the frame pointer save index. Users of this index are primarily 615 // DYNALLOC instructions. 616 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 617 int FPSI = FI->getFramePointerSaveIndex(); 618 // Get the instruction opcode. 619 unsigned OpC = MI.getOpcode(); 620 621 // Special case for dynamic alloca. 622 if (FPSI && FrameIndex == FPSI && 623 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { 624 lowerDynamicAlloc(II, SPAdj, RS); 625 return 0; 626 } 627 628 // Special case for pseudo-op SPILL_CR. 629 if (EnableRegisterScavenging) // FIXME (64-bit): Enable by default. 630 if (OpC == PPC::SPILL_CR) { 631 lowerCRSpilling(II, FrameIndex, SPAdj, RS); 632 return 0; 633 } 634 635 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 636 MI.getOperand(FIOperandNo).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1, 637 false); 638 639 // Figure out if the offset in the instruction is shifted right two bits. This 640 // is true for instructions like "STD", which the machine implicitly adds two 641 // low zeros to. 642 bool isIXAddr = false; 643 switch (OpC) { 644 case PPC::LWA: 645 case PPC::LD: 646 case PPC::STD: 647 case PPC::STD_32: 648 isIXAddr = true; 649 break; 650 } 651 652 // Now add the frame object offset to the offset from r1. 653 int Offset = MFI->getObjectOffset(FrameIndex); 654 if (!isIXAddr) 655 Offset += MI.getOperand(OffsetOperandNo).getImm(); 656 else 657 Offset += MI.getOperand(OffsetOperandNo).getImm() << 2; 658 659 // If we're not using a Frame Pointer that has been set to the value of the 660 // SP before having the stack size subtracted from it, then add the stack size 661 // to Offset to get the correct offset. 662 // Naked functions have stack size 0, although getStackSize may not reflect that 663 // because we didn't call all the pieces that compute it for naked functions. 664 if (!MF.getFunction()->hasFnAttr(Attribute::Naked)) 665 Offset += MFI->getStackSize(); 666 667 // If we can, encode the offset directly into the instruction. If this is a 668 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If 669 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits 670 // clear can be encoded. This is extremely uncommon, because normally you 671 // only "std" to a stack slot that is at least 4-byte aligned, but it can 672 // happen in invalid code. 673 if (isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0)) { 674 if (isIXAddr) 675 Offset >>= 2; // The actual encoded value has the low two bits zero. 676 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 677 return 0; 678 } 679 680 // The offset doesn't fit into a single register, scavenge one to build the 681 // offset in. 682 // FIXME: figure out what SPAdj is doing here. 683 684 // FIXME (64-bit): Use "findScratchRegister". 685 unsigned SReg; 686 if (EnableRegisterScavenging) 687 SReg = findScratchRegister(II, RS, &PPC::GPRCRegClass, SPAdj); 688 else 689 SReg = PPC::R0; 690 691 // Insert a set of rA with the full offset value before the ld, st, or add 692 BuildMI(MBB, II, dl, TII.get(PPC::LIS), SReg) 693 .addImm(Offset >> 16); 694 BuildMI(MBB, II, dl, TII.get(PPC::ORI), SReg) 695 .addReg(SReg, RegState::Kill) 696 .addImm(Offset); 697 698 // Convert into indexed form of the instruction: 699 // 700 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 701 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 702 unsigned OperandBase; 703 704 if (OpC != TargetOpcode::INLINEASM) { 705 assert(ImmToIdxMap.count(OpC) && 706 "No indexed form of load or store available!"); 707 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; 708 MI.setDesc(TII.get(NewOpcode)); 709 OperandBase = 1; 710 } else { 711 OperandBase = OffsetOperandNo; 712 } 713 714 unsigned StackReg = MI.getOperand(FIOperandNo).getReg(); 715 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false); 716 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false); 717 return 0; 718 } 719 720 /// VRRegNo - Map from a numbered VR register to its enum value. 721 /// 722 static const unsigned short VRRegNo[] = { 723 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 , 724 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, 725 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, 726 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31 727 }; 728 729 /// RemoveVRSaveCode - We have found that this function does not need any code 730 /// to manipulate the VRSAVE register, even though it uses vector registers. 731 /// This can happen when the only registers used are known to be live in or out 732 /// of the function. Remove all of the VRSAVE related code from the function. 733 static void RemoveVRSaveCode(MachineInstr *MI) { 734 MachineBasicBlock *Entry = MI->getParent(); 735 MachineFunction *MF = Entry->getParent(); 736 737 // We know that the MTVRSAVE instruction immediately follows MI. Remove it. 738 MachineBasicBlock::iterator MBBI = MI; 739 ++MBBI; 740 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE); 741 MBBI->eraseFromParent(); 742 743 bool RemovedAllMTVRSAVEs = true; 744 // See if we can find and remove the MTVRSAVE instruction from all of the 745 // epilog blocks. 746 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) { 747 // If last instruction is a return instruction, add an epilogue 748 if (!I->empty() && I->back().getDesc().isReturn()) { 749 bool FoundIt = false; 750 for (MBBI = I->end(); MBBI != I->begin(); ) { 751 --MBBI; 752 if (MBBI->getOpcode() == PPC::MTVRSAVE) { 753 MBBI->eraseFromParent(); // remove it. 754 FoundIt = true; 755 break; 756 } 757 } 758 RemovedAllMTVRSAVEs &= FoundIt; 759 } 760 } 761 762 // If we found and removed all MTVRSAVE instructions, remove the read of 763 // VRSAVE as well. 764 if (RemovedAllMTVRSAVEs) { 765 MBBI = MI; 766 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?"); 767 --MBBI; 768 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?"); 769 MBBI->eraseFromParent(); 770 } 771 772 // Finally, nuke the UPDATE_VRSAVE. 773 MI->eraseFromParent(); 774 } 775 776 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the 777 // instruction selector. Based on the vector registers that have been used, 778 // transform this into the appropriate ORI instruction. 779 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) { 780 MachineFunction *MF = MI->getParent()->getParent(); 781 DebugLoc dl = MI->getDebugLoc(); 782 783 unsigned UsedRegMask = 0; 784 for (unsigned i = 0; i != 32; ++i) 785 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i])) 786 UsedRegMask |= 1 << (31-i); 787 788 // Live in and live out values already must be in the mask, so don't bother 789 // marking them. 790 for (MachineRegisterInfo::livein_iterator 791 I = MF->getRegInfo().livein_begin(), 792 E = MF->getRegInfo().livein_end(); I != E; ++I) { 793 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first); 794 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg. 795 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 796 } 797 for (MachineRegisterInfo::liveout_iterator 798 I = MF->getRegInfo().liveout_begin(), 799 E = MF->getRegInfo().liveout_end(); I != E; ++I) { 800 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I); 801 if (VRRegNo[RegNo] == *I) // If this really is a vector reg. 802 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 803 } 804 805 // If no registers are used, turn this into a copy. 806 if (UsedRegMask == 0) { 807 // Remove all VRSAVE code. 808 RemoveVRSaveCode(MI); 809 return; 810 } 811 812 unsigned SrcReg = MI->getOperand(1).getReg(); 813 unsigned DstReg = MI->getOperand(0).getReg(); 814 815 if ((UsedRegMask & 0xFFFF) == UsedRegMask) { 816 if (DstReg != SrcReg) 817 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 818 .addReg(SrcReg) 819 .addImm(UsedRegMask); 820 else 821 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 822 .addReg(SrcReg, RegState::Kill) 823 .addImm(UsedRegMask); 824 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { 825 if (DstReg != SrcReg) 826 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 827 .addReg(SrcReg) 828 .addImm(UsedRegMask >> 16); 829 else 830 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 831 .addReg(SrcReg, RegState::Kill) 832 .addImm(UsedRegMask >> 16); 833 } else { 834 if (DstReg != SrcReg) 835 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 836 .addReg(SrcReg) 837 .addImm(UsedRegMask >> 16); 838 else 839 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 840 .addReg(SrcReg, RegState::Kill) 841 .addImm(UsedRegMask >> 16); 842 843 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 844 .addReg(DstReg, RegState::Kill) 845 .addImm(UsedRegMask & 0xFFFF); 846 } 847 848 // Remove the old UPDATE_VRSAVE instruction. 849 MI->eraseFromParent(); 850 } 851 852 /// determineFrameLayout - Determine the size of the frame and maximum call 853 /// frame size. 854 void PPCRegisterInfo::determineFrameLayout(MachineFunction &MF) const { 855 MachineFrameInfo *MFI = MF.getFrameInfo(); 856 857 // Get the number of bytes to allocate from the FrameInfo 858 unsigned FrameSize = MFI->getStackSize(); 859 860 // Get the alignments provided by the target, and the maximum alignment 861 // (if any) of the fixed frame objects. 862 unsigned MaxAlign = MFI->getMaxAlignment(); 863 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 864 unsigned AlignMask = TargetAlign - 1; // 865 866 // If we are a leaf function, and use up to 224 bytes of stack space, 867 // don't have a frame pointer, calls, or dynamic alloca then we do not need 868 // to adjust the stack pointer (we fit in the Red Zone). 869 bool DisableRedZone = MF.getFunction()->hasFnAttr(Attribute::NoRedZone); 870 // FIXME SVR4 The 32-bit SVR4 ABI has no red zone. 871 if (!DisableRedZone && 872 FrameSize <= 224 && // Fits in red zone. 873 !MFI->hasVarSizedObjects() && // No dynamic alloca. 874 !MFI->adjustsStack() && // No calls. 875 (!ALIGN_STACK || MaxAlign <= TargetAlign)) { // No special alignment. 876 // No need for frame 877 MFI->setStackSize(0); 878 return; 879 } 880 881 // Get the maximum call frame size of all the calls. 882 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 883 884 // Maximum call frame needs to be at least big enough for linkage and 8 args. 885 unsigned minCallFrameSize = 886 PPCFrameInfo::getMinCallFrameSize(Subtarget.isPPC64(), 887 Subtarget.isDarwinABI()); 888 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize); 889 890 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so 891 // that allocations will be aligned. 892 if (MFI->hasVarSizedObjects()) 893 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask; 894 895 // Update maximum call frame size. 896 MFI->setMaxCallFrameSize(maxCallFrameSize); 897 898 // Include call frame size in total. 899 FrameSize += maxCallFrameSize; 900 901 // Make sure the frame is aligned. 902 FrameSize = (FrameSize + AlignMask) & ~AlignMask; 903 904 // Update frame info. 905 MFI->setStackSize(FrameSize); 906 } 907 908 void 909 PPCRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 910 RegScavenger *RS) const { 911 // Save and clear the LR state. 912 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 913 unsigned LR = getRARegister(); 914 FI->setMustSaveLR(MustSaveLR(MF, LR)); 915 MF.getRegInfo().setPhysRegUnused(LR); 916 917 // Save R31 if necessary 918 int FPSI = FI->getFramePointerSaveIndex(); 919 bool isPPC64 = Subtarget.isPPC64(); 920 bool isDarwinABI = Subtarget.isDarwinABI(); 921 MachineFrameInfo *MFI = MF.getFrameInfo(); 922 923 // If the frame pointer save index hasn't been defined yet. 924 if (!FPSI && needsFP(MF)) { 925 // Find out what the fix offset of the frame pointer save area. 926 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(isPPC64, 927 isDarwinABI); 928 // Allocate the frame index for frame pointer save area. 929 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true); 930 // Save the result. 931 FI->setFramePointerSaveIndex(FPSI); 932 } 933 934 // Reserve stack space to move the linkage area to in case of a tail call. 935 int TCSPDelta = 0; 936 if (GuaranteedTailCallOpt && (TCSPDelta = FI->getTailCallSPDelta()) < 0) { 937 MF.getFrameInfo()->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true); 938 } 939 940 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or 941 // a large stack, which will require scavenging a register to materialize a 942 // large offset. 943 // FIXME: this doesn't actually check stack size, so is a bit pessimistic 944 // FIXME: doesn't detect whether or not we need to spill vXX, which requires 945 // r0 for now. 946 947 if (EnableRegisterScavenging) // FIXME (64-bit): Enable. 948 if (needsFP(MF) || spillsCR(MF)) { 949 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 950 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 951 const TargetRegisterClass *RC = isPPC64 ? G8RC : GPRC; 952 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 953 RC->getAlignment(), 954 false)); 955 } 956 } 957 958 void 959 PPCRegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) 960 const { 961 // Early exit if not using the SVR4 ABI. 962 if (!Subtarget.isSVR4ABI()) { 963 return; 964 } 965 966 // Get callee saved register information. 967 MachineFrameInfo *FFI = MF.getFrameInfo(); 968 const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo(); 969 970 // Early exit if no callee saved registers are modified! 971 if (CSI.empty() && !needsFP(MF)) { 972 return; 973 } 974 975 unsigned MinGPR = PPC::R31; 976 unsigned MinG8R = PPC::X31; 977 unsigned MinFPR = PPC::F31; 978 unsigned MinVR = PPC::V31; 979 980 bool HasGPSaveArea = false; 981 bool HasG8SaveArea = false; 982 bool HasFPSaveArea = false; 983 bool HasCRSaveArea = false; 984 bool HasVRSAVESaveArea = false; 985 bool HasVRSaveArea = false; 986 987 SmallVector<CalleeSavedInfo, 18> GPRegs; 988 SmallVector<CalleeSavedInfo, 18> G8Regs; 989 SmallVector<CalleeSavedInfo, 18> FPRegs; 990 SmallVector<CalleeSavedInfo, 18> VRegs; 991 992 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 993 unsigned Reg = CSI[i].getReg(); 994 if (PPC::GPRCRegisterClass->contains(Reg)) { 995 HasGPSaveArea = true; 996 997 GPRegs.push_back(CSI[i]); 998 999 if (Reg < MinGPR) { 1000 MinGPR = Reg; 1001 } 1002 } else if (PPC::G8RCRegisterClass->contains(Reg)) { 1003 HasG8SaveArea = true; 1004 1005 G8Regs.push_back(CSI[i]); 1006 1007 if (Reg < MinG8R) { 1008 MinG8R = Reg; 1009 } 1010 } else if (PPC::F8RCRegisterClass->contains(Reg)) { 1011 HasFPSaveArea = true; 1012 1013 FPRegs.push_back(CSI[i]); 1014 1015 if (Reg < MinFPR) { 1016 MinFPR = Reg; 1017 } 1018 // FIXME SVR4: Disable CR save area for now. 1019 } else if (PPC::CRBITRCRegisterClass->contains(Reg) 1020 || PPC::CRRCRegisterClass->contains(Reg)) { 1021 // HasCRSaveArea = true; 1022 } else if (PPC::VRSAVERCRegisterClass->contains(Reg)) { 1023 HasVRSAVESaveArea = true; 1024 } else if (PPC::VRRCRegisterClass->contains(Reg)) { 1025 HasVRSaveArea = true; 1026 1027 VRegs.push_back(CSI[i]); 1028 1029 if (Reg < MinVR) { 1030 MinVR = Reg; 1031 } 1032 } else { 1033 llvm_unreachable("Unknown RegisterClass!"); 1034 } 1035 } 1036 1037 PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>(); 1038 1039 int64_t LowerBound = 0; 1040 1041 // Take into account stack space reserved for tail calls. 1042 int TCSPDelta = 0; 1043 if (GuaranteedTailCallOpt && (TCSPDelta = PFI->getTailCallSPDelta()) < 0) { 1044 LowerBound = TCSPDelta; 1045 } 1046 1047 // The Floating-point register save area is right below the back chain word 1048 // of the previous stack frame. 1049 if (HasFPSaveArea) { 1050 for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) { 1051 int FI = FPRegs[i].getFrameIdx(); 1052 1053 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1054 } 1055 1056 LowerBound -= (31 - getRegisterNumbering(MinFPR) + 1) * 8; 1057 } 1058 1059 // Check whether the frame pointer register is allocated. If so, make sure it 1060 // is spilled to the correct offset. 1061 if (needsFP(MF)) { 1062 HasGPSaveArea = true; 1063 1064 int FI = PFI->getFramePointerSaveIndex(); 1065 assert(FI && "No Frame Pointer Save Slot!"); 1066 1067 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1068 } 1069 1070 // General register save area starts right below the Floating-point 1071 // register save area. 1072 if (HasGPSaveArea || HasG8SaveArea) { 1073 // Move general register save area spill slots down, taking into account 1074 // the size of the Floating-point register save area. 1075 for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) { 1076 int FI = GPRegs[i].getFrameIdx(); 1077 1078 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1079 } 1080 1081 // Move general register save area spill slots down, taking into account 1082 // the size of the Floating-point register save area. 1083 for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) { 1084 int FI = G8Regs[i].getFrameIdx(); 1085 1086 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1087 } 1088 1089 unsigned MinReg = std::min<unsigned>(getRegisterNumbering(MinGPR), 1090 getRegisterNumbering(MinG8R)); 1091 1092 if (Subtarget.isPPC64()) { 1093 LowerBound -= (31 - MinReg + 1) * 8; 1094 } else { 1095 LowerBound -= (31 - MinReg + 1) * 4; 1096 } 1097 } 1098 1099 // The CR save area is below the general register save area. 1100 if (HasCRSaveArea) { 1101 // FIXME SVR4: Is it actually possible to have multiple elements in CSI 1102 // which have the CR/CRBIT register class? 1103 // Adjust the frame index of the CR spill slot. 1104 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1105 unsigned Reg = CSI[i].getReg(); 1106 1107 if (PPC::CRBITRCRegisterClass->contains(Reg) || 1108 PPC::CRRCRegisterClass->contains(Reg)) { 1109 int FI = CSI[i].getFrameIdx(); 1110 1111 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1112 } 1113 } 1114 1115 LowerBound -= 4; // The CR save area is always 4 bytes long. 1116 } 1117 1118 if (HasVRSAVESaveArea) { 1119 // FIXME SVR4: Is it actually possible to have multiple elements in CSI 1120 // which have the VRSAVE register class? 1121 // Adjust the frame index of the VRSAVE spill slot. 1122 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1123 unsigned Reg = CSI[i].getReg(); 1124 1125 if (PPC::VRSAVERCRegisterClass->contains(Reg)) { 1126 int FI = CSI[i].getFrameIdx(); 1127 1128 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1129 } 1130 } 1131 1132 LowerBound -= 4; // The VRSAVE save area is always 4 bytes long. 1133 } 1134 1135 if (HasVRSaveArea) { 1136 // Insert alignment padding, we need 16-byte alignment. 1137 LowerBound = (LowerBound - 15) & ~(15); 1138 1139 for (unsigned i = 0, e = VRegs.size(); i != e; ++i) { 1140 int FI = VRegs[i].getFrameIdx(); 1141 1142 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1143 } 1144 } 1145 } 1146 1147 void 1148 PPCRegisterInfo::emitPrologue(MachineFunction &MF) const { 1149 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB 1150 MachineBasicBlock::iterator MBBI = MBB.begin(); 1151 MachineFrameInfo *MFI = MF.getFrameInfo(); 1152 MachineModuleInfo &MMI = MF.getMMI(); 1153 DebugLoc dl; 1154 bool needsFrameMoves = MMI.hasDebugInfo() || 1155 !MF.getFunction()->doesNotThrow() || 1156 UnwindTablesMandatory; 1157 1158 // Prepare for frame info. 1159 MCSymbol *FrameLabel = 0; 1160 1161 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it, 1162 // process it. 1163 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { 1164 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) { 1165 HandleVRSaveUpdate(MBBI, TII); 1166 break; 1167 } 1168 } 1169 1170 // Move MBBI back to the beginning of the function. 1171 MBBI = MBB.begin(); 1172 1173 // Work out frame sizes. 1174 determineFrameLayout(MF); 1175 unsigned FrameSize = MFI->getStackSize(); 1176 1177 int NegFrameSize = -FrameSize; 1178 1179 // Get processor type. 1180 bool isPPC64 = Subtarget.isPPC64(); 1181 // Get operating system 1182 bool isDarwinABI = Subtarget.isDarwinABI(); 1183 // Check if the link register (LR) must be saved. 1184 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1185 bool MustSaveLR = FI->mustSaveLR(); 1186 // Do we have a frame pointer for this function? 1187 bool HasFP = hasFP(MF) && FrameSize; 1188 1189 int LROffset = PPCFrameInfo::getReturnSaveOffset(isPPC64, isDarwinABI); 1190 1191 int FPOffset = 0; 1192 if (HasFP) { 1193 if (Subtarget.isSVR4ABI()) { 1194 MachineFrameInfo *FFI = MF.getFrameInfo(); 1195 int FPIndex = FI->getFramePointerSaveIndex(); 1196 assert(FPIndex && "No Frame Pointer Save Slot!"); 1197 FPOffset = FFI->getObjectOffset(FPIndex); 1198 } else { 1199 FPOffset = PPCFrameInfo::getFramePointerSaveOffset(isPPC64, isDarwinABI); 1200 } 1201 } 1202 1203 if (isPPC64) { 1204 if (MustSaveLR) 1205 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR8), PPC::X0); 1206 1207 if (HasFP) 1208 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD)) 1209 .addReg(PPC::X31) 1210 .addImm(FPOffset/4) 1211 .addReg(PPC::X1); 1212 1213 if (MustSaveLR) 1214 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD)) 1215 .addReg(PPC::X0) 1216 .addImm(LROffset / 4) 1217 .addReg(PPC::X1); 1218 } else { 1219 if (MustSaveLR) 1220 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR), PPC::R0); 1221 1222 if (HasFP) 1223 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW)) 1224 .addReg(PPC::R31) 1225 .addImm(FPOffset) 1226 .addReg(PPC::R1); 1227 1228 if (MustSaveLR) 1229 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW)) 1230 .addReg(PPC::R0) 1231 .addImm(LROffset) 1232 .addReg(PPC::R1); 1233 } 1234 1235 // Skip if a leaf routine. 1236 if (!FrameSize) return; 1237 1238 // Get stack alignments. 1239 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 1240 unsigned MaxAlign = MFI->getMaxAlignment(); 1241 1242 // Adjust stack pointer: r1 += NegFrameSize. 1243 // If there is a preferred stack alignment, align R1 now 1244 if (!isPPC64) { 1245 // PPC32. 1246 if (ALIGN_STACK && MaxAlign > TargetAlign) { 1247 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) && 1248 "Invalid alignment!"); 1249 assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!"); 1250 1251 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), PPC::R0) 1252 .addReg(PPC::R1) 1253 .addImm(0) 1254 .addImm(32 - Log2_32(MaxAlign)) 1255 .addImm(31); 1256 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC) ,PPC::R0) 1257 .addReg(PPC::R0, RegState::Kill) 1258 .addImm(NegFrameSize); 1259 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX)) 1260 .addReg(PPC::R1) 1261 .addReg(PPC::R1) 1262 .addReg(PPC::R0); 1263 } else if (isInt<16>(NegFrameSize)) { 1264 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWU), PPC::R1) 1265 .addReg(PPC::R1) 1266 .addImm(NegFrameSize) 1267 .addReg(PPC::R1); 1268 } else { 1269 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0) 1270 .addImm(NegFrameSize >> 16); 1271 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0) 1272 .addReg(PPC::R0, RegState::Kill) 1273 .addImm(NegFrameSize & 0xFFFF); 1274 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX)) 1275 .addReg(PPC::R1) 1276 .addReg(PPC::R1) 1277 .addReg(PPC::R0); 1278 } 1279 } else { // PPC64. 1280 if (ALIGN_STACK && MaxAlign > TargetAlign) { 1281 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) && 1282 "Invalid alignment!"); 1283 assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!"); 1284 1285 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), PPC::X0) 1286 .addReg(PPC::X1) 1287 .addImm(0) 1288 .addImm(64 - Log2_32(MaxAlign)); 1289 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC8), PPC::X0) 1290 .addReg(PPC::X0) 1291 .addImm(NegFrameSize); 1292 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX)) 1293 .addReg(PPC::X1) 1294 .addReg(PPC::X1) 1295 .addReg(PPC::X0); 1296 } else if (isInt<16>(NegFrameSize)) { 1297 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDU), PPC::X1) 1298 .addReg(PPC::X1) 1299 .addImm(NegFrameSize / 4) 1300 .addReg(PPC::X1); 1301 } else { 1302 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0) 1303 .addImm(NegFrameSize >> 16); 1304 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0) 1305 .addReg(PPC::X0, RegState::Kill) 1306 .addImm(NegFrameSize & 0xFFFF); 1307 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX)) 1308 .addReg(PPC::X1) 1309 .addReg(PPC::X1) 1310 .addReg(PPC::X0); 1311 } 1312 } 1313 1314 std::vector<MachineMove> &Moves = MMI.getFrameMoves(); 1315 1316 // Add the "machine moves" for the instructions we generated above, but in 1317 // reverse order. 1318 if (needsFrameMoves) { 1319 // Mark effective beginning of when frame pointer becomes valid. 1320 FrameLabel = MMI.getContext().CreateTempSymbol(); 1321 BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(FrameLabel); 1322 1323 // Show update of SP. 1324 if (NegFrameSize) { 1325 MachineLocation SPDst(MachineLocation::VirtualFP); 1326 MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize); 1327 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc)); 1328 } else { 1329 MachineLocation SP(isPPC64 ? PPC::X31 : PPC::R31); 1330 Moves.push_back(MachineMove(FrameLabel, SP, SP)); 1331 } 1332 1333 if (HasFP) { 1334 MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset); 1335 MachineLocation FPSrc(isPPC64 ? PPC::X31 : PPC::R31); 1336 Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc)); 1337 } 1338 1339 if (MustSaveLR) { 1340 MachineLocation LRDst(MachineLocation::VirtualFP, LROffset); 1341 MachineLocation LRSrc(isPPC64 ? PPC::LR8 : PPC::LR); 1342 Moves.push_back(MachineMove(FrameLabel, LRDst, LRSrc)); 1343 } 1344 } 1345 1346 MCSymbol *ReadyLabel = 0; 1347 1348 // If there is a frame pointer, copy R1 into R31 1349 if (HasFP) { 1350 if (!isPPC64) { 1351 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR), PPC::R31) 1352 .addReg(PPC::R1) 1353 .addReg(PPC::R1); 1354 } else { 1355 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR8), PPC::X31) 1356 .addReg(PPC::X1) 1357 .addReg(PPC::X1); 1358 } 1359 1360 if (needsFrameMoves) { 1361 ReadyLabel = MMI.getContext().CreateTempSymbol(); 1362 1363 // Mark effective beginning of when frame pointer is ready. 1364 BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(ReadyLabel); 1365 1366 MachineLocation FPDst(HasFP ? (isPPC64 ? PPC::X31 : PPC::R31) : 1367 (isPPC64 ? PPC::X1 : PPC::R1)); 1368 MachineLocation FPSrc(MachineLocation::VirtualFP); 1369 Moves.push_back(MachineMove(ReadyLabel, FPDst, FPSrc)); 1370 } 1371 } 1372 1373 if (needsFrameMoves) { 1374 MCSymbol *Label = HasFP ? ReadyLabel : FrameLabel; 1375 1376 // Add callee saved registers to move list. 1377 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 1378 for (unsigned I = 0, E = CSI.size(); I != E; ++I) { 1379 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx()); 1380 unsigned Reg = CSI[I].getReg(); 1381 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue; 1382 MachineLocation CSDst(MachineLocation::VirtualFP, Offset); 1383 MachineLocation CSSrc(Reg); 1384 Moves.push_back(MachineMove(Label, CSDst, CSSrc)); 1385 } 1386 } 1387 } 1388 1389 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF, 1390 MachineBasicBlock &MBB) const { 1391 MachineBasicBlock::iterator MBBI = prior(MBB.end()); 1392 unsigned RetOpcode = MBBI->getOpcode(); 1393 DebugLoc dl; 1394 1395 assert( (RetOpcode == PPC::BLR || 1396 RetOpcode == PPC::TCRETURNri || 1397 RetOpcode == PPC::TCRETURNdi || 1398 RetOpcode == PPC::TCRETURNai || 1399 RetOpcode == PPC::TCRETURNri8 || 1400 RetOpcode == PPC::TCRETURNdi8 || 1401 RetOpcode == PPC::TCRETURNai8) && 1402 "Can only insert epilog into returning blocks"); 1403 1404 // Get alignment info so we know how to restore r1 1405 const MachineFrameInfo *MFI = MF.getFrameInfo(); 1406 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 1407 unsigned MaxAlign = MFI->getMaxAlignment(); 1408 1409 // Get the number of bytes allocated from the FrameInfo. 1410 int FrameSize = MFI->getStackSize(); 1411 1412 // Get processor type. 1413 bool isPPC64 = Subtarget.isPPC64(); 1414 // Get operating system 1415 bool isDarwinABI = Subtarget.isDarwinABI(); 1416 // Check if the link register (LR) has been saved. 1417 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1418 bool MustSaveLR = FI->mustSaveLR(); 1419 // Do we have a frame pointer for this function? 1420 bool HasFP = hasFP(MF) && FrameSize; 1421 1422 int LROffset = PPCFrameInfo::getReturnSaveOffset(isPPC64, isDarwinABI); 1423 1424 int FPOffset = 0; 1425 if (HasFP) { 1426 if (Subtarget.isSVR4ABI()) { 1427 MachineFrameInfo *FFI = MF.getFrameInfo(); 1428 int FPIndex = FI->getFramePointerSaveIndex(); 1429 assert(FPIndex && "No Frame Pointer Save Slot!"); 1430 FPOffset = FFI->getObjectOffset(FPIndex); 1431 } else { 1432 FPOffset = PPCFrameInfo::getFramePointerSaveOffset(isPPC64, isDarwinABI); 1433 } 1434 } 1435 1436 bool UsesTCRet = RetOpcode == PPC::TCRETURNri || 1437 RetOpcode == PPC::TCRETURNdi || 1438 RetOpcode == PPC::TCRETURNai || 1439 RetOpcode == PPC::TCRETURNri8 || 1440 RetOpcode == PPC::TCRETURNdi8 || 1441 RetOpcode == PPC::TCRETURNai8; 1442 1443 if (UsesTCRet) { 1444 int MaxTCRetDelta = FI->getTailCallSPDelta(); 1445 MachineOperand &StackAdjust = MBBI->getOperand(1); 1446 assert(StackAdjust.isImm() && "Expecting immediate value."); 1447 // Adjust stack pointer. 1448 int StackAdj = StackAdjust.getImm(); 1449 int Delta = StackAdj - MaxTCRetDelta; 1450 assert((Delta >= 0) && "Delta must be positive"); 1451 if (MaxTCRetDelta>0) 1452 FrameSize += (StackAdj +Delta); 1453 else 1454 FrameSize += StackAdj; 1455 } 1456 1457 if (FrameSize) { 1458 // The loaded (or persistent) stack pointer value is offset by the 'stwu' 1459 // on entry to the function. Add this offset back now. 1460 if (!isPPC64) { 1461 // If this function contained a fastcc call and GuaranteedTailCallOpt is 1462 // enabled (=> hasFastCall()==true) the fastcc call might contain a tail 1463 // call which invalidates the stack pointer value in SP(0). So we use the 1464 // value of R31 in this case. 1465 if (FI->hasFastCall() && isInt<16>(FrameSize)) { 1466 assert(hasFP(MF) && "Expecting a valid the frame pointer."); 1467 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1) 1468 .addReg(PPC::R31).addImm(FrameSize); 1469 } else if(FI->hasFastCall()) { 1470 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0) 1471 .addImm(FrameSize >> 16); 1472 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0) 1473 .addReg(PPC::R0, RegState::Kill) 1474 .addImm(FrameSize & 0xFFFF); 1475 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD4)) 1476 .addReg(PPC::R1) 1477 .addReg(PPC::R31) 1478 .addReg(PPC::R0); 1479 } else if (isInt<16>(FrameSize) && 1480 (!ALIGN_STACK || TargetAlign >= MaxAlign) && 1481 !MFI->hasVarSizedObjects()) { 1482 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1) 1483 .addReg(PPC::R1).addImm(FrameSize); 1484 } else { 1485 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ),PPC::R1) 1486 .addImm(0).addReg(PPC::R1); 1487 } 1488 } else { 1489 if (FI->hasFastCall() && isInt<16>(FrameSize)) { 1490 assert(hasFP(MF) && "Expecting a valid the frame pointer."); 1491 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1) 1492 .addReg(PPC::X31).addImm(FrameSize); 1493 } else if(FI->hasFastCall()) { 1494 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0) 1495 .addImm(FrameSize >> 16); 1496 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0) 1497 .addReg(PPC::X0, RegState::Kill) 1498 .addImm(FrameSize & 0xFFFF); 1499 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD8)) 1500 .addReg(PPC::X1) 1501 .addReg(PPC::X31) 1502 .addReg(PPC::X0); 1503 } else if (isInt<16>(FrameSize) && TargetAlign >= MaxAlign && 1504 !MFI->hasVarSizedObjects()) { 1505 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1) 1506 .addReg(PPC::X1).addImm(FrameSize); 1507 } else { 1508 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X1) 1509 .addImm(0).addReg(PPC::X1); 1510 } 1511 } 1512 } 1513 1514 if (isPPC64) { 1515 if (MustSaveLR) 1516 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X0) 1517 .addImm(LROffset/4).addReg(PPC::X1); 1518 1519 if (HasFP) 1520 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X31) 1521 .addImm(FPOffset/4).addReg(PPC::X1); 1522 1523 if (MustSaveLR) 1524 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR8)).addReg(PPC::X0); 1525 } else { 1526 if (MustSaveLR) 1527 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R0) 1528 .addImm(LROffset).addReg(PPC::R1); 1529 1530 if (HasFP) 1531 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R31) 1532 .addImm(FPOffset).addReg(PPC::R1); 1533 1534 if (MustSaveLR) 1535 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR)).addReg(PPC::R0); 1536 } 1537 1538 // Callee pop calling convention. Pop parameter/linkage area. Used for tail 1539 // call optimization 1540 if (GuaranteedTailCallOpt && RetOpcode == PPC::BLR && 1541 MF.getFunction()->getCallingConv() == CallingConv::Fast) { 1542 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1543 unsigned CallerAllocatedAmt = FI->getMinReservedArea(); 1544 unsigned StackReg = isPPC64 ? PPC::X1 : PPC::R1; 1545 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31; 1546 unsigned TmpReg = isPPC64 ? PPC::X0 : PPC::R0; 1547 unsigned ADDIInstr = isPPC64 ? PPC::ADDI8 : PPC::ADDI; 1548 unsigned ADDInstr = isPPC64 ? PPC::ADD8 : PPC::ADD4; 1549 unsigned LISInstr = isPPC64 ? PPC::LIS8 : PPC::LIS; 1550 unsigned ORIInstr = isPPC64 ? PPC::ORI8 : PPC::ORI; 1551 1552 if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) { 1553 BuildMI(MBB, MBBI, dl, TII.get(ADDIInstr), StackReg) 1554 .addReg(StackReg).addImm(CallerAllocatedAmt); 1555 } else { 1556 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) 1557 .addImm(CallerAllocatedAmt >> 16); 1558 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) 1559 .addReg(TmpReg, RegState::Kill) 1560 .addImm(CallerAllocatedAmt & 0xFFFF); 1561 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr)) 1562 .addReg(StackReg) 1563 .addReg(FPReg) 1564 .addReg(TmpReg); 1565 } 1566 } else if (RetOpcode == PPC::TCRETURNdi) { 1567 MBBI = prior(MBB.end()); 1568 MachineOperand &JumpTarget = MBBI->getOperand(0); 1569 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)). 1570 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); 1571 } else if (RetOpcode == PPC::TCRETURNri) { 1572 MBBI = prior(MBB.end()); 1573 assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); 1574 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR)); 1575 } else if (RetOpcode == PPC::TCRETURNai) { 1576 MBBI = prior(MBB.end()); 1577 MachineOperand &JumpTarget = MBBI->getOperand(0); 1578 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm()); 1579 } else if (RetOpcode == PPC::TCRETURNdi8) { 1580 MBBI = prior(MBB.end()); 1581 MachineOperand &JumpTarget = MBBI->getOperand(0); 1582 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)). 1583 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); 1584 } else if (RetOpcode == PPC::TCRETURNri8) { 1585 MBBI = prior(MBB.end()); 1586 assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); 1587 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8)); 1588 } else if (RetOpcode == PPC::TCRETURNai8) { 1589 MBBI = prior(MBB.end()); 1590 MachineOperand &JumpTarget = MBBI->getOperand(0); 1591 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm()); 1592 } 1593 } 1594 1595 unsigned PPCRegisterInfo::getRARegister() const { 1596 return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8; 1597 } 1598 1599 unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 1600 if (!Subtarget.isPPC64()) 1601 return hasFP(MF) ? PPC::R31 : PPC::R1; 1602 else 1603 return hasFP(MF) ? PPC::X31 : PPC::X1; 1604 } 1605 1606 void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) 1607 const { 1608 // Initial state of the frame pointer is R1. 1609 MachineLocation Dst(MachineLocation::VirtualFP); 1610 MachineLocation Src(PPC::R1, 0); 1611 Moves.push_back(MachineMove(0, Dst, Src)); 1612 } 1613 1614 unsigned PPCRegisterInfo::getEHExceptionRegister() const { 1615 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3; 1616 } 1617 1618 unsigned PPCRegisterInfo::getEHHandlerRegister() const { 1619 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4; 1620 } 1621 1622 int PPCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { 1623 // FIXME: Most probably dwarf numbers differs for Linux and Darwin 1624 return PPCGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); 1625 } 1626 1627 #include "PPCGenRegisterInfo.inc" 1628