1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the TargetRegisterInfo 11 // class. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #define DEBUG_TYPE "reginfo" 16 #include "PPC.h" 17 #include "PPCInstrBuilder.h" 18 #include "PPCMachineFunctionInfo.h" 19 #include "PPCRegisterInfo.h" 20 #include "PPCFrameInfo.h" 21 #include "PPCSubtarget.h" 22 #include "llvm/Constants.h" 23 #include "llvm/Type.h" 24 #include "llvm/CodeGen/ValueTypes.h" 25 #include "llvm/CodeGen/MachineInstrBuilder.h" 26 #include "llvm/CodeGen/MachineModuleInfo.h" 27 #include "llvm/CodeGen/MachineFunction.h" 28 #include "llvm/CodeGen/MachineFrameInfo.h" 29 #include "llvm/CodeGen/MachineLocation.h" 30 #include "llvm/CodeGen/MachineRegisterInfo.h" 31 #include "llvm/CodeGen/RegisterScavenging.h" 32 #include "llvm/CodeGen/SelectionDAGNodes.h" 33 #include "llvm/Target/TargetFrameInfo.h" 34 #include "llvm/Target/TargetInstrInfo.h" 35 #include "llvm/Target/TargetMachine.h" 36 #include "llvm/Target/TargetOptions.h" 37 #include "llvm/Support/CommandLine.h" 38 #include "llvm/Support/Debug.h" 39 #include "llvm/Support/MathExtras.h" 40 #include "llvm/ADT/BitVector.h" 41 #include "llvm/ADT/STLExtras.h" 42 #include <cstdlib> 43 using namespace llvm; 44 45 // FIXME (64-bit): Eventually enable by default. 46 cl::opt<bool> EnablePPC32RS("enable-ppc32-regscavenger", 47 cl::init(false), 48 cl::desc("Enable PPC32 register scavenger"), 49 cl::Hidden); 50 cl::opt<bool> EnablePPC64RS("enable-ppc64-regscavenger", 51 cl::init(false), 52 cl::desc("Enable PPC64 register scavenger"), 53 cl::Hidden); 54 #define EnableRegisterScavenging \ 55 ((EnablePPC32RS && !Subtarget.isPPC64()) || \ 56 (EnablePPC64RS && Subtarget.isPPC64())) 57 58 // FIXME (64-bit): Should be inlined. 59 bool 60 PPCRegisterInfo::requiresRegisterScavenging(const MachineFunction &) const { 61 return EnableRegisterScavenging; 62 } 63 64 /// getRegisterNumbering - Given the enum value for some register, e.g. 65 /// PPC::F14, return the number that it corresponds to (e.g. 14). 66 unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) { 67 using namespace PPC; 68 switch (RegEnum) { 69 case 0: return 0; 70 case R0 : case X0 : case F0 : case V0 : case CR0: case CR0LT: return 0; 71 case R1 : case X1 : case F1 : case V1 : case CR1: case CR0GT: return 1; 72 case R2 : case X2 : case F2 : case V2 : case CR2: case CR0EQ: return 2; 73 case R3 : case X3 : case F3 : case V3 : case CR3: case CR0UN: return 3; 74 case R4 : case X4 : case F4 : case V4 : case CR4: case CR1LT: return 4; 75 case R5 : case X5 : case F5 : case V5 : case CR5: case CR1GT: return 5; 76 case R6 : case X6 : case F6 : case V6 : case CR6: case CR1EQ: return 6; 77 case R7 : case X7 : case F7 : case V7 : case CR7: case CR1UN: return 7; 78 case R8 : case X8 : case F8 : case V8 : case CR2LT: return 8; 79 case R9 : case X9 : case F9 : case V9 : case CR2GT: return 9; 80 case R10: case X10: case F10: case V10: case CR2EQ: return 10; 81 case R11: case X11: case F11: case V11: case CR2UN: return 11; 82 case R12: case X12: case F12: case V12: case CR3LT: return 12; 83 case R13: case X13: case F13: case V13: case CR3GT: return 13; 84 case R14: case X14: case F14: case V14: case CR3EQ: return 14; 85 case R15: case X15: case F15: case V15: case CR3UN: return 15; 86 case R16: case X16: case F16: case V16: case CR4LT: return 16; 87 case R17: case X17: case F17: case V17: case CR4GT: return 17; 88 case R18: case X18: case F18: case V18: case CR4EQ: return 18; 89 case R19: case X19: case F19: case V19: case CR4UN: return 19; 90 case R20: case X20: case F20: case V20: case CR5LT: return 20; 91 case R21: case X21: case F21: case V21: case CR5GT: return 21; 92 case R22: case X22: case F22: case V22: case CR5EQ: return 22; 93 case R23: case X23: case F23: case V23: case CR5UN: return 23; 94 case R24: case X24: case F24: case V24: case CR6LT: return 24; 95 case R25: case X25: case F25: case V25: case CR6GT: return 25; 96 case R26: case X26: case F26: case V26: case CR6EQ: return 26; 97 case R27: case X27: case F27: case V27: case CR6UN: return 27; 98 case R28: case X28: case F28: case V28: case CR7LT: return 28; 99 case R29: case X29: case F29: case V29: case CR7GT: return 29; 100 case R30: case X30: case F30: case V30: case CR7EQ: return 30; 101 case R31: case X31: case F31: case V31: case CR7UN: return 31; 102 default: 103 cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n"; 104 abort(); 105 } 106 } 107 108 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST, 109 const TargetInstrInfo &tii) 110 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP), 111 Subtarget(ST), TII(tii) { 112 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 113 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 114 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 115 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 116 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 117 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 118 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 119 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 120 121 // 64-bit 122 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8; 123 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8; 124 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8; 125 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX; 126 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32; 127 } 128 129 void PPCRegisterInfo::reMaterialize(MachineBasicBlock &MBB, 130 MachineBasicBlock::iterator I, 131 unsigned DestReg, 132 const MachineInstr *Orig) const { 133 MachineInstr *MI = Orig->clone(); 134 MI->getOperand(0).setReg(DestReg); 135 MBB.insert(I, MI); 136 } 137 138 const unsigned* 139 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 140 // 32-bit Darwin calling convention. 141 static const unsigned Macho32_CalleeSavedRegs[] = { 142 PPC::R13, PPC::R14, PPC::R15, 143 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 144 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 145 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 146 PPC::R28, PPC::R29, PPC::R30, PPC::R31, 147 148 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 149 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 150 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 151 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 152 PPC::F30, PPC::F31, 153 154 PPC::CR2, PPC::CR3, PPC::CR4, 155 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 156 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 157 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 158 159 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 160 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 161 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 162 163 PPC::LR, 0 164 }; 165 166 static const unsigned ELF32_CalleeSavedRegs[] = { 167 PPC::R13, PPC::R14, PPC::R15, 168 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 169 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 170 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 171 PPC::R28, PPC::R29, PPC::R30, PPC::R31, 172 173 PPC::F9, 174 PPC::F10, PPC::F11, PPC::F12, PPC::F13, 175 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 176 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 177 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 178 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 179 PPC::F30, PPC::F31, 180 181 PPC::CR2, PPC::CR3, PPC::CR4, 182 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 183 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 184 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 185 186 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 187 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 188 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 189 190 PPC::LR, 0 191 }; 192 // 64-bit Darwin calling convention. 193 static const unsigned Macho64_CalleeSavedRegs[] = { 194 PPC::X14, PPC::X15, 195 PPC::X16, PPC::X17, PPC::X18, PPC::X19, 196 PPC::X20, PPC::X21, PPC::X22, PPC::X23, 197 PPC::X24, PPC::X25, PPC::X26, PPC::X27, 198 PPC::X28, PPC::X29, PPC::X30, PPC::X31, 199 200 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 201 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 202 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 203 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 204 PPC::F30, PPC::F31, 205 206 PPC::CR2, PPC::CR3, PPC::CR4, 207 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 208 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 209 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 210 211 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 212 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 213 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 214 215 PPC::LR8, 0 216 }; 217 218 if (Subtarget.isMachoABI()) 219 return Subtarget.isPPC64() ? Macho64_CalleeSavedRegs : 220 Macho32_CalleeSavedRegs; 221 222 // ELF 32. 223 return ELF32_CalleeSavedRegs; 224 } 225 226 const TargetRegisterClass* const* 227 PPCRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const { 228 // 32-bit Macho calling convention. 229 static const TargetRegisterClass * const Macho32_CalleeSavedRegClasses[] = { 230 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 231 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 232 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 233 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 234 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 235 236 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 237 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 238 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 239 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 240 &PPC::F8RCRegClass,&PPC::F8RCRegClass, 241 242 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, 243 244 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 245 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 246 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 247 248 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 249 &PPC::CRBITRCRegClass, 250 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 251 &PPC::CRBITRCRegClass, 252 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 253 &PPC::CRBITRCRegClass, 254 255 &PPC::GPRCRegClass, 0 256 }; 257 258 static const TargetRegisterClass * const ELF32_CalleeSavedRegClasses[] = { 259 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 260 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 261 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 262 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 263 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 264 265 &PPC::F8RCRegClass, 266 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 267 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 268 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 269 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 270 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 271 &PPC::F8RCRegClass,&PPC::F8RCRegClass, 272 273 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, 274 275 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 276 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 277 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 278 279 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 280 &PPC::CRBITRCRegClass, 281 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 282 &PPC::CRBITRCRegClass, 283 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 284 &PPC::CRBITRCRegClass, 285 286 &PPC::GPRCRegClass, 0 287 }; 288 289 // 64-bit Macho calling convention. 290 static const TargetRegisterClass * const Macho64_CalleeSavedRegClasses[] = { 291 &PPC::G8RCRegClass,&PPC::G8RCRegClass, 292 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 293 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 294 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 295 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 296 297 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 298 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 299 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 300 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 301 &PPC::F8RCRegClass,&PPC::F8RCRegClass, 302 303 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, 304 305 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 306 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 307 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 308 309 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 310 &PPC::CRBITRCRegClass, 311 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 312 &PPC::CRBITRCRegClass, 313 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 314 &PPC::CRBITRCRegClass, 315 316 &PPC::G8RCRegClass, 0 317 }; 318 319 if (Subtarget.isMachoABI()) 320 return Subtarget.isPPC64() ? Macho64_CalleeSavedRegClasses : 321 Macho32_CalleeSavedRegClasses; 322 323 // ELF 32. 324 return ELF32_CalleeSavedRegClasses; 325 } 326 327 // needsFP - Return true if the specified function should have a dedicated frame 328 // pointer register. This is true if the function has variable sized allocas or 329 // if frame pointer elimination is disabled. 330 // 331 static bool needsFP(const MachineFunction &MF) { 332 const MachineFrameInfo *MFI = MF.getFrameInfo(); 333 return NoFramePointerElim || MFI->hasVarSizedObjects(); 334 } 335 336 static bool spillsCR(const MachineFunction &MF) { 337 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 338 return FuncInfo->isCRSpilled(); 339 } 340 341 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 342 BitVector Reserved(getNumRegs()); 343 Reserved.set(PPC::R0); 344 Reserved.set(PPC::R1); 345 Reserved.set(PPC::LR); 346 Reserved.set(PPC::LR8); 347 348 // In Linux, r2 is reserved for the OS. 349 if (!Subtarget.isDarwin()) 350 Reserved.set(PPC::R2); 351 352 // On PPC64, r13 is the thread pointer. Never allocate this register. Note 353 // that this is over conservative, as it also prevents allocation of R31 when 354 // the FP is not needed. 355 if (Subtarget.isPPC64()) { 356 Reserved.set(PPC::R13); 357 Reserved.set(PPC::R31); 358 359 if (!EnableRegisterScavenging) 360 Reserved.set(PPC::R0); // FIXME (64-bit): Remove 361 362 Reserved.set(PPC::X0); 363 Reserved.set(PPC::X1); 364 Reserved.set(PPC::X13); 365 Reserved.set(PPC::X31); 366 } 367 368 if (needsFP(MF)) 369 Reserved.set(PPC::R31); 370 371 return Reserved; 372 } 373 374 //===----------------------------------------------------------------------===// 375 // Stack Frame Processing methods 376 //===----------------------------------------------------------------------===// 377 378 // hasFP - Return true if the specified function actually has a dedicated frame 379 // pointer register. This is true if the function needs a frame pointer and has 380 // a non-zero stack size. 381 bool PPCRegisterInfo::hasFP(const MachineFunction &MF) const { 382 const MachineFrameInfo *MFI = MF.getFrameInfo(); 383 return MFI->getStackSize() && needsFP(MF); 384 } 385 386 /// MustSaveLR - Return true if this function requires that we save the LR 387 /// register onto the stack in the prolog and restore it in the epilog of the 388 /// function. 389 static bool MustSaveLR(const MachineFunction &MF) { 390 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>(); 391 392 // We need an save/restore of LR if there is any use/def of LR explicitly, or 393 // if there is some use of the LR stack slot (e.g. for builtin_return_address. 394 return MFI->usesLR() || MFI->isLRStoreRequired() || 395 // FIXME: Anything that has a call should clobber the LR register, 396 // isn't this redundant?? 397 MF.getFrameInfo()->hasCalls(); 398 } 399 400 void PPCRegisterInfo:: 401 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 402 MachineBasicBlock::iterator I) const { 403 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions. 404 MBB.erase(I); 405 } 406 407 /// findScratchRegister - Find a 'free' PPC register. Try for a call-clobbered 408 /// register first and then a spilled callee-saved register if that fails. 409 static 410 unsigned findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS, 411 const TargetRegisterClass *RC, int SPAdj) { 412 assert(RS && "Register scavenging must be on"); 413 unsigned Reg = RS->FindUnusedReg(RC, true); 414 // FIXME: move ARM callee-saved reg scan to target independent code, then 415 // search for already spilled CS register here. 416 if (Reg == 0) 417 Reg = RS->scavengeRegister(RC, II, SPAdj); 418 return Reg; 419 } 420 421 /// lowerDynamicAlloc - Generate the code for allocating an object in the 422 /// current frame. The sequence of code with be in the general form 423 /// 424 /// addi R0, SP, #frameSize ; get the address of the previous frame 425 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size 426 /// addi Rnew, SP, #maxCalFrameSize ; get the top of the allocation 427 /// 428 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II, 429 int SPAdj, RegScavenger *RS) const { 430 // Get the instruction. 431 MachineInstr &MI = *II; 432 // Get the instruction's basic block. 433 MachineBasicBlock &MBB = *MI.getParent(); 434 // Get the basic block's function. 435 MachineFunction &MF = *MBB.getParent(); 436 // Get the frame info. 437 MachineFrameInfo *MFI = MF.getFrameInfo(); 438 // Determine whether 64-bit pointers are used. 439 bool LP64 = Subtarget.isPPC64(); 440 441 // Get the maximum call stack size. 442 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 443 // Get the total frame size. 444 unsigned FrameSize = MFI->getStackSize(); 445 446 // Get stack alignments. 447 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 448 unsigned MaxAlign = MFI->getMaxAlignment(); 449 assert(MaxAlign <= TargetAlign && 450 "Dynamic alloca with large aligns not supported"); 451 452 // Determine the previous frame's address. If FrameSize can't be 453 // represented as 16 bits or we need special alignment, then we load the 454 // previous frame's address from 0(SP). Why not do an addis of the hi? 455 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. 456 // Constructing the constant and adding would take 3 instructions. 457 // Fortunately, a frame greater than 32K is rare. 458 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 459 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 460 const TargetRegisterClass *RC = LP64 ? G8RC : GPRC; 461 462 // FIXME (64-bit): Use "findScratchRegister" 463 unsigned Reg; 464 if (EnableRegisterScavenging) 465 Reg = findScratchRegister(II, RS, RC, SPAdj); 466 else 467 Reg = PPC::R0; 468 469 if (MaxAlign < TargetAlign && isInt16(FrameSize)) { 470 BuildMI(MBB, II, TII.get(PPC::ADDI), Reg) 471 .addReg(PPC::R31) 472 .addImm(FrameSize); 473 } else if (LP64) { 474 if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part. 475 BuildMI(MBB, II, TII.get(PPC::LD), Reg) 476 .addImm(0) 477 .addReg(PPC::X1); 478 else 479 BuildMI(MBB, II, TII.get(PPC::LD), PPC::X0) 480 .addImm(0) 481 .addReg(PPC::X1); 482 } else { 483 BuildMI(MBB, II, TII.get(PPC::LWZ), Reg) 484 .addImm(0) 485 .addReg(PPC::R1); 486 } 487 488 // Grow the stack and update the stack pointer link, then determine the 489 // address of new allocated space. 490 if (LP64) { 491 if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part. 492 BuildMI(MBB, II, TII.get(PPC::STDUX)) 493 .addReg(Reg, false, false, true) 494 .addReg(PPC::X1) 495 .addReg(MI.getOperand(1).getReg()); 496 else 497 BuildMI(MBB, II, TII.get(PPC::STDUX)) 498 .addReg(PPC::X0, false, false, true) 499 .addReg(PPC::X1) 500 .addReg(MI.getOperand(1).getReg()); 501 502 if (!MI.getOperand(1).isKill()) 503 BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 504 .addReg(PPC::X1) 505 .addImm(maxCallFrameSize); 506 else 507 // Implicitly kill the register. 508 BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 509 .addReg(PPC::X1) 510 .addImm(maxCallFrameSize) 511 .addReg(MI.getOperand(1).getReg(), false, true, true); 512 } else { 513 BuildMI(MBB, II, TII.get(PPC::STWUX)) 514 .addReg(Reg, false, false, true) 515 .addReg(PPC::R1) 516 .addReg(MI.getOperand(1).getReg()); 517 518 if (!MI.getOperand(1).isKill()) 519 BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 520 .addReg(PPC::R1) 521 .addImm(maxCallFrameSize); 522 else 523 // Implicitly kill the register. 524 BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 525 .addReg(PPC::R1) 526 .addImm(maxCallFrameSize) 527 .addReg(MI.getOperand(1).getReg(), false, true, true); 528 } 529 530 // Discard the DYNALLOC instruction. 531 MBB.erase(II); 532 } 533 534 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of 535 /// reserving a whole register (R0), we scrounge for one here. This generates 536 /// code like this: 537 /// 538 /// mfcr rA ; Move the conditional register into GPR rA. 539 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot. 540 /// stw rA, FI ; Store rA to the frame. 541 /// 542 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, 543 unsigned FrameIndex, int SPAdj, 544 RegScavenger *RS) const { 545 // Get the instruction. 546 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>, <FI> 547 // Get the instruction's basic block. 548 MachineBasicBlock &MBB = *MI.getParent(); 549 550 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 551 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 552 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC; 553 unsigned Reg = findScratchRegister(II, RS, RC, SPAdj); 554 555 // We need to store the CR in the low 4-bits of the saved value. First, issue 556 // an MFCR to save all of the CRBits. Add an implicit kill of the CR. 557 if (!MI.getOperand(0).isKill()) 558 BuildMI(MBB, II, TII.get(PPC::MFCR), Reg); 559 else 560 // Implicitly kill the CR register. 561 BuildMI(MBB, II, TII.get(PPC::MFCR), Reg) 562 .addReg(MI.getOperand(0).getReg(), false, true, true); 563 564 // If the saved register wasn't CR0, shift the bits left so that they are in 565 // CR0's slot. 566 unsigned SrcReg = MI.getOperand(0).getReg(); 567 if (SrcReg != PPC::CR0) 568 // rlwinm rA, rA, ShiftBits, 0, 31. 569 BuildMI(MBB, II, TII.get(PPC::RLWINM), Reg) 570 .addReg(Reg, false, false, true) 571 .addImm(PPCRegisterInfo::getRegisterNumbering(SrcReg) * 4) 572 .addImm(0) 573 .addImm(31); 574 575 addFrameReference(BuildMI(MBB, II, TII.get(PPC::STW)) 576 .addReg(Reg, false, false, MI.getOperand(1).getImm()), 577 FrameIndex); 578 579 // Discard the pseudo instruction. 580 MBB.erase(II); 581 } 582 583 void PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 584 int SPAdj, RegScavenger *RS) const { 585 assert(SPAdj == 0 && "Unexpected"); 586 587 // Get the instruction. 588 MachineInstr &MI = *II; 589 // Get the instruction's basic block. 590 MachineBasicBlock &MBB = *MI.getParent(); 591 // Get the basic block's function. 592 MachineFunction &MF = *MBB.getParent(); 593 // Get the frame info. 594 MachineFrameInfo *MFI = MF.getFrameInfo(); 595 596 // Find out which operand is the frame index. 597 unsigned FIOperandNo = 0; 598 while (!MI.getOperand(FIOperandNo).isFrameIndex()) { 599 ++FIOperandNo; 600 assert(FIOperandNo != MI.getNumOperands() && 601 "Instr doesn't have FrameIndex operand!"); 602 } 603 // Take into account whether it's an add or mem instruction 604 unsigned OffsetOperandNo = (FIOperandNo == 2) ? 1 : 2; 605 if (MI.getOpcode() == TargetInstrInfo::INLINEASM) 606 OffsetOperandNo = FIOperandNo-1; 607 608 // Get the frame index. 609 int FrameIndex = MI.getOperand(FIOperandNo).getIndex(); 610 611 // Get the frame pointer save index. Users of this index are primarily 612 // DYNALLOC instructions. 613 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 614 int FPSI = FI->getFramePointerSaveIndex(); 615 // Get the instruction opcode. 616 unsigned OpC = MI.getOpcode(); 617 618 // Special case for dynamic alloca. 619 if (FPSI && FrameIndex == FPSI && 620 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { 621 lowerDynamicAlloc(II, SPAdj, RS); 622 return; 623 } 624 625 // Special case for pseudo-op SPILL_CR. 626 if (EnableRegisterScavenging) // FIXME (64-bit): Enable by default. 627 if (OpC == PPC::SPILL_CR) { 628 lowerCRSpilling(II, FrameIndex, SPAdj, RS); 629 return; 630 } 631 632 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 633 MI.getOperand(FIOperandNo).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1, 634 false); 635 636 // Figure out if the offset in the instruction is shifted right two bits. This 637 // is true for instructions like "STD", which the machine implicitly adds two 638 // low zeros to. 639 bool isIXAddr = false; 640 switch (OpC) { 641 case PPC::LWA: 642 case PPC::LD: 643 case PPC::STD: 644 case PPC::STD_32: 645 isIXAddr = true; 646 break; 647 } 648 649 // Now add the frame object offset to the offset from r1. 650 int Offset = MFI->getObjectOffset(FrameIndex); 651 if (!isIXAddr) 652 Offset += MI.getOperand(OffsetOperandNo).getImm(); 653 else 654 Offset += MI.getOperand(OffsetOperandNo).getImm() << 2; 655 656 // If we're not using a Frame Pointer that has been set to the value of the 657 // SP before having the stack size subtracted from it, then add the stack size 658 // to Offset to get the correct offset. 659 Offset += MFI->getStackSize(); 660 661 // If we can, encode the offset directly into the instruction. If this is a 662 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If 663 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits 664 // clear can be encoded. This is extremely uncommon, because normally you 665 // only "std" to a stack slot that is at least 4-byte aligned, but it can 666 // happen in invalid code. 667 if (isInt16(Offset) && (!isIXAddr || (Offset & 3) == 0)) { 668 if (isIXAddr) 669 Offset >>= 2; // The actual encoded value has the low two bits zero. 670 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 671 return; 672 } 673 674 // The offset doesn't fit into a single register, scavenge one to build the 675 // offset in. 676 // FIXME: figure out what SPAdj is doing here. 677 678 // FIXME (64-bit): Use "findScratchRegister". 679 unsigned SReg; 680 if (EnableRegisterScavenging) 681 SReg = findScratchRegister(II, RS, &PPC::GPRCRegClass, SPAdj); 682 else 683 SReg = PPC::R0; 684 685 // Insert a set of rA with the full offset value before the ld, st, or add 686 BuildMI(MBB, II, TII.get(PPC::LIS), SReg) 687 .addImm(Offset >> 16); 688 BuildMI(MBB, II, TII.get(PPC::ORI), SReg) 689 .addReg(SReg, false, false, true) 690 .addImm(Offset); 691 692 // Convert into indexed form of the instruction: 693 // 694 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 695 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 696 unsigned OperandBase; 697 698 if (OpC != TargetInstrInfo::INLINEASM) { 699 assert(ImmToIdxMap.count(OpC) && 700 "No indexed form of load or store available!"); 701 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; 702 MI.setDesc(TII.get(NewOpcode)); 703 OperandBase = 1; 704 } else { 705 OperandBase = OffsetOperandNo; 706 } 707 708 unsigned StackReg = MI.getOperand(FIOperandNo).getReg(); 709 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false); 710 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false); 711 } 712 713 /// VRRegNo - Map from a numbered VR register to its enum value. 714 /// 715 static const unsigned short VRRegNo[] = { 716 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 , 717 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, 718 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, 719 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31 720 }; 721 722 /// RemoveVRSaveCode - We have found that this function does not need any code 723 /// to manipulate the VRSAVE register, even though it uses vector registers. 724 /// This can happen when the only registers used are known to be live in or out 725 /// of the function. Remove all of the VRSAVE related code from the function. 726 static void RemoveVRSaveCode(MachineInstr *MI) { 727 MachineBasicBlock *Entry = MI->getParent(); 728 MachineFunction *MF = Entry->getParent(); 729 730 // We know that the MTVRSAVE instruction immediately follows MI. Remove it. 731 MachineBasicBlock::iterator MBBI = MI; 732 ++MBBI; 733 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE); 734 MBBI->eraseFromParent(); 735 736 bool RemovedAllMTVRSAVEs = true; 737 // See if we can find and remove the MTVRSAVE instruction from all of the 738 // epilog blocks. 739 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) { 740 // If last instruction is a return instruction, add an epilogue 741 if (!I->empty() && I->back().getDesc().isReturn()) { 742 bool FoundIt = false; 743 for (MBBI = I->end(); MBBI != I->begin(); ) { 744 --MBBI; 745 if (MBBI->getOpcode() == PPC::MTVRSAVE) { 746 MBBI->eraseFromParent(); // remove it. 747 FoundIt = true; 748 break; 749 } 750 } 751 RemovedAllMTVRSAVEs &= FoundIt; 752 } 753 } 754 755 // If we found and removed all MTVRSAVE instructions, remove the read of 756 // VRSAVE as well. 757 if (RemovedAllMTVRSAVEs) { 758 MBBI = MI; 759 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?"); 760 --MBBI; 761 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?"); 762 MBBI->eraseFromParent(); 763 } 764 765 // Finally, nuke the UPDATE_VRSAVE. 766 MI->eraseFromParent(); 767 } 768 769 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the 770 // instruction selector. Based on the vector registers that have been used, 771 // transform this into the appropriate ORI instruction. 772 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) { 773 MachineFunction *MF = MI->getParent()->getParent(); 774 775 unsigned UsedRegMask = 0; 776 for (unsigned i = 0; i != 32; ++i) 777 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i])) 778 UsedRegMask |= 1 << (31-i); 779 780 // Live in and live out values already must be in the mask, so don't bother 781 // marking them. 782 for (MachineRegisterInfo::livein_iterator 783 I = MF->getRegInfo().livein_begin(), 784 E = MF->getRegInfo().livein_end(); I != E; ++I) { 785 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first); 786 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg. 787 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 788 } 789 for (MachineRegisterInfo::liveout_iterator 790 I = MF->getRegInfo().liveout_begin(), 791 E = MF->getRegInfo().liveout_end(); I != E; ++I) { 792 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I); 793 if (VRRegNo[RegNo] == *I) // If this really is a vector reg. 794 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 795 } 796 797 // If no registers are used, turn this into a copy. 798 if (UsedRegMask == 0) { 799 // Remove all VRSAVE code. 800 RemoveVRSaveCode(MI); 801 return; 802 } 803 804 unsigned SrcReg = MI->getOperand(1).getReg(); 805 unsigned DstReg = MI->getOperand(0).getReg(); 806 807 if ((UsedRegMask & 0xFFFF) == UsedRegMask) { 808 if (DstReg != SrcReg) 809 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg) 810 .addReg(SrcReg) 811 .addImm(UsedRegMask); 812 else 813 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg) 814 .addReg(SrcReg, false, false, true) 815 .addImm(UsedRegMask); 816 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { 817 if (DstReg != SrcReg) 818 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) 819 .addReg(SrcReg) 820 .addImm(UsedRegMask >> 16); 821 else 822 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) 823 .addReg(SrcReg, false, false, true) 824 .addImm(UsedRegMask >> 16); 825 } else { 826 if (DstReg != SrcReg) 827 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) 828 .addReg(SrcReg) 829 .addImm(UsedRegMask >> 16); 830 else 831 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) 832 .addReg(SrcReg, false, false, true) 833 .addImm(UsedRegMask >> 16); 834 835 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg) 836 .addReg(DstReg, false, false, true) 837 .addImm(UsedRegMask & 0xFFFF); 838 } 839 840 // Remove the old UPDATE_VRSAVE instruction. 841 MI->eraseFromParent(); 842 } 843 844 /// determineFrameLayout - Determine the size of the frame and maximum call 845 /// frame size. 846 void PPCRegisterInfo::determineFrameLayout(MachineFunction &MF) const { 847 MachineFrameInfo *MFI = MF.getFrameInfo(); 848 849 // Get the number of bytes to allocate from the FrameInfo 850 unsigned FrameSize = MFI->getStackSize(); 851 852 // Get the alignments provided by the target, and the maximum alignment 853 // (if any) of the fixed frame objects. 854 unsigned MaxAlign = MFI->getMaxAlignment(); 855 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 856 unsigned AlignMask = TargetAlign - 1; // 857 858 // If we are a leaf function, and use up to 224 bytes of stack space, 859 // don't have a frame pointer, calls, or dynamic alloca then we do not need 860 // to adjust the stack pointer (we fit in the Red Zone). 861 if (FrameSize <= 224 && // Fits in red zone. 862 !MFI->hasVarSizedObjects() && // No dynamic alloca. 863 !MFI->hasCalls() && // No calls. 864 MaxAlign <= TargetAlign) { // No special alignment. 865 // No need for frame 866 MFI->setStackSize(0); 867 return; 868 } 869 870 // Get the maximum call frame size of all the calls. 871 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 872 873 // Maximum call frame needs to be at least big enough for linkage and 8 args. 874 unsigned minCallFrameSize = 875 PPCFrameInfo::getMinCallFrameSize(Subtarget.isPPC64(), 876 Subtarget.isMachoABI()); 877 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize); 878 879 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so 880 // that allocations will be aligned. 881 if (MFI->hasVarSizedObjects()) 882 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask; 883 884 // Update maximum call frame size. 885 MFI->setMaxCallFrameSize(maxCallFrameSize); 886 887 // Include call frame size in total. 888 FrameSize += maxCallFrameSize; 889 890 // Make sure the frame is aligned. 891 FrameSize = (FrameSize + AlignMask) & ~AlignMask; 892 893 // Update frame info. 894 MFI->setStackSize(FrameSize); 895 } 896 897 void 898 PPCRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 899 RegScavenger *RS) const { 900 // Save and clear the LR state. 901 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 902 unsigned LR = getRARegister(); 903 FI->setUsesLR(MF.getRegInfo().isPhysRegUsed(LR)); 904 MF.getRegInfo().setPhysRegUnused(LR); 905 906 // Save R31 if necessary 907 int FPSI = FI->getFramePointerSaveIndex(); 908 bool IsPPC64 = Subtarget.isPPC64(); 909 bool IsELF32_ABI = Subtarget.isELF32_ABI(); 910 bool IsMachoABI = Subtarget.isMachoABI(); 911 MachineFrameInfo *MFI = MF.getFrameInfo(); 912 913 // If the frame pointer save index hasn't been defined yet. 914 if (!FPSI && (NoFramePointerElim || MFI->hasVarSizedObjects()) && 915 IsELF32_ABI) { 916 // Find out what the fix offset of the frame pointer save area. 917 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, 918 IsMachoABI); 919 // Allocate the frame index for frame pointer save area. 920 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset); 921 // Save the result. 922 FI->setFramePointerSaveIndex(FPSI); 923 } 924 925 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or 926 // a large stack, which will require scavenging a register to materialize a 927 // large offset. 928 // FIXME: this doesn't actually check stack size, so is a bit pessimistic 929 // FIXME: doesn't detect whether or not we need to spill vXX, which requires 930 // r0 for now. 931 932 if (EnableRegisterScavenging) // FIXME (64-bit): Enable. 933 if (needsFP(MF) || spillsCR(MF)) { 934 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 935 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 936 const TargetRegisterClass *RC = IsPPC64 ? G8RC : GPRC; 937 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 938 RC->getAlignment())); 939 } 940 } 941 942 void 943 PPCRegisterInfo::emitPrologue(MachineFunction &MF) const { 944 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB 945 MachineBasicBlock::iterator MBBI = MBB.begin(); 946 MachineFrameInfo *MFI = MF.getFrameInfo(); 947 MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); 948 949 // Prepare for frame info. 950 unsigned FrameLabelId = 0; 951 952 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it, 953 // process it. 954 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { 955 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) { 956 HandleVRSaveUpdate(MBBI, TII); 957 break; 958 } 959 } 960 961 // Move MBBI back to the beginning of the function. 962 MBBI = MBB.begin(); 963 964 // Work out frame sizes. 965 determineFrameLayout(MF); 966 unsigned FrameSize = MFI->getStackSize(); 967 968 int NegFrameSize = -FrameSize; 969 970 // Get processor type. 971 bool IsPPC64 = Subtarget.isPPC64(); 972 // Get operating system 973 bool IsMachoABI = Subtarget.isMachoABI(); 974 // Check if the link register (LR) has been used. 975 bool UsesLR = MustSaveLR(MF); 976 // Do we have a frame pointer for this function? 977 bool HasFP = hasFP(MF) && FrameSize; 978 979 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI); 980 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI); 981 982 if (IsPPC64) { 983 if (UsesLR) 984 BuildMI(MBB, MBBI, TII.get(PPC::MFLR8), PPC::X0); 985 986 if (HasFP) 987 BuildMI(MBB, MBBI, TII.get(PPC::STD)) 988 .addReg(PPC::X31) 989 .addImm(FPOffset/4) 990 .addReg(PPC::X1); 991 992 if (UsesLR) 993 BuildMI(MBB, MBBI, TII.get(PPC::STD)) 994 .addReg(PPC::X0) 995 .addImm(LROffset / 4) 996 .addReg(PPC::X1); 997 } else { 998 if (UsesLR) 999 BuildMI(MBB, MBBI, TII.get(PPC::MFLR), PPC::R0); 1000 1001 if (HasFP) 1002 BuildMI(MBB, MBBI, TII.get(PPC::STW)) 1003 .addReg(PPC::R31) 1004 .addImm(FPOffset) 1005 .addReg(PPC::R1); 1006 1007 if (UsesLR) 1008 BuildMI(MBB, MBBI, TII.get(PPC::STW)) 1009 .addReg(PPC::R0) 1010 .addImm(LROffset) 1011 .addReg(PPC::R1); 1012 } 1013 1014 // Skip if a leaf routine. 1015 if (!FrameSize) return; 1016 1017 // Get stack alignments. 1018 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 1019 unsigned MaxAlign = MFI->getMaxAlignment(); 1020 1021 if (MMI && MMI->needsFrameInfo()) { 1022 // Mark effective beginning of when frame pointer becomes valid. 1023 FrameLabelId = MMI->NextLabelID(); 1024 BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(FrameLabelId).addImm(0); 1025 } 1026 1027 // Adjust stack pointer: r1 += NegFrameSize. 1028 // If there is a preferred stack alignment, align R1 now 1029 if (!IsPPC64) { 1030 // PPC32. 1031 if (MaxAlign > TargetAlign) { 1032 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!"); 1033 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!"); 1034 1035 BuildMI(MBB, MBBI, TII.get(PPC::RLWINM), PPC::R0) 1036 .addReg(PPC::R1) 1037 .addImm(0) 1038 .addImm(32 - Log2_32(MaxAlign)) 1039 .addImm(31); 1040 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC) ,PPC::R0) 1041 .addReg(PPC::R0, false, false, true) 1042 .addImm(NegFrameSize); 1043 BuildMI(MBB, MBBI, TII.get(PPC::STWUX)) 1044 .addReg(PPC::R1) 1045 .addReg(PPC::R1) 1046 .addReg(PPC::R0); 1047 } else if (isInt16(NegFrameSize)) { 1048 BuildMI(MBB, MBBI, TII.get(PPC::STWU), PPC::R1) 1049 .addReg(PPC::R1) 1050 .addImm(NegFrameSize) 1051 .addReg(PPC::R1); 1052 } else { 1053 BuildMI(MBB, MBBI, TII.get(PPC::LIS), PPC::R0) 1054 .addImm(NegFrameSize >> 16); 1055 BuildMI(MBB, MBBI, TII.get(PPC::ORI), PPC::R0) 1056 .addReg(PPC::R0, false, false, true) 1057 .addImm(NegFrameSize & 0xFFFF); 1058 BuildMI(MBB, MBBI, TII.get(PPC::STWUX)) 1059 .addReg(PPC::R1) 1060 .addReg(PPC::R1) 1061 .addReg(PPC::R0); 1062 } 1063 } else { // PPC64. 1064 if (MaxAlign > TargetAlign) { 1065 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!"); 1066 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!"); 1067 1068 BuildMI(MBB, MBBI, TII.get(PPC::RLDICL), PPC::X0) 1069 .addReg(PPC::X1) 1070 .addImm(0) 1071 .addImm(64 - Log2_32(MaxAlign)); 1072 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC8), PPC::X0) 1073 .addReg(PPC::X0) 1074 .addImm(NegFrameSize); 1075 BuildMI(MBB, MBBI, TII.get(PPC::STDUX)) 1076 .addReg(PPC::X1) 1077 .addReg(PPC::X1) 1078 .addReg(PPC::X0); 1079 } else if (isInt16(NegFrameSize)) { 1080 BuildMI(MBB, MBBI, TII.get(PPC::STDU), PPC::X1) 1081 .addReg(PPC::X1) 1082 .addImm(NegFrameSize / 4) 1083 .addReg(PPC::X1); 1084 } else { 1085 BuildMI(MBB, MBBI, TII.get(PPC::LIS8), PPC::X0) 1086 .addImm(NegFrameSize >> 16); 1087 BuildMI(MBB, MBBI, TII.get(PPC::ORI8), PPC::X0) 1088 .addReg(PPC::X0, false, false, true) 1089 .addImm(NegFrameSize & 0xFFFF); 1090 BuildMI(MBB, MBBI, TII.get(PPC::STDUX)) 1091 .addReg(PPC::X1) 1092 .addReg(PPC::X1) 1093 .addReg(PPC::X0); 1094 } 1095 } 1096 1097 if (MMI && MMI->needsFrameInfo()) { 1098 std::vector<MachineMove> &Moves = MMI->getFrameMoves(); 1099 1100 if (NegFrameSize) { 1101 // Show update of SP. 1102 MachineLocation SPDst(MachineLocation::VirtualFP); 1103 MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize); 1104 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc)); 1105 } else { 1106 MachineLocation SP(IsPPC64 ? PPC::X31 : PPC::R31); 1107 Moves.push_back(MachineMove(FrameLabelId, SP, SP)); 1108 } 1109 1110 if (HasFP) { 1111 MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset); 1112 MachineLocation FPSrc(IsPPC64 ? PPC::X31 : PPC::R31); 1113 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc)); 1114 } 1115 1116 // Add callee saved registers to move list. 1117 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 1118 for (unsigned I = 0, E = CSI.size(); I != E; ++I) { 1119 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx()); 1120 unsigned Reg = CSI[I].getReg(); 1121 if (Reg == PPC::LR || Reg == PPC::LR8) continue; 1122 MachineLocation CSDst(MachineLocation::VirtualFP, Offset); 1123 MachineLocation CSSrc(Reg); 1124 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc)); 1125 } 1126 1127 MachineLocation LRDst(MachineLocation::VirtualFP, LROffset); 1128 MachineLocation LRSrc(IsPPC64 ? PPC::LR8 : PPC::LR); 1129 Moves.push_back(MachineMove(FrameLabelId, LRDst, LRSrc)); 1130 1131 // Mark effective beginning of when frame pointer is ready. 1132 unsigned ReadyLabelId = MMI->NextLabelID(); 1133 BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(ReadyLabelId).addImm(0); 1134 1135 MachineLocation FPDst(HasFP ? (IsPPC64 ? PPC::X31 : PPC::R31) : 1136 (IsPPC64 ? PPC::X1 : PPC::R1)); 1137 MachineLocation FPSrc(MachineLocation::VirtualFP); 1138 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc)); 1139 } 1140 1141 // If there is a frame pointer, copy R1 into R31 1142 if (HasFP) { 1143 if (!IsPPC64) { 1144 BuildMI(MBB, MBBI, TII.get(PPC::OR), PPC::R31) 1145 .addReg(PPC::R1) 1146 .addReg(PPC::R1); 1147 } else { 1148 BuildMI(MBB, MBBI, TII.get(PPC::OR8), PPC::X31) 1149 .addReg(PPC::X1) 1150 .addReg(PPC::X1); 1151 } 1152 } 1153 } 1154 1155 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF, 1156 MachineBasicBlock &MBB) const { 1157 MachineBasicBlock::iterator MBBI = prior(MBB.end()); 1158 assert(MBBI->getOpcode() == PPC::BLR && 1159 "Can only insert epilog into returning blocks"); 1160 1161 // Get alignment info so we know how to restore r1 1162 const MachineFrameInfo *MFI = MF.getFrameInfo(); 1163 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 1164 unsigned MaxAlign = MFI->getMaxAlignment(); 1165 1166 // Get the number of bytes allocated from the FrameInfo. 1167 unsigned FrameSize = MFI->getStackSize(); 1168 1169 // Get processor type. 1170 bool IsPPC64 = Subtarget.isPPC64(); 1171 // Get operating system 1172 bool IsMachoABI = Subtarget.isMachoABI(); 1173 // Check if the link register (LR) has been used. 1174 bool UsesLR = MustSaveLR(MF); 1175 // Do we have a frame pointer for this function? 1176 bool HasFP = hasFP(MF) && FrameSize; 1177 1178 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI); 1179 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI); 1180 1181 if (FrameSize) { 1182 // The loaded (or persistent) stack pointer value is offset by the 'stwu' 1183 // on entry to the function. Add this offset back now. 1184 if (!Subtarget.isPPC64()) { 1185 if (isInt16(FrameSize) && TargetAlign >= MaxAlign && 1186 !MFI->hasVarSizedObjects()) { 1187 BuildMI(MBB, MBBI, TII.get(PPC::ADDI), PPC::R1) 1188 .addReg(PPC::R1).addImm(FrameSize); 1189 } else { 1190 BuildMI(MBB, MBBI, TII.get(PPC::LWZ),PPC::R1).addImm(0).addReg(PPC::R1); 1191 } 1192 } else { 1193 if (isInt16(FrameSize) && TargetAlign >= MaxAlign && 1194 !MFI->hasVarSizedObjects()) { 1195 BuildMI(MBB, MBBI, TII.get(PPC::ADDI8), PPC::X1) 1196 .addReg(PPC::X1).addImm(FrameSize); 1197 } else { 1198 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X1).addImm(0).addReg(PPC::X1); 1199 } 1200 } 1201 } 1202 1203 if (IsPPC64) { 1204 if (UsesLR) 1205 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X0) 1206 .addImm(LROffset/4).addReg(PPC::X1); 1207 1208 if (HasFP) 1209 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X31) 1210 .addImm(FPOffset/4).addReg(PPC::X1); 1211 1212 if (UsesLR) 1213 BuildMI(MBB, MBBI, TII.get(PPC::MTLR8)).addReg(PPC::X0); 1214 } else { 1215 if (UsesLR) 1216 BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R0) 1217 .addImm(LROffset).addReg(PPC::R1); 1218 1219 if (HasFP) 1220 BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R31) 1221 .addImm(FPOffset).addReg(PPC::R1); 1222 1223 if (UsesLR) 1224 BuildMI(MBB, MBBI, TII.get(PPC::MTLR)).addReg(PPC::R0); 1225 } 1226 } 1227 1228 unsigned PPCRegisterInfo::getRARegister() const { 1229 return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8; 1230 } 1231 1232 unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const { 1233 if (!Subtarget.isPPC64()) 1234 return hasFP(MF) ? PPC::R31 : PPC::R1; 1235 else 1236 return hasFP(MF) ? PPC::X31 : PPC::X1; 1237 } 1238 1239 void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) 1240 const { 1241 // Initial state of the frame pointer is R1. 1242 MachineLocation Dst(MachineLocation::VirtualFP); 1243 MachineLocation Src(PPC::R1, 0); 1244 Moves.push_back(MachineMove(0, Dst, Src)); 1245 } 1246 1247 unsigned PPCRegisterInfo::getEHExceptionRegister() const { 1248 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3; 1249 } 1250 1251 unsigned PPCRegisterInfo::getEHHandlerRegister() const { 1252 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4; 1253 } 1254 1255 int PPCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { 1256 // FIXME: Most probably dwarf numbers differs for Linux and Darwin 1257 return PPCGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); 1258 } 1259 1260 #include "PPCGenRegisterInfo.inc" 1261 1262