1 //===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the TargetRegisterInfo 11 // class. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #define DEBUG_TYPE "reginfo" 16 #include "PPCRegisterInfo.h" 17 #include "PPC.h" 18 #include "PPCFrameLowering.h" 19 #include "PPCInstrBuilder.h" 20 #include "PPCMachineFunctionInfo.h" 21 #include "PPCSubtarget.h" 22 #include "llvm/ADT/BitVector.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/CodeGen/MachineFrameInfo.h" 25 #include "llvm/CodeGen/MachineFunction.h" 26 #include "llvm/CodeGen/MachineInstrBuilder.h" 27 #include "llvm/CodeGen/MachineModuleInfo.h" 28 #include "llvm/CodeGen/MachineRegisterInfo.h" 29 #include "llvm/CodeGen/RegisterScavenging.h" 30 #include "llvm/CodeGen/ValueTypes.h" 31 #include "llvm/IR/CallingConv.h" 32 #include "llvm/IR/Constants.h" 33 #include "llvm/IR/Function.h" 34 #include "llvm/IR/Type.h" 35 #include "llvm/Support/CommandLine.h" 36 #include "llvm/Support/Debug.h" 37 #include "llvm/Support/ErrorHandling.h" 38 #include "llvm/Support/MathExtras.h" 39 #include "llvm/Support/raw_ostream.h" 40 #include "llvm/Target/TargetFrameLowering.h" 41 #include "llvm/Target/TargetInstrInfo.h" 42 #include "llvm/Target/TargetMachine.h" 43 #include "llvm/Target/TargetOptions.h" 44 #include <cstdlib> 45 46 #define GET_REGINFO_TARGET_DESC 47 #include "PPCGenRegisterInfo.inc" 48 49 namespace llvm { 50 cl::opt<bool> DisablePPC32RS("disable-ppc32-regscavenger", 51 cl::init(false), 52 cl::desc("Disable PPC32 register scavenger"), 53 cl::Hidden); 54 cl::opt<bool> DisablePPC64RS("disable-ppc64-regscavenger", 55 cl::init(false), 56 cl::desc("Disable PPC64 register scavenger"), 57 cl::Hidden); 58 } 59 60 using namespace llvm; 61 62 // FIXME (64-bit): Should be inlined. 63 bool 64 PPCRegisterInfo::requiresRegisterScavenging(const MachineFunction &) const { 65 return ((!DisablePPC32RS && !Subtarget.isPPC64()) || 66 (!DisablePPC64RS && Subtarget.isPPC64())); 67 } 68 69 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST, 70 const TargetInstrInfo &tii) 71 : PPCGenRegisterInfo(ST.isPPC64() ? PPC::LR8 : PPC::LR, 72 ST.isPPC64() ? 0 : 1, 73 ST.isPPC64() ? 0 : 1), 74 Subtarget(ST), TII(tii) { 75 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 76 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 77 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 78 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 79 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 80 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 81 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 82 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 83 84 // 64-bit 85 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8; 86 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8; 87 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8; 88 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX; 89 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32; 90 } 91 92 bool 93 PPCRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const { 94 return requiresRegisterScavenging(MF); 95 } 96 97 98 /// getPointerRegClass - Return the register class to use to hold pointers. 99 /// This is used for addressing modes. 100 const TargetRegisterClass * 101 PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) 102 const { 103 if (Subtarget.isPPC64()) 104 return &PPC::G8RCRegClass; 105 return &PPC::GPRCRegClass; 106 } 107 108 const uint16_t* 109 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 110 if (Subtarget.isDarwinABI()) 111 return Subtarget.isPPC64() ? CSR_Darwin64_SaveList : 112 CSR_Darwin32_SaveList; 113 114 return Subtarget.isPPC64() ? CSR_SVR464_SaveList : CSR_SVR432_SaveList; 115 } 116 117 const uint32_t* 118 PPCRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const { 119 if (Subtarget.isDarwinABI()) 120 return Subtarget.isPPC64() ? CSR_Darwin64_RegMask : 121 CSR_Darwin32_RegMask; 122 123 return Subtarget.isPPC64() ? CSR_SVR464_RegMask : CSR_SVR432_RegMask; 124 } 125 126 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 127 BitVector Reserved(getNumRegs()); 128 const PPCFrameLowering *PPCFI = 129 static_cast<const PPCFrameLowering*>(MF.getTarget().getFrameLowering()); 130 131 Reserved.set(PPC::R0); 132 Reserved.set(PPC::R1); 133 Reserved.set(PPC::LR); 134 Reserved.set(PPC::LR8); 135 Reserved.set(PPC::RM); 136 137 // The SVR4 ABI reserves r2 and r13 138 if (Subtarget.isSVR4ABI()) { 139 Reserved.set(PPC::R2); // System-reserved register 140 Reserved.set(PPC::R13); // Small Data Area pointer register 141 } 142 // Reserve R2 on Darwin to hack around the problem of save/restore of CR 143 // when the stack frame is too big to address directly; we need two regs. 144 // This is a hack. 145 if (Subtarget.isDarwinABI()) { 146 Reserved.set(PPC::R2); 147 } 148 149 // On PPC64, r13 is the thread pointer. Never allocate this register. 150 // Note that this is over conservative, as it also prevents allocation of R31 151 // when the FP is not needed. 152 if (Subtarget.isPPC64()) { 153 Reserved.set(PPC::R13); 154 Reserved.set(PPC::R31); 155 156 Reserved.set(PPC::X0); 157 Reserved.set(PPC::X1); 158 Reserved.set(PPC::X13); 159 Reserved.set(PPC::X31); 160 161 // The 64-bit SVR4 ABI reserves r2 for the TOC pointer. 162 if (Subtarget.isSVR4ABI()) { 163 Reserved.set(PPC::X2); 164 } 165 // Reserve X2 on Darwin to hack around the problem of save/restore of CR 166 // when the stack frame is too big to address directly; we need two regs. 167 // This is a hack. 168 if (Subtarget.isDarwinABI()) { 169 Reserved.set(PPC::X2); 170 } 171 } 172 173 if (PPCFI->needsFP(MF)) 174 Reserved.set(PPC::R31); 175 176 return Reserved; 177 } 178 179 unsigned 180 PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 181 MachineFunction &MF) const { 182 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 183 const unsigned DefaultSafety = 1; 184 185 switch (RC->getID()) { 186 default: 187 return 0; 188 case PPC::G8RCRegClassID: 189 case PPC::GPRCRegClassID: { 190 unsigned FP = TFI->hasFP(MF) ? 1 : 0; 191 return 32 - FP - DefaultSafety; 192 } 193 case PPC::F8RCRegClassID: 194 case PPC::F4RCRegClassID: 195 case PPC::VRRCRegClassID: 196 return 32 - DefaultSafety; 197 case PPC::CRRCRegClassID: 198 return 8 - DefaultSafety; 199 } 200 } 201 202 bool 203 PPCRegisterInfo::avoidWriteAfterWrite(const TargetRegisterClass *RC) const { 204 switch (RC->getID()) { 205 case PPC::G8RCRegClassID: 206 case PPC::GPRCRegClassID: 207 case PPC::F8RCRegClassID: 208 case PPC::F4RCRegClassID: 209 case PPC::VRRCRegClassID: 210 return true; 211 default: 212 return false; 213 } 214 } 215 216 //===----------------------------------------------------------------------===// 217 // Stack Frame Processing methods 218 //===----------------------------------------------------------------------===// 219 220 /// findScratchRegister - Find a 'free' PPC register. Try for a call-clobbered 221 /// register first and then a spilled callee-saved register if that fails. 222 static 223 unsigned findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS, 224 const TargetRegisterClass *RC, int SPAdj) { 225 assert(RS && "Register scavenging must be on"); 226 unsigned Reg = RS->FindUnusedReg(RC); 227 // FIXME: move ARM callee-saved reg scan to target independent code, then 228 // search for already spilled CS register here. 229 if (Reg == 0) 230 Reg = RS->scavengeRegister(RC, II, SPAdj); 231 return Reg; 232 } 233 234 /// lowerDynamicAlloc - Generate the code for allocating an object in the 235 /// current frame. The sequence of code with be in the general form 236 /// 237 /// addi R0, SP, \#frameSize ; get the address of the previous frame 238 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size 239 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation 240 /// 241 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II, 242 int SPAdj, RegScavenger *RS) const { 243 // Get the instruction. 244 MachineInstr &MI = *II; 245 // Get the instruction's basic block. 246 MachineBasicBlock &MBB = *MI.getParent(); 247 // Get the basic block's function. 248 MachineFunction &MF = *MBB.getParent(); 249 // Get the frame info. 250 MachineFrameInfo *MFI = MF.getFrameInfo(); 251 // Determine whether 64-bit pointers are used. 252 bool LP64 = Subtarget.isPPC64(); 253 DebugLoc dl = MI.getDebugLoc(); 254 255 // Get the maximum call stack size. 256 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 257 // Get the total frame size. 258 unsigned FrameSize = MFI->getStackSize(); 259 260 // Get stack alignments. 261 unsigned TargetAlign = MF.getTarget().getFrameLowering()->getStackAlignment(); 262 unsigned MaxAlign = MFI->getMaxAlignment(); 263 if (MaxAlign > TargetAlign) 264 report_fatal_error("Dynamic alloca with large aligns not supported"); 265 266 // Determine the previous frame's address. If FrameSize can't be 267 // represented as 16 bits or we need special alignment, then we load the 268 // previous frame's address from 0(SP). Why not do an addis of the hi? 269 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. 270 // Constructing the constant and adding would take 3 instructions. 271 // Fortunately, a frame greater than 32K is rare. 272 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 273 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 274 const TargetRegisterClass *RC = LP64 ? G8RC : GPRC; 275 276 // FIXME (64-bit): Use "findScratchRegister" 277 unsigned Reg; 278 if (requiresRegisterScavenging(MF)) 279 Reg = findScratchRegister(II, RS, RC, SPAdj); 280 else 281 Reg = PPC::R0; 282 283 if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) { 284 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) 285 .addReg(PPC::R31) 286 .addImm(FrameSize); 287 } else if (LP64) { 288 if (requiresRegisterScavenging(MF)) // FIXME (64-bit): Use "true" part. 289 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg) 290 .addImm(0) 291 .addReg(PPC::X1); 292 else 293 BuildMI(MBB, II, dl, TII.get(PPC::LD), PPC::X0) 294 .addImm(0) 295 .addReg(PPC::X1); 296 } else { 297 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) 298 .addImm(0) 299 .addReg(PPC::R1); 300 } 301 302 // Grow the stack and update the stack pointer link, then determine the 303 // address of new allocated space. 304 if (LP64) { 305 if (requiresRegisterScavenging(MF)) // FIXME (64-bit): Use "true" part. 306 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1) 307 .addReg(Reg, RegState::Kill) 308 .addReg(PPC::X1) 309 .addReg(MI.getOperand(1).getReg()); 310 else 311 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1) 312 .addReg(PPC::X0, RegState::Kill) 313 .addReg(PPC::X1) 314 .addReg(MI.getOperand(1).getReg()); 315 316 if (!MI.getOperand(1).isKill()) 317 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 318 .addReg(PPC::X1) 319 .addImm(maxCallFrameSize); 320 else 321 // Implicitly kill the register. 322 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 323 .addReg(PPC::X1) 324 .addImm(maxCallFrameSize) 325 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill); 326 } else { 327 BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1) 328 .addReg(Reg, RegState::Kill) 329 .addReg(PPC::R1) 330 .addReg(MI.getOperand(1).getReg()); 331 332 if (!MI.getOperand(1).isKill()) 333 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 334 .addReg(PPC::R1) 335 .addImm(maxCallFrameSize); 336 else 337 // Implicitly kill the register. 338 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 339 .addReg(PPC::R1) 340 .addImm(maxCallFrameSize) 341 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill); 342 } 343 344 // Discard the DYNALLOC instruction. 345 MBB.erase(II); 346 } 347 348 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of 349 /// reserving a whole register (R0), we scrounge for one here. This generates 350 /// code like this: 351 /// 352 /// mfcr rA ; Move the conditional register into GPR rA. 353 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot. 354 /// stw rA, FI ; Store rA to the frame. 355 /// 356 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, 357 unsigned FrameIndex, int SPAdj, 358 RegScavenger *RS) const { 359 // Get the instruction. 360 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset> 361 // Get the instruction's basic block. 362 MachineBasicBlock &MBB = *MI.getParent(); 363 DebugLoc dl = MI.getDebugLoc(); 364 365 // FIXME: Once LLVM supports creating virtual registers here, or the register 366 // scavenger can return multiple registers, stop using reserved registers 367 // here. 368 (void) SPAdj; 369 (void) RS; 370 371 bool LP64 = Subtarget.isPPC64(); 372 unsigned Reg = Subtarget.isDarwinABI() ? (LP64 ? PPC::X2 : PPC::R2) : 373 (LP64 ? PPC::X0 : PPC::R0); 374 unsigned SrcReg = MI.getOperand(0).getReg(); 375 376 // We need to store the CR in the low 4-bits of the saved value. First, issue 377 // an MFCRpsued to save all of the CRBits and, if needed, kill the SrcReg. 378 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFCR8pseud : PPC::MFCRpseud), Reg) 379 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 380 381 // If the saved register wasn't CR0, shift the bits left so that they are in 382 // CR0's slot. 383 if (SrcReg != PPC::CR0) 384 // rlwinm rA, rA, ShiftBits, 0, 31. 385 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 386 .addReg(Reg, RegState::Kill) 387 .addImm(getPPCRegisterNumbering(SrcReg) * 4) 388 .addImm(0) 389 .addImm(31); 390 391 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW)) 392 .addReg(Reg, getKillRegState(MI.getOperand(1).getImm())), 393 FrameIndex); 394 395 // Discard the pseudo instruction. 396 MBB.erase(II); 397 } 398 399 void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II, 400 unsigned FrameIndex, int SPAdj, 401 RegScavenger *RS) const { 402 // Get the instruction. 403 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset> 404 // Get the instruction's basic block. 405 MachineBasicBlock &MBB = *MI.getParent(); 406 DebugLoc dl = MI.getDebugLoc(); 407 408 // FIXME: Once LLVM supports creating virtual registers here, or the register 409 // scavenger can return multiple registers, stop using reserved registers 410 // here. 411 (void) SPAdj; 412 (void) RS; 413 414 bool LP64 = Subtarget.isPPC64(); 415 unsigned Reg = Subtarget.isDarwinABI() ? (LP64 ? PPC::X2 : PPC::R2) : 416 (LP64 ? PPC::X0 : PPC::R0); 417 unsigned DestReg = MI.getOperand(0).getReg(); 418 assert(MI.definesRegister(DestReg) && 419 "RESTORE_CR does not define its destination"); 420 421 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), 422 Reg), FrameIndex); 423 424 // If the reloaded register isn't CR0, shift the bits right so that they are 425 // in the right CR's slot. 426 if (DestReg != PPC::CR0) { 427 unsigned ShiftBits = getPPCRegisterNumbering(DestReg)*4; 428 // rlwinm r11, r11, 32-ShiftBits, 0, 31. 429 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 430 .addReg(Reg).addImm(32-ShiftBits).addImm(0) 431 .addImm(31); 432 } 433 434 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTCRF8 : PPC::MTCRF), DestReg) 435 .addReg(Reg); 436 437 // Discard the pseudo instruction. 438 MBB.erase(II); 439 } 440 441 bool 442 PPCRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF, 443 unsigned Reg, int &FrameIdx) const { 444 445 // For the nonvolatile condition registers (CR2, CR3, CR4) in an SVR4 446 // ABI, return true to prevent allocating an additional frame slot. 447 // For 64-bit, the CR save area is at SP+8; the value of FrameIdx = 0 448 // is arbitrary and will be subsequently ignored. For 32-bit, we have 449 // previously created the stack slot if needed, so return its FrameIdx. 450 if (Subtarget.isSVR4ABI() && PPC::CR2 <= Reg && Reg <= PPC::CR4) { 451 if (Subtarget.isPPC64()) 452 FrameIdx = 0; 453 else { 454 const PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 455 FrameIdx = FI->getCRSpillFrameIndex(); 456 } 457 return true; 458 } 459 return false; 460 } 461 462 void 463 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 464 int SPAdj, unsigned FIOperandNum, 465 RegScavenger *RS) const { 466 assert(SPAdj == 0 && "Unexpected"); 467 468 // Get the instruction. 469 MachineInstr &MI = *II; 470 // Get the instruction's basic block. 471 MachineBasicBlock &MBB = *MI.getParent(); 472 // Get the basic block's function. 473 MachineFunction &MF = *MBB.getParent(); 474 // Get the frame info. 475 MachineFrameInfo *MFI = MF.getFrameInfo(); 476 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 477 DebugLoc dl = MI.getDebugLoc(); 478 479 // Take into account whether it's an add or mem instruction 480 unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2; 481 if (MI.isInlineAsm()) 482 OffsetOperandNo = FIOperandNum-1; 483 484 // Get the frame index. 485 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 486 487 // Get the frame pointer save index. Users of this index are primarily 488 // DYNALLOC instructions. 489 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 490 int FPSI = FI->getFramePointerSaveIndex(); 491 // Get the instruction opcode. 492 unsigned OpC = MI.getOpcode(); 493 494 // Special case for dynamic alloca. 495 if (FPSI && FrameIndex == FPSI && 496 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { 497 lowerDynamicAlloc(II, SPAdj, RS); 498 return; 499 } 500 501 // Special case for pseudo-ops SPILL_CR and RESTORE_CR. 502 if (requiresRegisterScavenging(MF)) { 503 if (OpC == PPC::SPILL_CR) { 504 lowerCRSpilling(II, FrameIndex, SPAdj, RS); 505 return; 506 } else if (OpC == PPC::RESTORE_CR) { 507 lowerCRRestore(II, FrameIndex, SPAdj, RS); 508 return; 509 } 510 } 511 512 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 513 514 bool is64Bit = Subtarget.isPPC64(); 515 MI.getOperand(FIOperandNum).ChangeToRegister(TFI->hasFP(MF) ? 516 (is64Bit ? PPC::X31 : PPC::R31) : 517 (is64Bit ? PPC::X1 : PPC::R1), 518 false); 519 520 // Figure out if the offset in the instruction is shifted right two bits. This 521 // is true for instructions like "STD", which the machine implicitly adds two 522 // low zeros to. 523 bool isIXAddr = false; 524 switch (OpC) { 525 case PPC::LWA: 526 case PPC::LD: 527 case PPC::STD: 528 case PPC::STD_32: 529 isIXAddr = true; 530 break; 531 } 532 533 // Now add the frame object offset to the offset from r1. 534 int Offset = MFI->getObjectOffset(FrameIndex); 535 if (!isIXAddr) 536 Offset += MI.getOperand(OffsetOperandNo).getImm(); 537 else 538 Offset += MI.getOperand(OffsetOperandNo).getImm() << 2; 539 540 // If we're not using a Frame Pointer that has been set to the value of the 541 // SP before having the stack size subtracted from it, then add the stack size 542 // to Offset to get the correct offset. 543 // Naked functions have stack size 0, although getStackSize may not reflect that 544 // because we didn't call all the pieces that compute it for naked functions. 545 if (!MF.getFunction()->getAttributes(). 546 hasAttribute(AttributeSet::FunctionIndex, Attribute::Naked)) 547 Offset += MFI->getStackSize(); 548 549 // If we can, encode the offset directly into the instruction. If this is a 550 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If 551 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits 552 // clear can be encoded. This is extremely uncommon, because normally you 553 // only "std" to a stack slot that is at least 4-byte aligned, but it can 554 // happen in invalid code. 555 if (OpC == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm 556 (isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0))) { 557 if (isIXAddr) 558 Offset >>= 2; // The actual encoded value has the low two bits zero. 559 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 560 return; 561 } 562 563 // The offset doesn't fit into a single register, scavenge one to build the 564 // offset in. 565 566 unsigned SReg; 567 if (requiresRegisterScavenging(MF)) { 568 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 569 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 570 SReg = findScratchRegister(II, RS, is64Bit ? G8RC : GPRC, SPAdj); 571 } else 572 SReg = is64Bit ? PPC::X0 : PPC::R0; 573 574 // Insert a set of rA with the full offset value before the ld, st, or add 575 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SReg) 576 .addImm(Offset >> 16); 577 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg) 578 .addReg(SReg, RegState::Kill) 579 .addImm(Offset); 580 581 // Convert into indexed form of the instruction: 582 // 583 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 584 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 585 unsigned OperandBase; 586 587 if (OpC != TargetOpcode::INLINEASM) { 588 assert(ImmToIdxMap.count(OpC) && 589 "No indexed form of load or store available!"); 590 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; 591 MI.setDesc(TII.get(NewOpcode)); 592 OperandBase = 1; 593 } else { 594 OperandBase = OffsetOperandNo; 595 } 596 597 unsigned StackReg = MI.getOperand(FIOperandNum).getReg(); 598 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false); 599 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true); 600 } 601 602 unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 603 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 604 605 if (!Subtarget.isPPC64()) 606 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1; 607 else 608 return TFI->hasFP(MF) ? PPC::X31 : PPC::X1; 609 } 610 611 unsigned PPCRegisterInfo::getEHExceptionRegister() const { 612 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3; 613 } 614 615 unsigned PPCRegisterInfo::getEHHandlerRegister() const { 616 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4; 617 } 618