1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the TargetRegisterInfo 11 // class. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #define DEBUG_TYPE "reginfo" 16 #include "PPC.h" 17 #include "PPCInstrBuilder.h" 18 #include "PPCMachineFunctionInfo.h" 19 #include "PPCRegisterInfo.h" 20 #include "PPCFrameLowering.h" 21 #include "PPCSubtarget.h" 22 #include "llvm/CallingConv.h" 23 #include "llvm/Constants.h" 24 #include "llvm/Function.h" 25 #include "llvm/Type.h" 26 #include "llvm/CodeGen/ValueTypes.h" 27 #include "llvm/CodeGen/MachineInstrBuilder.h" 28 #include "llvm/CodeGen/MachineModuleInfo.h" 29 #include "llvm/CodeGen/MachineFunction.h" 30 #include "llvm/CodeGen/MachineFrameInfo.h" 31 #include "llvm/CodeGen/MachineLocation.h" 32 #include "llvm/CodeGen/MachineRegisterInfo.h" 33 #include "llvm/CodeGen/RegisterScavenging.h" 34 #include "llvm/Target/TargetFrameLowering.h" 35 #include "llvm/Target/TargetInstrInfo.h" 36 #include "llvm/Target/TargetMachine.h" 37 #include "llvm/Target/TargetOptions.h" 38 #include "llvm/Support/CommandLine.h" 39 #include "llvm/Support/Debug.h" 40 #include "llvm/Support/ErrorHandling.h" 41 #include "llvm/Support/MathExtras.h" 42 #include "llvm/Support/raw_ostream.h" 43 #include "llvm/ADT/BitVector.h" 44 #include "llvm/ADT/STLExtras.h" 45 #include <cstdlib> 46 47 #define GET_REGINFO_TARGET_DESC 48 #include "PPCGenRegisterInfo.inc" 49 50 // FIXME (64-bit): Eventually enable by default. 51 namespace llvm { 52 cl::opt<bool> EnablePPC32RS("enable-ppc32-regscavenger", 53 cl::init(false), 54 cl::desc("Enable PPC32 register scavenger"), 55 cl::Hidden); 56 cl::opt<bool> EnablePPC64RS("enable-ppc64-regscavenger", 57 cl::init(false), 58 cl::desc("Enable PPC64 register scavenger"), 59 cl::Hidden); 60 } 61 62 using namespace llvm; 63 64 // FIXME (64-bit): Should be inlined. 65 bool 66 PPCRegisterInfo::requiresRegisterScavenging(const MachineFunction &) const { 67 return ((EnablePPC32RS && !Subtarget.isPPC64()) || 68 (EnablePPC64RS && Subtarget.isPPC64())); 69 } 70 71 /// getRegisterNumbering - Given the enum value for some register, e.g. 72 /// PPC::F14, return the number that it corresponds to (e.g. 14). 73 unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) { 74 using namespace PPC; 75 switch (RegEnum) { 76 case 0: return 0; 77 case R0 : case X0 : case F0 : case V0 : case CR0: case CR0LT: return 0; 78 case R1 : case X1 : case F1 : case V1 : case CR1: case CR0GT: return 1; 79 case R2 : case X2 : case F2 : case V2 : case CR2: case CR0EQ: return 2; 80 case R3 : case X3 : case F3 : case V3 : case CR3: case CR0UN: return 3; 81 case R4 : case X4 : case F4 : case V4 : case CR4: case CR1LT: return 4; 82 case R5 : case X5 : case F5 : case V5 : case CR5: case CR1GT: return 5; 83 case R6 : case X6 : case F6 : case V6 : case CR6: case CR1EQ: return 6; 84 case R7 : case X7 : case F7 : case V7 : case CR7: case CR1UN: return 7; 85 case R8 : case X8 : case F8 : case V8 : case CR2LT: return 8; 86 case R9 : case X9 : case F9 : case V9 : case CR2GT: return 9; 87 case R10: case X10: case F10: case V10: case CR2EQ: return 10; 88 case R11: case X11: case F11: case V11: case CR2UN: return 11; 89 case R12: case X12: case F12: case V12: case CR3LT: return 12; 90 case R13: case X13: case F13: case V13: case CR3GT: return 13; 91 case R14: case X14: case F14: case V14: case CR3EQ: return 14; 92 case R15: case X15: case F15: case V15: case CR3UN: return 15; 93 case R16: case X16: case F16: case V16: case CR4LT: return 16; 94 case R17: case X17: case F17: case V17: case CR4GT: return 17; 95 case R18: case X18: case F18: case V18: case CR4EQ: return 18; 96 case R19: case X19: case F19: case V19: case CR4UN: return 19; 97 case R20: case X20: case F20: case V20: case CR5LT: return 20; 98 case R21: case X21: case F21: case V21: case CR5GT: return 21; 99 case R22: case X22: case F22: case V22: case CR5EQ: return 22; 100 case R23: case X23: case F23: case V23: case CR5UN: return 23; 101 case R24: case X24: case F24: case V24: case CR6LT: return 24; 102 case R25: case X25: case F25: case V25: case CR6GT: return 25; 103 case R26: case X26: case F26: case V26: case CR6EQ: return 26; 104 case R27: case X27: case F27: case V27: case CR6UN: return 27; 105 case R28: case X28: case F28: case V28: case CR7LT: return 28; 106 case R29: case X29: case F29: case V29: case CR7GT: return 29; 107 case R30: case X30: case F30: case V30: case CR7EQ: return 30; 108 case R31: case X31: case F31: case V31: case CR7UN: return 31; 109 default: 110 llvm_unreachable("Unhandled reg in PPCRegisterInfo::getRegisterNumbering!"); 111 } 112 } 113 114 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST, 115 const TargetInstrInfo &tii) 116 : PPCGenRegisterInfo(), Subtarget(ST), TII(tii) { 117 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 118 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 119 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 120 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 121 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 122 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 123 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 124 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 125 126 // 64-bit 127 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8; 128 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8; 129 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8; 130 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX; 131 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32; 132 } 133 134 /// getPointerRegClass - Return the register class to use to hold pointers. 135 /// This is used for addressing modes. 136 const TargetRegisterClass * 137 PPCRegisterInfo::getPointerRegClass(unsigned Kind) const { 138 if (Subtarget.isPPC64()) 139 return &PPC::G8RCRegClass; 140 return &PPC::GPRCRegClass; 141 } 142 143 const unsigned* 144 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 145 // 32-bit Darwin calling convention. 146 static const unsigned Darwin32_CalleeSavedRegs[] = { 147 PPC::R13, PPC::R14, PPC::R15, 148 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 149 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 150 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 151 PPC::R28, PPC::R29, PPC::R30, PPC::R31, 152 153 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 154 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 155 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 156 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 157 PPC::F30, PPC::F31, 158 159 PPC::CR2, PPC::CR3, PPC::CR4, 160 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 161 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 162 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 163 164 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 165 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 166 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 167 168 PPC::LR, 0 169 }; 170 171 // 32-bit SVR4 calling convention. 172 static const unsigned SVR4_CalleeSavedRegs[] = { 173 PPC::R14, PPC::R15, 174 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 175 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 176 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 177 PPC::R28, PPC::R29, PPC::R30, PPC::R31, 178 179 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 180 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 181 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 182 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 183 PPC::F30, PPC::F31, 184 185 PPC::CR2, PPC::CR3, PPC::CR4, 186 187 PPC::VRSAVE, 188 189 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 190 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 191 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 192 193 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 194 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 195 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 196 197 0 198 }; 199 // 64-bit Darwin calling convention. 200 static const unsigned Darwin64_CalleeSavedRegs[] = { 201 PPC::X14, PPC::X15, 202 PPC::X16, PPC::X17, PPC::X18, PPC::X19, 203 PPC::X20, PPC::X21, PPC::X22, PPC::X23, 204 PPC::X24, PPC::X25, PPC::X26, PPC::X27, 205 PPC::X28, PPC::X29, PPC::X30, PPC::X31, 206 207 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 208 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 209 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 210 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 211 PPC::F30, PPC::F31, 212 213 PPC::CR2, PPC::CR3, PPC::CR4, 214 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 215 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 216 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 217 218 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 219 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 220 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 221 222 PPC::LR8, 0 223 }; 224 225 // 64-bit SVR4 calling convention. 226 static const unsigned SVR4_64_CalleeSavedRegs[] = { 227 PPC::X14, PPC::X15, 228 PPC::X16, PPC::X17, PPC::X18, PPC::X19, 229 PPC::X20, PPC::X21, PPC::X22, PPC::X23, 230 PPC::X24, PPC::X25, PPC::X26, PPC::X27, 231 PPC::X28, PPC::X29, PPC::X30, PPC::X31, 232 233 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 234 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 235 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 236 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 237 PPC::F30, PPC::F31, 238 239 PPC::CR2, PPC::CR3, PPC::CR4, 240 241 PPC::VRSAVE, 242 243 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 244 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 245 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 246 247 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 248 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 249 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 250 251 0 252 }; 253 254 if (Subtarget.isDarwinABI()) 255 return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegs : 256 Darwin32_CalleeSavedRegs; 257 258 return Subtarget.isPPC64() ? SVR4_64_CalleeSavedRegs : SVR4_CalleeSavedRegs; 259 } 260 261 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 262 BitVector Reserved(getNumRegs()); 263 const PPCFrameLowering *PPCFI = 264 static_cast<const PPCFrameLowering*>(MF.getTarget().getFrameLowering()); 265 266 Reserved.set(PPC::R0); 267 Reserved.set(PPC::R1); 268 Reserved.set(PPC::LR); 269 Reserved.set(PPC::LR8); 270 Reserved.set(PPC::RM); 271 272 // The SVR4 ABI reserves r2 and r13 273 if (Subtarget.isSVR4ABI()) { 274 Reserved.set(PPC::R2); // System-reserved register 275 Reserved.set(PPC::R13); // Small Data Area pointer register 276 } 277 // Reserve R2 on Darwin to hack around the problem of save/restore of CR 278 // when the stack frame is too big to address directly; we need two regs. 279 // This is a hack. 280 if (Subtarget.isDarwinABI()) { 281 Reserved.set(PPC::R2); 282 } 283 284 // On PPC64, r13 is the thread pointer. Never allocate this register. 285 // Note that this is over conservative, as it also prevents allocation of R31 286 // when the FP is not needed. 287 if (Subtarget.isPPC64()) { 288 Reserved.set(PPC::R13); 289 Reserved.set(PPC::R31); 290 291 if (!requiresRegisterScavenging(MF)) 292 Reserved.set(PPC::R0); // FIXME (64-bit): Remove 293 294 Reserved.set(PPC::X0); 295 Reserved.set(PPC::X1); 296 Reserved.set(PPC::X13); 297 Reserved.set(PPC::X31); 298 299 // The 64-bit SVR4 ABI reserves r2 for the TOC pointer. 300 if (Subtarget.isSVR4ABI()) { 301 Reserved.set(PPC::X2); 302 } 303 // Reserve R2 on Darwin to hack around the problem of save/restore of CR 304 // when the stack frame is too big to address directly; we need two regs. 305 // This is a hack. 306 if (Subtarget.isDarwinABI()) { 307 Reserved.set(PPC::X2); 308 } 309 } 310 311 if (PPCFI->needsFP(MF)) 312 Reserved.set(PPC::R31); 313 314 return Reserved; 315 } 316 317 //===----------------------------------------------------------------------===// 318 // Stack Frame Processing methods 319 //===----------------------------------------------------------------------===// 320 321 void PPCRegisterInfo:: 322 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 323 MachineBasicBlock::iterator I) const { 324 if (GuaranteedTailCallOpt && I->getOpcode() == PPC::ADJCALLSTACKUP) { 325 // Add (actually subtract) back the amount the callee popped on return. 326 if (int CalleeAmt = I->getOperand(1).getImm()) { 327 bool is64Bit = Subtarget.isPPC64(); 328 CalleeAmt *= -1; 329 unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1; 330 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0; 331 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI; 332 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4; 333 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS; 334 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI; 335 MachineInstr *MI = I; 336 DebugLoc dl = MI->getDebugLoc(); 337 338 if (isInt<16>(CalleeAmt)) { 339 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg).addReg(StackReg). 340 addImm(CalleeAmt); 341 } else { 342 MachineBasicBlock::iterator MBBI = I; 343 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) 344 .addImm(CalleeAmt >> 16); 345 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) 346 .addReg(TmpReg, RegState::Kill) 347 .addImm(CalleeAmt & 0xFFFF); 348 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr)) 349 .addReg(StackReg) 350 .addReg(StackReg) 351 .addReg(TmpReg); 352 } 353 } 354 } 355 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions. 356 MBB.erase(I); 357 } 358 359 /// findScratchRegister - Find a 'free' PPC register. Try for a call-clobbered 360 /// register first and then a spilled callee-saved register if that fails. 361 static 362 unsigned findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS, 363 const TargetRegisterClass *RC, int SPAdj) { 364 assert(RS && "Register scavenging must be on"); 365 unsigned Reg = RS->FindUnusedReg(RC); 366 // FIXME: move ARM callee-saved reg scan to target independent code, then 367 // search for already spilled CS register here. 368 if (Reg == 0) 369 Reg = RS->scavengeRegister(RC, II, SPAdj); 370 return Reg; 371 } 372 373 /// lowerDynamicAlloc - Generate the code for allocating an object in the 374 /// current frame. The sequence of code with be in the general form 375 /// 376 /// addi R0, SP, \#frameSize ; get the address of the previous frame 377 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size 378 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation 379 /// 380 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II, 381 int SPAdj, RegScavenger *RS) const { 382 // Get the instruction. 383 MachineInstr &MI = *II; 384 // Get the instruction's basic block. 385 MachineBasicBlock &MBB = *MI.getParent(); 386 // Get the basic block's function. 387 MachineFunction &MF = *MBB.getParent(); 388 // Get the frame info. 389 MachineFrameInfo *MFI = MF.getFrameInfo(); 390 // Determine whether 64-bit pointers are used. 391 bool LP64 = Subtarget.isPPC64(); 392 DebugLoc dl = MI.getDebugLoc(); 393 394 // Get the maximum call stack size. 395 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 396 // Get the total frame size. 397 unsigned FrameSize = MFI->getStackSize(); 398 399 // Get stack alignments. 400 unsigned TargetAlign = MF.getTarget().getFrameLowering()->getStackAlignment(); 401 unsigned MaxAlign = MFI->getMaxAlignment(); 402 if (MaxAlign > TargetAlign) 403 report_fatal_error("Dynamic alloca with large aligns not supported"); 404 405 // Determine the previous frame's address. If FrameSize can't be 406 // represented as 16 bits or we need special alignment, then we load the 407 // previous frame's address from 0(SP). Why not do an addis of the hi? 408 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. 409 // Constructing the constant and adding would take 3 instructions. 410 // Fortunately, a frame greater than 32K is rare. 411 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 412 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 413 const TargetRegisterClass *RC = LP64 ? G8RC : GPRC; 414 415 // FIXME (64-bit): Use "findScratchRegister" 416 unsigned Reg; 417 if (requiresRegisterScavenging(MF)) 418 Reg = findScratchRegister(II, RS, RC, SPAdj); 419 else 420 Reg = PPC::R0; 421 422 if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) { 423 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) 424 .addReg(PPC::R31) 425 .addImm(FrameSize); 426 } else if (LP64) { 427 if (requiresRegisterScavenging(MF)) // FIXME (64-bit): Use "true" part. 428 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg) 429 .addImm(0) 430 .addReg(PPC::X1); 431 else 432 BuildMI(MBB, II, dl, TII.get(PPC::LD), PPC::X0) 433 .addImm(0) 434 .addReg(PPC::X1); 435 } else { 436 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) 437 .addImm(0) 438 .addReg(PPC::R1); 439 } 440 441 // Grow the stack and update the stack pointer link, then determine the 442 // address of new allocated space. 443 if (LP64) { 444 if (requiresRegisterScavenging(MF)) // FIXME (64-bit): Use "true" part. 445 BuildMI(MBB, II, dl, TII.get(PPC::STDUX)) 446 .addReg(Reg, RegState::Kill) 447 .addReg(PPC::X1) 448 .addReg(MI.getOperand(1).getReg()); 449 else 450 BuildMI(MBB, II, dl, TII.get(PPC::STDUX)) 451 .addReg(PPC::X0, RegState::Kill) 452 .addReg(PPC::X1) 453 .addReg(MI.getOperand(1).getReg()); 454 455 if (!MI.getOperand(1).isKill()) 456 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 457 .addReg(PPC::X1) 458 .addImm(maxCallFrameSize); 459 else 460 // Implicitly kill the register. 461 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 462 .addReg(PPC::X1) 463 .addImm(maxCallFrameSize) 464 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill); 465 } else { 466 BuildMI(MBB, II, dl, TII.get(PPC::STWUX)) 467 .addReg(Reg, RegState::Kill) 468 .addReg(PPC::R1) 469 .addReg(MI.getOperand(1).getReg()); 470 471 if (!MI.getOperand(1).isKill()) 472 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 473 .addReg(PPC::R1) 474 .addImm(maxCallFrameSize); 475 else 476 // Implicitly kill the register. 477 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 478 .addReg(PPC::R1) 479 .addImm(maxCallFrameSize) 480 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill); 481 } 482 483 // Discard the DYNALLOC instruction. 484 MBB.erase(II); 485 } 486 487 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of 488 /// reserving a whole register (R0), we scrounge for one here. This generates 489 /// code like this: 490 /// 491 /// mfcr rA ; Move the conditional register into GPR rA. 492 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot. 493 /// stw rA, FI ; Store rA to the frame. 494 /// 495 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, 496 unsigned FrameIndex, int SPAdj, 497 RegScavenger *RS) const { 498 // Get the instruction. 499 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>, <FI> 500 // Get the instruction's basic block. 501 MachineBasicBlock &MBB = *MI.getParent(); 502 DebugLoc dl = MI.getDebugLoc(); 503 504 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 505 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 506 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC; 507 unsigned Reg = findScratchRegister(II, RS, RC, SPAdj); 508 unsigned SrcReg = MI.getOperand(0).getReg(); 509 bool LP64 = Subtarget.isPPC64(); 510 511 // We need to store the CR in the low 4-bits of the saved value. First, issue 512 // an MFCRpsued to save all of the CRBits and, if needed, kill the SrcReg. 513 BuildMI(MBB, II, dl, TII.get(PPC::MFCRpseud), Reg) 514 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 515 516 // If the saved register wasn't CR0, shift the bits left so that they are in 517 // CR0's slot. 518 if (SrcReg != PPC::CR0) 519 // rlwinm rA, rA, ShiftBits, 0, 31. 520 BuildMI(MBB, II, dl, TII.get(PPC::RLWINM), Reg) 521 .addReg(Reg, RegState::Kill) 522 .addImm(PPCRegisterInfo::getRegisterNumbering(SrcReg) * 4) 523 .addImm(0) 524 .addImm(31); 525 526 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW)) 527 .addReg(Reg, getKillRegState(MI.getOperand(1).getImm())), 528 FrameIndex); 529 530 // Discard the pseudo instruction. 531 MBB.erase(II); 532 } 533 534 void 535 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 536 int SPAdj, RegScavenger *RS) const { 537 assert(SPAdj == 0 && "Unexpected"); 538 539 // Get the instruction. 540 MachineInstr &MI = *II; 541 // Get the instruction's basic block. 542 MachineBasicBlock &MBB = *MI.getParent(); 543 // Get the basic block's function. 544 MachineFunction &MF = *MBB.getParent(); 545 // Get the frame info. 546 MachineFrameInfo *MFI = MF.getFrameInfo(); 547 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 548 DebugLoc dl = MI.getDebugLoc(); 549 550 // Find out which operand is the frame index. 551 unsigned FIOperandNo = 0; 552 while (!MI.getOperand(FIOperandNo).isFI()) { 553 ++FIOperandNo; 554 assert(FIOperandNo != MI.getNumOperands() && 555 "Instr doesn't have FrameIndex operand!"); 556 } 557 // Take into account whether it's an add or mem instruction 558 unsigned OffsetOperandNo = (FIOperandNo == 2) ? 1 : 2; 559 if (MI.isInlineAsm()) 560 OffsetOperandNo = FIOperandNo-1; 561 562 // Get the frame index. 563 int FrameIndex = MI.getOperand(FIOperandNo).getIndex(); 564 565 // Get the frame pointer save index. Users of this index are primarily 566 // DYNALLOC instructions. 567 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 568 int FPSI = FI->getFramePointerSaveIndex(); 569 // Get the instruction opcode. 570 unsigned OpC = MI.getOpcode(); 571 572 // Special case for dynamic alloca. 573 if (FPSI && FrameIndex == FPSI && 574 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { 575 lowerDynamicAlloc(II, SPAdj, RS); 576 return; 577 } 578 579 // Special case for pseudo-op SPILL_CR. 580 if (requiresRegisterScavenging(MF)) // FIXME (64-bit): Enable by default. 581 if (OpC == PPC::SPILL_CR) { 582 lowerCRSpilling(II, FrameIndex, SPAdj, RS); 583 return; 584 } 585 586 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 587 MI.getOperand(FIOperandNo).ChangeToRegister(TFI->hasFP(MF) ? 588 PPC::R31 : PPC::R1, 589 false); 590 591 // Figure out if the offset in the instruction is shifted right two bits. This 592 // is true for instructions like "STD", which the machine implicitly adds two 593 // low zeros to. 594 bool isIXAddr = false; 595 switch (OpC) { 596 case PPC::LWA: 597 case PPC::LD: 598 case PPC::STD: 599 case PPC::STD_32: 600 isIXAddr = true; 601 break; 602 } 603 604 // Now add the frame object offset to the offset from r1. 605 int Offset = MFI->getObjectOffset(FrameIndex); 606 if (!isIXAddr) 607 Offset += MI.getOperand(OffsetOperandNo).getImm(); 608 else 609 Offset += MI.getOperand(OffsetOperandNo).getImm() << 2; 610 611 // If we're not using a Frame Pointer that has been set to the value of the 612 // SP before having the stack size subtracted from it, then add the stack size 613 // to Offset to get the correct offset. 614 // Naked functions have stack size 0, although getStackSize may not reflect that 615 // because we didn't call all the pieces that compute it for naked functions. 616 if (!MF.getFunction()->hasFnAttr(Attribute::Naked)) 617 Offset += MFI->getStackSize(); 618 619 // If we can, encode the offset directly into the instruction. If this is a 620 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If 621 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits 622 // clear can be encoded. This is extremely uncommon, because normally you 623 // only "std" to a stack slot that is at least 4-byte aligned, but it can 624 // happen in invalid code. 625 if (isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0)) { 626 if (isIXAddr) 627 Offset >>= 2; // The actual encoded value has the low two bits zero. 628 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 629 return; 630 } 631 632 // The offset doesn't fit into a single register, scavenge one to build the 633 // offset in. 634 // FIXME: figure out what SPAdj is doing here. 635 636 // FIXME (64-bit): Use "findScratchRegister". 637 unsigned SReg; 638 if (requiresRegisterScavenging(MF)) 639 SReg = findScratchRegister(II, RS, &PPC::GPRCRegClass, SPAdj); 640 else 641 SReg = PPC::R0; 642 643 // Insert a set of rA with the full offset value before the ld, st, or add 644 BuildMI(MBB, II, dl, TII.get(PPC::LIS), SReg) 645 .addImm(Offset >> 16); 646 BuildMI(MBB, II, dl, TII.get(PPC::ORI), SReg) 647 .addReg(SReg, RegState::Kill) 648 .addImm(Offset); 649 650 // Convert into indexed form of the instruction: 651 // 652 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 653 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 654 unsigned OperandBase; 655 656 if (OpC != TargetOpcode::INLINEASM) { 657 assert(ImmToIdxMap.count(OpC) && 658 "No indexed form of load or store available!"); 659 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; 660 MI.setDesc(TII.get(NewOpcode)); 661 OperandBase = 1; 662 } else { 663 OperandBase = OffsetOperandNo; 664 } 665 666 unsigned StackReg = MI.getOperand(FIOperandNo).getReg(); 667 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false); 668 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false); 669 } 670 671 unsigned PPCRegisterInfo::getRARegister() const { 672 return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8; 673 } 674 675 unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 676 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 677 678 if (!Subtarget.isPPC64()) 679 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1; 680 else 681 return TFI->hasFP(MF) ? PPC::X31 : PPC::X1; 682 } 683 684 unsigned PPCRegisterInfo::getEHExceptionRegister() const { 685 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3; 686 } 687 688 unsigned PPCRegisterInfo::getEHHandlerRegister() const { 689 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4; 690 } 691 692 /// DWARFFlavour - Flavour of dwarf regnumbers 693 /// 694 namespace DWARFFlavour { 695 enum { 696 PPC64 = 0, PPC32 = 1 697 }; 698 } 699 700 int PPCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { 701 // FIXME: Most probably dwarf numbers differs for Linux and Darwin 702 unsigned Flavour = Subtarget.isPPC64() ? 703 DWARFFlavour::PPC64 : DWARFFlavour::PPC32; 704 705 return PPCGenRegisterInfo::getDwarfRegNumFull(RegNum, Flavour); 706 } 707 708 int PPCRegisterInfo::getLLVMRegNum(unsigned RegNum, bool isEH) const { 709 // FIXME: Most probably dwarf numbers differs for Linux and Darwin 710 unsigned Flavour = Subtarget.isPPC64() ? 711 DWARFFlavour::PPC64 : DWARFFlavour::PPC32; 712 713 return PPCGenRegisterInfo::getLLVMRegNumFull(RegNum, Flavour); 714 } 715