1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file was developed by the LLVM research group and is distributed under 6 // the University of Illinois Open Source License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the MRegisterInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #define DEBUG_TYPE "reginfo" 15 #include "PPC.h" 16 #include "PPCInstrBuilder.h" 17 #include "PPCMachineFunctionInfo.h" 18 #include "PPCRegisterInfo.h" 19 #include "PPCFrameInfo.h" 20 #include "PPCSubtarget.h" 21 #include "llvm/Constants.h" 22 #include "llvm/Type.h" 23 #include "llvm/CodeGen/ValueTypes.h" 24 #include "llvm/CodeGen/MachineInstrBuilder.h" 25 #include "llvm/CodeGen/MachineModuleInfo.h" 26 #include "llvm/CodeGen/MachineFunction.h" 27 #include "llvm/CodeGen/MachineFrameInfo.h" 28 #include "llvm/CodeGen/MachineLocation.h" 29 #include "llvm/CodeGen/SelectionDAGNodes.h" 30 #include "llvm/Target/TargetFrameInfo.h" 31 #include "llvm/Target/TargetInstrInfo.h" 32 #include "llvm/Target/TargetMachine.h" 33 #include "llvm/Target/TargetOptions.h" 34 #include "llvm/Support/CommandLine.h" 35 #include "llvm/Support/Debug.h" 36 #include "llvm/Support/MathExtras.h" 37 #include "llvm/ADT/BitVector.h" 38 #include "llvm/ADT/STLExtras.h" 39 #include <cstdlib> 40 using namespace llvm; 41 42 /// getRegisterNumbering - Given the enum value for some register, e.g. 43 /// PPC::F14, return the number that it corresponds to (e.g. 14). 44 unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) { 45 using namespace PPC; 46 switch (RegEnum) { 47 case R0 : case X0 : case F0 : case V0 : case CR0: return 0; 48 case R1 : case X1 : case F1 : case V1 : case CR1: return 1; 49 case R2 : case X2 : case F2 : case V2 : case CR2: return 2; 50 case R3 : case X3 : case F3 : case V3 : case CR3: return 3; 51 case R4 : case X4 : case F4 : case V4 : case CR4: return 4; 52 case R5 : case X5 : case F5 : case V5 : case CR5: return 5; 53 case R6 : case X6 : case F6 : case V6 : case CR6: return 6; 54 case R7 : case X7 : case F7 : case V7 : case CR7: return 7; 55 case R8 : case X8 : case F8 : case V8 : return 8; 56 case R9 : case X9 : case F9 : case V9 : return 9; 57 case R10: case X10: case F10: case V10: return 10; 58 case R11: case X11: case F11: case V11: return 11; 59 case R12: case X12: case F12: case V12: return 12; 60 case R13: case X13: case F13: case V13: return 13; 61 case R14: case X14: case F14: case V14: return 14; 62 case R15: case X15: case F15: case V15: return 15; 63 case R16: case X16: case F16: case V16: return 16; 64 case R17: case X17: case F17: case V17: return 17; 65 case R18: case X18: case F18: case V18: return 18; 66 case R19: case X19: case F19: case V19: return 19; 67 case R20: case X20: case F20: case V20: return 20; 68 case R21: case X21: case F21: case V21: return 21; 69 case R22: case X22: case F22: case V22: return 22; 70 case R23: case X23: case F23: case V23: return 23; 71 case R24: case X24: case F24: case V24: return 24; 72 case R25: case X25: case F25: case V25: return 25; 73 case R26: case X26: case F26: case V26: return 26; 74 case R27: case X27: case F27: case V27: return 27; 75 case R28: case X28: case F28: case V28: return 28; 76 case R29: case X29: case F29: case V29: return 29; 77 case R30: case X30: case F30: case V30: return 30; 78 case R31: case X31: case F31: case V31: return 31; 79 default: 80 cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n"; 81 abort(); 82 } 83 } 84 85 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST, 86 const TargetInstrInfo &tii) 87 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP), 88 Subtarget(ST), TII(tii) { 89 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 90 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 91 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 92 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 93 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 94 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 95 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 96 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 97 98 // 64-bit 99 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8; 100 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8; 101 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8; 102 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX; 103 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32; 104 } 105 106 static void StoreRegToStackSlot(const TargetInstrInfo &TII, 107 unsigned SrcReg, bool isKill, int FrameIdx, 108 const TargetRegisterClass *RC, 109 SmallVectorImpl<MachineInstr*> &NewMIs) { 110 if (RC == PPC::GPRCRegisterClass) { 111 if (SrcReg != PPC::LR) { 112 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW)) 113 .addReg(SrcReg, false, false, isKill), FrameIdx)); 114 } else { 115 // FIXME: this spills LR immediately to memory in one step. To do this, 116 // we use R11, which we know cannot be used in the prolog/epilog. This is 117 // a hack. 118 NewMIs.push_back(BuildMI(TII.get(PPC::MFLR), PPC::R11)); 119 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW)) 120 .addReg(PPC::R11, false, false, isKill), FrameIdx)); 121 } 122 } else if (RC == PPC::G8RCRegisterClass) { 123 if (SrcReg != PPC::LR8) { 124 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STD)) 125 .addReg(SrcReg, false, false, isKill), FrameIdx)); 126 } else { 127 // FIXME: this spills LR immediately to memory in one step. To do this, 128 // we use R11, which we know cannot be used in the prolog/epilog. This is 129 // a hack. 130 NewMIs.push_back(BuildMI(TII.get(PPC::MFLR8), PPC::X11)); 131 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STD)) 132 .addReg(PPC::X11, false, false, isKill), FrameIdx)); 133 } 134 } else if (RC == PPC::F8RCRegisterClass) { 135 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STFD)) 136 .addReg(SrcReg, false, false, isKill), FrameIdx)); 137 } else if (RC == PPC::F4RCRegisterClass) { 138 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STFS)) 139 .addReg(SrcReg, false, false, isKill), FrameIdx)); 140 } else if (RC == PPC::CRRCRegisterClass) { 141 // FIXME: We use R0 here, because it isn't available for RA. 142 // We need to store the CR in the low 4-bits of the saved value. First, 143 // issue a MFCR to save all of the CRBits. 144 NewMIs.push_back(BuildMI(TII.get(PPC::MFCR), PPC::R0)); 145 146 // If the saved register wasn't CR0, shift the bits left so that they are in 147 // CR0's slot. 148 if (SrcReg != PPC::CR0) { 149 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4; 150 // rlwinm r0, r0, ShiftBits, 0, 31. 151 NewMIs.push_back(BuildMI(TII.get(PPC::RLWINM), PPC::R0) 152 .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31)); 153 } 154 155 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW)) 156 .addReg(PPC::R0, false, false, isKill), FrameIdx)); 157 } else if (RC == PPC::VRRCRegisterClass) { 158 // We don't have indexed addressing for vector loads. Emit: 159 // R0 = ADDI FI# 160 // STVX VAL, 0, R0 161 // 162 // FIXME: We use R0 here, because it isn't available for RA. 163 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::ADDI), PPC::R0), 164 FrameIdx, 0, 0)); 165 NewMIs.push_back(BuildMI(TII.get(PPC::STVX)) 166 .addReg(SrcReg, false, false, isKill).addReg(PPC::R0).addReg(PPC::R0)); 167 } else { 168 assert(0 && "Unknown regclass!"); 169 abort(); 170 } 171 } 172 173 void 174 PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 175 MachineBasicBlock::iterator MI, 176 unsigned SrcReg, bool isKill, int FrameIdx, 177 const TargetRegisterClass *RC) const { 178 SmallVector<MachineInstr*, 4> NewMIs; 179 StoreRegToStackSlot(TII, SrcReg, isKill, FrameIdx, RC, NewMIs); 180 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i) 181 MBB.insert(MI, NewMIs[i]); 182 } 183 184 void PPCRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, 185 bool isKill, 186 SmallVectorImpl<MachineOperand> &Addr, 187 const TargetRegisterClass *RC, 188 SmallVectorImpl<MachineInstr*> &NewMIs) const { 189 if (Addr[0].isFrameIndex()) { 190 StoreRegToStackSlot(TII, SrcReg, isKill, Addr[0].getFrameIndex(), RC, 191 NewMIs); 192 return; 193 } 194 195 unsigned Opc = 0; 196 if (RC == PPC::GPRCRegisterClass) { 197 Opc = PPC::STW; 198 } else if (RC == PPC::G8RCRegisterClass) { 199 Opc = PPC::STD; 200 } else if (RC == PPC::F8RCRegisterClass) { 201 Opc = PPC::STFD; 202 } else if (RC == PPC::F4RCRegisterClass) { 203 Opc = PPC::STFS; 204 } else if (RC == PPC::VRRCRegisterClass) { 205 Opc = PPC::STVX; 206 } else { 207 assert(0 && "Unknown regclass!"); 208 abort(); 209 } 210 MachineInstrBuilder MIB = BuildMI(TII.get(Opc)) 211 .addReg(SrcReg, false, false, isKill); 212 for (unsigned i = 0, e = Addr.size(); i != e; ++i) { 213 MachineOperand &MO = Addr[i]; 214 if (MO.isRegister()) 215 MIB.addReg(MO.getReg()); 216 else if (MO.isImmediate()) 217 MIB.addImm(MO.getImmedValue()); 218 else 219 MIB.addFrameIndex(MO.getFrameIndex()); 220 } 221 NewMIs.push_back(MIB); 222 return; 223 } 224 225 static void LoadRegFromStackSlot(const TargetInstrInfo &TII, 226 unsigned DestReg, int FrameIdx, 227 const TargetRegisterClass *RC, 228 SmallVectorImpl<MachineInstr*> &NewMIs) { 229 if (RC == PPC::GPRCRegisterClass) { 230 if (DestReg != PPC::LR) { 231 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LWZ), DestReg), 232 FrameIdx)); 233 } else { 234 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LWZ), PPC::R11), 235 FrameIdx)); 236 NewMIs.push_back(BuildMI(TII.get(PPC::MTLR)).addReg(PPC::R11)); 237 } 238 } else if (RC == PPC::G8RCRegisterClass) { 239 if (DestReg != PPC::LR8) { 240 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LD), DestReg), 241 FrameIdx)); 242 } else { 243 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LD), PPC::R11), 244 FrameIdx)); 245 NewMIs.push_back(BuildMI(TII.get(PPC::MTLR8)).addReg(PPC::R11)); 246 } 247 } else if (RC == PPC::F8RCRegisterClass) { 248 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LFD), DestReg), 249 FrameIdx)); 250 } else if (RC == PPC::F4RCRegisterClass) { 251 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LFS), DestReg), 252 FrameIdx)); 253 } else if (RC == PPC::CRRCRegisterClass) { 254 // FIXME: We use R0 here, because it isn't available for RA. 255 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LWZ), PPC::R0), 256 FrameIdx)); 257 258 // If the reloaded register isn't CR0, shift the bits right so that they are 259 // in the right CR's slot. 260 if (DestReg != PPC::CR0) { 261 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4; 262 // rlwinm r11, r11, 32-ShiftBits, 0, 31. 263 NewMIs.push_back(BuildMI(TII.get(PPC::RLWINM), PPC::R0) 264 .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31)); 265 } 266 267 NewMIs.push_back(BuildMI(TII.get(PPC::MTCRF), DestReg).addReg(PPC::R0)); 268 } else if (RC == PPC::VRRCRegisterClass) { 269 // We don't have indexed addressing for vector loads. Emit: 270 // R0 = ADDI FI# 271 // Dest = LVX 0, R0 272 // 273 // FIXME: We use R0 here, because it isn't available for RA. 274 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::ADDI), PPC::R0), 275 FrameIdx, 0, 0)); 276 NewMIs.push_back(BuildMI(TII.get(PPC::LVX),DestReg).addReg(PPC::R0) 277 .addReg(PPC::R0)); 278 } else { 279 assert(0 && "Unknown regclass!"); 280 abort(); 281 } 282 } 283 284 void 285 PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 286 MachineBasicBlock::iterator MI, 287 unsigned DestReg, int FrameIdx, 288 const TargetRegisterClass *RC) const { 289 SmallVector<MachineInstr*, 4> NewMIs; 290 LoadRegFromStackSlot(TII, DestReg, FrameIdx, RC, NewMIs); 291 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i) 292 MBB.insert(MI, NewMIs[i]); 293 } 294 295 void PPCRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 296 SmallVectorImpl<MachineOperand> &Addr, 297 const TargetRegisterClass *RC, 298 SmallVectorImpl<MachineInstr*> &NewMIs) const { 299 if (Addr[0].isFrameIndex()) { 300 LoadRegFromStackSlot(TII, DestReg, Addr[0].getFrameIndex(), RC, NewMIs); 301 return; 302 } 303 304 unsigned Opc = 0; 305 if (RC == PPC::GPRCRegisterClass) { 306 assert(DestReg != PPC::LR && "Can't handle this yet!"); 307 Opc = PPC::LWZ; 308 } else if (RC == PPC::G8RCRegisterClass) { 309 assert(DestReg != PPC::LR8 && "Can't handle this yet!"); 310 Opc = PPC::LD; 311 } else if (RC == PPC::F8RCRegisterClass) { 312 Opc = PPC::LFD; 313 } else if (RC == PPC::F4RCRegisterClass) { 314 Opc = PPC::LFS; 315 } else if (RC == PPC::VRRCRegisterClass) { 316 Opc = PPC::LVX; 317 } else { 318 assert(0 && "Unknown regclass!"); 319 abort(); 320 } 321 MachineInstrBuilder MIB = BuildMI(TII.get(Opc), DestReg); 322 for (unsigned i = 0, e = Addr.size(); i != e; ++i) { 323 MachineOperand &MO = Addr[i]; 324 if (MO.isRegister()) 325 MIB.addReg(MO.getReg()); 326 else if (MO.isImmediate()) 327 MIB.addImm(MO.getImmedValue()); 328 else 329 MIB.addFrameIndex(MO.getFrameIndex()); 330 } 331 NewMIs.push_back(MIB); 332 return; 333 } 334 335 void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, 336 MachineBasicBlock::iterator MI, 337 unsigned DestReg, unsigned SrcReg, 338 const TargetRegisterClass *DestRC, 339 const TargetRegisterClass *SrcRC) const { 340 if (DestRC != SrcRC) { 341 cerr << "Not yet supported!"; 342 abort(); 343 } 344 345 if (DestRC == PPC::GPRCRegisterClass) { 346 BuildMI(MBB, MI, TII.get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg); 347 } else if (DestRC == PPC::G8RCRegisterClass) { 348 BuildMI(MBB, MI, TII.get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg); 349 } else if (DestRC == PPC::F4RCRegisterClass) { 350 BuildMI(MBB, MI, TII.get(PPC::FMRS), DestReg).addReg(SrcReg); 351 } else if (DestRC == PPC::F8RCRegisterClass) { 352 BuildMI(MBB, MI, TII.get(PPC::FMRD), DestReg).addReg(SrcReg); 353 } else if (DestRC == PPC::CRRCRegisterClass) { 354 BuildMI(MBB, MI, TII.get(PPC::MCRF), DestReg).addReg(SrcReg); 355 } else if (DestRC == PPC::VRRCRegisterClass) { 356 BuildMI(MBB, MI, TII.get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg); 357 } else { 358 cerr << "Attempt to copy register that is not GPR or FPR"; 359 abort(); 360 } 361 } 362 363 void PPCRegisterInfo::reMaterialize(MachineBasicBlock &MBB, 364 MachineBasicBlock::iterator I, 365 unsigned DestReg, 366 const MachineInstr *Orig) const { 367 MachineInstr *MI = Orig->clone(); 368 MI->getOperand(0).setReg(DestReg); 369 MBB.insert(I, MI); 370 } 371 372 const unsigned* 373 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 374 // 32-bit Darwin calling convention. 375 static const unsigned Macho32_CalleeSavedRegs[] = { 376 PPC::R13, PPC::R14, PPC::R15, 377 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 378 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 379 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 380 PPC::R28, PPC::R29, PPC::R30, PPC::R31, 381 382 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 383 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 384 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 385 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 386 PPC::F30, PPC::F31, 387 388 PPC::CR2, PPC::CR3, PPC::CR4, 389 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 390 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 391 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 392 393 PPC::LR, 0 394 }; 395 396 static const unsigned ELF32_CalleeSavedRegs[] = { 397 PPC::R13, PPC::R14, PPC::R15, 398 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 399 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 400 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 401 PPC::R28, PPC::R29, PPC::R30, PPC::R31, 402 403 PPC::F9, 404 PPC::F10, PPC::F11, PPC::F12, PPC::F13, 405 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 406 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 407 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 408 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 409 PPC::F30, PPC::F31, 410 411 PPC::CR2, PPC::CR3, PPC::CR4, 412 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 413 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 414 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 415 416 PPC::LR, 0 417 }; 418 // 64-bit Darwin calling convention. 419 static const unsigned Macho64_CalleeSavedRegs[] = { 420 PPC::X14, PPC::X15, 421 PPC::X16, PPC::X17, PPC::X18, PPC::X19, 422 PPC::X20, PPC::X21, PPC::X22, PPC::X23, 423 PPC::X24, PPC::X25, PPC::X26, PPC::X27, 424 PPC::X28, PPC::X29, PPC::X30, PPC::X31, 425 426 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 427 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 428 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 429 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 430 PPC::F30, PPC::F31, 431 432 PPC::CR2, PPC::CR3, PPC::CR4, 433 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 434 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 435 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 436 437 PPC::LR8, 0 438 }; 439 440 if (Subtarget.isMachoABI()) 441 return Subtarget.isPPC64() ? Macho64_CalleeSavedRegs : 442 Macho32_CalleeSavedRegs; 443 444 // ELF 32. 445 return ELF32_CalleeSavedRegs; 446 } 447 448 const TargetRegisterClass* const* 449 PPCRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const { 450 // 32-bit Macho calling convention. 451 static const TargetRegisterClass * const Macho32_CalleeSavedRegClasses[] = { 452 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 453 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 454 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 455 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 456 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 457 458 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 459 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 460 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 461 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 462 &PPC::F8RCRegClass,&PPC::F8RCRegClass, 463 464 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, 465 466 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 467 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 468 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 469 470 &PPC::GPRCRegClass, 0 471 }; 472 473 static const TargetRegisterClass * const ELF32_CalleeSavedRegClasses[] = { 474 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 475 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 476 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 477 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 478 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 479 480 &PPC::F8RCRegClass, 481 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 482 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 483 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 484 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 485 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 486 &PPC::F8RCRegClass,&PPC::F8RCRegClass, 487 488 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, 489 490 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 491 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 492 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 493 494 &PPC::GPRCRegClass, 0 495 }; 496 497 // 64-bit Macho calling convention. 498 static const TargetRegisterClass * const Macho64_CalleeSavedRegClasses[] = { 499 &PPC::G8RCRegClass,&PPC::G8RCRegClass, 500 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 501 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 502 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 503 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 504 505 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 506 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 507 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 508 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 509 &PPC::F8RCRegClass,&PPC::F8RCRegClass, 510 511 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, 512 513 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 514 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 515 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 516 517 &PPC::G8RCRegClass, 0 518 }; 519 520 if (Subtarget.isMachoABI()) 521 return Subtarget.isPPC64() ? Macho64_CalleeSavedRegClasses : 522 Macho32_CalleeSavedRegClasses; 523 524 // ELF 32. 525 return ELF32_CalleeSavedRegClasses; 526 } 527 528 // needsFP - Return true if the specified function should have a dedicated frame 529 // pointer register. This is true if the function has variable sized allocas or 530 // if frame pointer elimination is disabled. 531 // 532 static bool needsFP(const MachineFunction &MF) { 533 const MachineFrameInfo *MFI = MF.getFrameInfo(); 534 return NoFramePointerElim || MFI->hasVarSizedObjects(); 535 } 536 537 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 538 BitVector Reserved(getNumRegs()); 539 Reserved.set(PPC::R0); 540 Reserved.set(PPC::R1); 541 Reserved.set(PPC::LR); 542 // In Linux, r2 is reserved for the OS. 543 if (!Subtarget.isDarwin()) 544 Reserved.set(PPC::R2); 545 // On PPC64, r13 is the thread pointer. Never allocate this register. 546 // Note that this is overconservative, as it also prevents allocation of 547 // R31 when the FP is not needed. 548 if (Subtarget.isPPC64()) { 549 Reserved.set(PPC::R13); 550 Reserved.set(PPC::R31); 551 } 552 if (needsFP(MF)) 553 Reserved.set(PPC::R31); 554 return Reserved; 555 } 556 557 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into 558 /// copy instructions, turning them into load/store instructions. 559 MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI, 560 SmallVectorImpl<unsigned> &Ops, 561 int FrameIndex) const { 562 if (Ops.size() != 1) return NULL; 563 564 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because 565 // it takes more than one instruction to store it. 566 unsigned Opc = MI->getOpcode(); 567 unsigned OpNum = Ops[0]; 568 569 MachineInstr *NewMI = NULL; 570 if ((Opc == PPC::OR && 571 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { 572 if (OpNum == 0) { // move -> store 573 unsigned InReg = MI->getOperand(1).getReg(); 574 NewMI = addFrameReference(BuildMI(TII.get(PPC::STW)).addReg(InReg), 575 FrameIndex); 576 } else { // move -> load 577 unsigned OutReg = MI->getOperand(0).getReg(); 578 NewMI = addFrameReference(BuildMI(TII.get(PPC::LWZ), OutReg), 579 FrameIndex); 580 } 581 } else if ((Opc == PPC::OR8 && 582 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { 583 if (OpNum == 0) { // move -> store 584 unsigned InReg = MI->getOperand(1).getReg(); 585 NewMI = addFrameReference(BuildMI(TII.get(PPC::STD)).addReg(InReg), 586 FrameIndex); 587 } else { // move -> load 588 unsigned OutReg = MI->getOperand(0).getReg(); 589 NewMI = addFrameReference(BuildMI(TII.get(PPC::LD), OutReg), FrameIndex); 590 } 591 } else if (Opc == PPC::FMRD) { 592 if (OpNum == 0) { // move -> store 593 unsigned InReg = MI->getOperand(1).getReg(); 594 NewMI = addFrameReference(BuildMI(TII.get(PPC::STFD)).addReg(InReg), 595 FrameIndex); 596 } else { // move -> load 597 unsigned OutReg = MI->getOperand(0).getReg(); 598 NewMI = addFrameReference(BuildMI(TII.get(PPC::LFD), OutReg), FrameIndex); 599 } 600 } else if (Opc == PPC::FMRS) { 601 if (OpNum == 0) { // move -> store 602 unsigned InReg = MI->getOperand(1).getReg(); 603 NewMI = addFrameReference(BuildMI(TII.get(PPC::STFS)).addReg(InReg), 604 FrameIndex); 605 } else { // move -> load 606 unsigned OutReg = MI->getOperand(0).getReg(); 607 NewMI = addFrameReference(BuildMI(TII.get(PPC::LFS), OutReg), FrameIndex); 608 } 609 } 610 611 if (NewMI) 612 NewMI->copyKillDeadInfo(MI); 613 return NewMI; 614 } 615 616 //===----------------------------------------------------------------------===// 617 // Stack Frame Processing methods 618 //===----------------------------------------------------------------------===// 619 620 // hasFP - Return true if the specified function actually has a dedicated frame 621 // pointer register. This is true if the function needs a frame pointer and has 622 // a non-zero stack size. 623 bool PPCRegisterInfo::hasFP(const MachineFunction &MF) const { 624 const MachineFrameInfo *MFI = MF.getFrameInfo(); 625 return MFI->getStackSize() && needsFP(MF); 626 } 627 628 /// usesLR - Returns if the link registers (LR) has been used in the function. 629 /// 630 bool PPCRegisterInfo::usesLR(MachineFunction &MF) const { 631 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 632 return FI->usesLR(); 633 } 634 635 void PPCRegisterInfo:: 636 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 637 MachineBasicBlock::iterator I) const { 638 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions. 639 MBB.erase(I); 640 } 641 642 /// LowerDynamicAlloc - Generate the code for allocating an object in the 643 /// current frame. The sequence of code with be in the general form 644 /// 645 /// addi R0, SP, #frameSize ; get the address of the previous frame 646 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size 647 /// addi Rnew, SP, #maxCalFrameSize ; get the top of the allocation 648 /// 649 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const { 650 // Get the instruction. 651 MachineInstr &MI = *II; 652 // Get the instruction's basic block. 653 MachineBasicBlock &MBB = *MI.getParent(); 654 // Get the basic block's function. 655 MachineFunction &MF = *MBB.getParent(); 656 // Get the frame info. 657 MachineFrameInfo *MFI = MF.getFrameInfo(); 658 // Determine whether 64-bit pointers are used. 659 bool LP64 = Subtarget.isPPC64(); 660 661 // Get the maximum call stack size. 662 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 663 // Get the total frame size. 664 unsigned FrameSize = MFI->getStackSize(); 665 666 // Get stack alignments. 667 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 668 unsigned MaxAlign = MFI->getMaxAlignment(); 669 assert(MaxAlign <= TargetAlign && 670 "Dynamic alloca with large aligns not supported"); 671 672 // Determine the previous frame's address. If FrameSize can't be 673 // represented as 16 bits or we need special alignment, then we load the 674 // previous frame's address from 0(SP). Why not do an addis of the hi? 675 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. 676 // Constructing the constant and adding would take 3 instructions. 677 // Fortunately, a frame greater than 32K is rare. 678 if (MaxAlign < TargetAlign && isInt16(FrameSize)) { 679 BuildMI(MBB, II, TII.get(PPC::ADDI), PPC::R0) 680 .addReg(PPC::R31) 681 .addImm(FrameSize); 682 } else if (LP64) { 683 BuildMI(MBB, II, TII.get(PPC::LD), PPC::X0) 684 .addImm(0) 685 .addReg(PPC::X1); 686 } else { 687 BuildMI(MBB, II, TII.get(PPC::LWZ), PPC::R0) 688 .addImm(0) 689 .addReg(PPC::R1); 690 } 691 692 // Grow the stack and update the stack pointer link, then 693 // determine the address of new allocated space. 694 if (LP64) { 695 BuildMI(MBB, II, TII.get(PPC::STDUX)) 696 .addReg(PPC::X0) 697 .addReg(PPC::X1) 698 .addReg(MI.getOperand(1).getReg()); 699 BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 700 .addReg(PPC::X1) 701 .addImm(maxCallFrameSize); 702 } else { 703 BuildMI(MBB, II, TII.get(PPC::STWUX)) 704 .addReg(PPC::R0) 705 .addReg(PPC::R1) 706 .addReg(MI.getOperand(1).getReg()); 707 BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 708 .addReg(PPC::R1) 709 .addImm(maxCallFrameSize); 710 } 711 712 // Discard the DYNALLOC instruction. 713 MBB.erase(II); 714 } 715 716 void PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 717 int SPAdj, RegScavenger *RS) const { 718 assert(SPAdj == 0 && "Unexpected"); 719 720 // Get the instruction. 721 MachineInstr &MI = *II; 722 // Get the instruction's basic block. 723 MachineBasicBlock &MBB = *MI.getParent(); 724 // Get the basic block's function. 725 MachineFunction &MF = *MBB.getParent(); 726 // Get the frame info. 727 MachineFrameInfo *MFI = MF.getFrameInfo(); 728 729 // Find out which operand is the frame index. 730 unsigned FIOperandNo = 0; 731 while (!MI.getOperand(FIOperandNo).isFrameIndex()) { 732 ++FIOperandNo; 733 assert(FIOperandNo != MI.getNumOperands() && 734 "Instr doesn't have FrameIndex operand!"); 735 } 736 // Take into account whether it's an add or mem instruction 737 unsigned OffsetOperandNo = (FIOperandNo == 2) ? 1 : 2; 738 if (MI.getOpcode() == TargetInstrInfo::INLINEASM) 739 OffsetOperandNo = FIOperandNo-1; 740 741 // Get the frame index. 742 int FrameIndex = MI.getOperand(FIOperandNo).getFrameIndex(); 743 744 // Get the frame pointer save index. Users of this index are primarily 745 // DYNALLOC instructions. 746 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 747 int FPSI = FI->getFramePointerSaveIndex(); 748 // Get the instruction opcode. 749 unsigned OpC = MI.getOpcode(); 750 751 // Special case for dynamic alloca. 752 if (FPSI && FrameIndex == FPSI && 753 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { 754 lowerDynamicAlloc(II); 755 return; 756 } 757 758 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 759 MI.getOperand(FIOperandNo).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1, 760 false); 761 762 // Figure out if the offset in the instruction is shifted right two bits. This 763 // is true for instructions like "STD", which the machine implicitly adds two 764 // low zeros to. 765 bool isIXAddr = false; 766 switch (OpC) { 767 case PPC::LWA: 768 case PPC::LD: 769 case PPC::STD: 770 case PPC::STD_32: 771 isIXAddr = true; 772 break; 773 } 774 775 // Now add the frame object offset to the offset from r1. 776 int Offset = MFI->getObjectOffset(FrameIndex); 777 if (!isIXAddr) 778 Offset += MI.getOperand(OffsetOperandNo).getImmedValue(); 779 else 780 Offset += MI.getOperand(OffsetOperandNo).getImmedValue() << 2; 781 782 // If we're not using a Frame Pointer that has been set to the value of the 783 // SP before having the stack size subtracted from it, then add the stack size 784 // to Offset to get the correct offset. 785 Offset += MFI->getStackSize(); 786 787 // If we can, encode the offset directly into the instruction. If this is a 788 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If 789 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits 790 // clear can be encoded. This is extremely uncommon, because normally you 791 // only "std" to a stack slot that is at least 4-byte aligned, but it can 792 // happen in invalid code. 793 if (isInt16(Offset) && (!isIXAddr || (isIXAddr & 3) == 0)) { 794 if (isIXAddr) 795 Offset >>= 2; // The actual encoded value has the low two bits zero. 796 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 797 return; 798 } 799 800 // Insert a set of r0 with the full offset value before the ld, st, or add 801 BuildMI(MBB, II, TII.get(PPC::LIS), PPC::R0).addImm(Offset >> 16); 802 BuildMI(MBB, II, TII.get(PPC::ORI), PPC::R0).addReg(PPC::R0).addImm(Offset); 803 804 // Convert into indexed form of the instruction 805 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 806 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 807 unsigned OperandBase; 808 if (OpC != TargetInstrInfo::INLINEASM) { 809 assert(ImmToIdxMap.count(OpC) && 810 "No indexed form of load or store available!"); 811 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; 812 MI.setInstrDescriptor(TII.get(NewOpcode)); 813 OperandBase = 1; 814 } else { 815 OperandBase = OffsetOperandNo; 816 } 817 818 unsigned StackReg = MI.getOperand(FIOperandNo).getReg(); 819 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false); 820 MI.getOperand(OperandBase+1).ChangeToRegister(PPC::R0, false); 821 } 822 823 /// VRRegNo - Map from a numbered VR register to its enum value. 824 /// 825 static const unsigned short VRRegNo[] = { 826 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 , 827 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, 828 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, 829 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31 830 }; 831 832 /// RemoveVRSaveCode - We have found that this function does not need any code 833 /// to manipulate the VRSAVE register, even though it uses vector registers. 834 /// This can happen when the only registers used are known to be live in or out 835 /// of the function. Remove all of the VRSAVE related code from the function. 836 static void RemoveVRSaveCode(MachineInstr *MI) { 837 MachineBasicBlock *Entry = MI->getParent(); 838 MachineFunction *MF = Entry->getParent(); 839 840 // We know that the MTVRSAVE instruction immediately follows MI. Remove it. 841 MachineBasicBlock::iterator MBBI = MI; 842 ++MBBI; 843 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE); 844 MBBI->eraseFromParent(); 845 846 bool RemovedAllMTVRSAVEs = true; 847 // See if we can find and remove the MTVRSAVE instruction from all of the 848 // epilog blocks. 849 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); 850 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) { 851 // If last instruction is a return instruction, add an epilogue 852 if (!I->empty() && TII.isReturn(I->back().getOpcode())) { 853 bool FoundIt = false; 854 for (MBBI = I->end(); MBBI != I->begin(); ) { 855 --MBBI; 856 if (MBBI->getOpcode() == PPC::MTVRSAVE) { 857 MBBI->eraseFromParent(); // remove it. 858 FoundIt = true; 859 break; 860 } 861 } 862 RemovedAllMTVRSAVEs &= FoundIt; 863 } 864 } 865 866 // If we found and removed all MTVRSAVE instructions, remove the read of 867 // VRSAVE as well. 868 if (RemovedAllMTVRSAVEs) { 869 MBBI = MI; 870 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?"); 871 --MBBI; 872 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?"); 873 MBBI->eraseFromParent(); 874 } 875 876 // Finally, nuke the UPDATE_VRSAVE. 877 MI->eraseFromParent(); 878 } 879 880 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the 881 // instruction selector. Based on the vector registers that have been used, 882 // transform this into the appropriate ORI instruction. 883 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) { 884 MachineFunction *MF = MI->getParent()->getParent(); 885 886 unsigned UsedRegMask = 0; 887 for (unsigned i = 0; i != 32; ++i) 888 if (MF->isPhysRegUsed(VRRegNo[i])) 889 UsedRegMask |= 1 << (31-i); 890 891 // Live in and live out values already must be in the mask, so don't bother 892 // marking them. 893 for (MachineFunction::livein_iterator I = 894 MF->livein_begin(), E = MF->livein_end(); I != E; ++I) { 895 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first); 896 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg. 897 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 898 } 899 for (MachineFunction::liveout_iterator I = 900 MF->liveout_begin(), E = MF->liveout_end(); I != E; ++I) { 901 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I); 902 if (VRRegNo[RegNo] == *I) // If this really is a vector reg. 903 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 904 } 905 906 unsigned SrcReg = MI->getOperand(1).getReg(); 907 unsigned DstReg = MI->getOperand(0).getReg(); 908 // If no registers are used, turn this into a copy. 909 if (UsedRegMask == 0) { 910 // Remove all VRSAVE code. 911 RemoveVRSaveCode(MI); 912 return; 913 } else if ((UsedRegMask & 0xFFFF) == UsedRegMask) { 914 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg) 915 .addReg(SrcReg).addImm(UsedRegMask); 916 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { 917 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) 918 .addReg(SrcReg).addImm(UsedRegMask >> 16); 919 } else { 920 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) 921 .addReg(SrcReg).addImm(UsedRegMask >> 16); 922 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg) 923 .addReg(DstReg).addImm(UsedRegMask & 0xFFFF); 924 } 925 926 // Remove the old UPDATE_VRSAVE instruction. 927 MI->eraseFromParent(); 928 } 929 930 /// determineFrameLayout - Determine the size of the frame and maximum call 931 /// frame size. 932 void PPCRegisterInfo::determineFrameLayout(MachineFunction &MF) const { 933 MachineFrameInfo *MFI = MF.getFrameInfo(); 934 935 // Get the number of bytes to allocate from the FrameInfo 936 unsigned FrameSize = MFI->getStackSize(); 937 938 // Get the alignments provided by the target, and the maximum alignment 939 // (if any) of the fixed frame objects. 940 unsigned MaxAlign = MFI->getMaxAlignment(); 941 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 942 unsigned AlignMask = TargetAlign - 1; // 943 944 // If we are a leaf function, and use up to 224 bytes of stack space, 945 // don't have a frame pointer, calls, or dynamic alloca then we do not need 946 // to adjust the stack pointer (we fit in the Red Zone). 947 if (FrameSize <= 224 && // Fits in red zone. 948 !MFI->hasVarSizedObjects() && // No dynamic alloca. 949 !MFI->hasCalls() && // No calls. 950 MaxAlign <= TargetAlign) { // No special alignment. 951 // No need for frame 952 MFI->setStackSize(0); 953 return; 954 } 955 956 // Get the maximum call frame size of all the calls. 957 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 958 959 // Maximum call frame needs to be at least big enough for linkage and 8 args. 960 unsigned minCallFrameSize = 961 PPCFrameInfo::getMinCallFrameSize(Subtarget.isPPC64(), 962 Subtarget.isMachoABI()); 963 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize); 964 965 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so 966 // that allocations will be aligned. 967 if (MFI->hasVarSizedObjects()) 968 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask; 969 970 // Update maximum call frame size. 971 MFI->setMaxCallFrameSize(maxCallFrameSize); 972 973 // Include call frame size in total. 974 FrameSize += maxCallFrameSize; 975 976 // Make sure the frame is aligned. 977 FrameSize = (FrameSize + AlignMask) & ~AlignMask; 978 979 // Update frame info. 980 MFI->setStackSize(FrameSize); 981 } 982 983 void PPCRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 984 RegScavenger *RS) 985 const { 986 // Save and clear the LR state. 987 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 988 unsigned LR = getRARegister(); 989 FI->setUsesLR(MF.isPhysRegUsed(LR)); 990 MF.setPhysRegUnused(LR); 991 992 // Save R31 if necessary 993 int FPSI = FI->getFramePointerSaveIndex(); 994 bool IsPPC64 = Subtarget.isPPC64(); 995 bool IsELF32_ABI = Subtarget.isELF32_ABI(); 996 bool IsMachoABI = Subtarget.isMachoABI(); 997 const MachineFrameInfo *MFI = MF.getFrameInfo(); 998 999 // If the frame pointer save index hasn't been defined yet. 1000 if (!FPSI && (NoFramePointerElim || MFI->hasVarSizedObjects()) 1001 && IsELF32_ABI) { 1002 // Find out what the fix offset of the frame pointer save area. 1003 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, 1004 IsMachoABI); 1005 // Allocate the frame index for frame pointer save area. 1006 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset); 1007 // Save the result. 1008 FI->setFramePointerSaveIndex(FPSI); 1009 } 1010 1011 } 1012 1013 void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const { 1014 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB 1015 MachineBasicBlock::iterator MBBI = MBB.begin(); 1016 MachineFrameInfo *MFI = MF.getFrameInfo(); 1017 MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); 1018 1019 // Prepare for frame info. 1020 unsigned FrameLabelId = 0; 1021 1022 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it, 1023 // process it. 1024 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { 1025 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) { 1026 HandleVRSaveUpdate(MBBI, TII); 1027 break; 1028 } 1029 } 1030 1031 // Move MBBI back to the beginning of the function. 1032 MBBI = MBB.begin(); 1033 1034 // Work out frame sizes. 1035 determineFrameLayout(MF); 1036 unsigned FrameSize = MFI->getStackSize(); 1037 1038 int NegFrameSize = -FrameSize; 1039 1040 // Get processor type. 1041 bool IsPPC64 = Subtarget.isPPC64(); 1042 // Get operating system 1043 bool IsMachoABI = Subtarget.isMachoABI(); 1044 // Check if the link register (LR) has been used. 1045 bool UsesLR = MFI->hasCalls() || usesLR(MF); 1046 // Do we have a frame pointer for this function? 1047 bool HasFP = hasFP(MF) && FrameSize; 1048 1049 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI); 1050 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI); 1051 1052 if (IsPPC64) { 1053 if (UsesLR) 1054 BuildMI(MBB, MBBI, TII.get(PPC::MFLR8), PPC::X0); 1055 1056 if (HasFP) 1057 BuildMI(MBB, MBBI, TII.get(PPC::STD)) 1058 .addReg(PPC::X31).addImm(FPOffset/4).addReg(PPC::X1); 1059 1060 if (UsesLR) 1061 BuildMI(MBB, MBBI, TII.get(PPC::STD)) 1062 .addReg(PPC::X0).addImm(LROffset/4).addReg(PPC::X1); 1063 } else { 1064 if (UsesLR) 1065 BuildMI(MBB, MBBI, TII.get(PPC::MFLR), PPC::R0); 1066 1067 if (HasFP) 1068 BuildMI(MBB, MBBI, TII.get(PPC::STW)) 1069 .addReg(PPC::R31).addImm(FPOffset).addReg(PPC::R1); 1070 1071 if (UsesLR) 1072 BuildMI(MBB, MBBI, TII.get(PPC::STW)) 1073 .addReg(PPC::R0).addImm(LROffset).addReg(PPC::R1); 1074 } 1075 1076 // Skip if a leaf routine. 1077 if (!FrameSize) return; 1078 1079 // Get stack alignments. 1080 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 1081 unsigned MaxAlign = MFI->getMaxAlignment(); 1082 1083 if (MMI && MMI->needsFrameInfo()) { 1084 // Mark effective beginning of when frame pointer becomes valid. 1085 FrameLabelId = MMI->NextLabelID(); 1086 BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(FrameLabelId); 1087 } 1088 1089 // Adjust stack pointer: r1 += NegFrameSize. 1090 // If there is a preferred stack alignment, align R1 now 1091 if (!IsPPC64) { 1092 // PPC32. 1093 if (MaxAlign > TargetAlign) { 1094 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!"); 1095 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!"); 1096 BuildMI(MBB, MBBI, TII.get(PPC::RLWINM), PPC::R0) 1097 .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31); 1098 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC) ,PPC::R0).addReg(PPC::R0) 1099 .addImm(NegFrameSize); 1100 BuildMI(MBB, MBBI, TII.get(PPC::STWUX)) 1101 .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0); 1102 } else if (isInt16(NegFrameSize)) { 1103 BuildMI(MBB, MBBI, TII.get(PPC::STWU), 1104 PPC::R1).addReg(PPC::R1).addImm(NegFrameSize).addReg(PPC::R1); 1105 } else { 1106 BuildMI(MBB, MBBI, TII.get(PPC::LIS), PPC::R0).addImm(NegFrameSize >> 16); 1107 BuildMI(MBB, MBBI, TII.get(PPC::ORI), PPC::R0).addReg(PPC::R0) 1108 .addImm(NegFrameSize & 0xFFFF); 1109 BuildMI(MBB, MBBI, TII.get(PPC::STWUX)).addReg(PPC::R1).addReg(PPC::R1) 1110 .addReg(PPC::R0); 1111 } 1112 } else { // PPC64. 1113 if (MaxAlign > TargetAlign) { 1114 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!"); 1115 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!"); 1116 BuildMI(MBB, MBBI, TII.get(PPC::RLDICL), PPC::X0) 1117 .addReg(PPC::X1).addImm(0).addImm(64-Log2_32(MaxAlign)); 1118 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC8), PPC::X0).addReg(PPC::X0) 1119 .addImm(NegFrameSize); 1120 BuildMI(MBB, MBBI, TII.get(PPC::STDUX)) 1121 .addReg(PPC::X1).addReg(PPC::X1).addReg(PPC::X0); 1122 } else if (isInt16(NegFrameSize)) { 1123 BuildMI(MBB, MBBI, TII.get(PPC::STDU), PPC::X1) 1124 .addReg(PPC::X1).addImm(NegFrameSize/4).addReg(PPC::X1); 1125 } else { 1126 BuildMI(MBB, MBBI, TII.get(PPC::LIS8), PPC::X0).addImm(NegFrameSize >>16); 1127 BuildMI(MBB, MBBI, TII.get(PPC::ORI8), PPC::X0).addReg(PPC::X0) 1128 .addImm(NegFrameSize & 0xFFFF); 1129 BuildMI(MBB, MBBI, TII.get(PPC::STDUX)).addReg(PPC::X1).addReg(PPC::X1) 1130 .addReg(PPC::X0); 1131 } 1132 } 1133 1134 if (MMI && MMI->needsFrameInfo()) { 1135 std::vector<MachineMove> &Moves = MMI->getFrameMoves(); 1136 1137 if (NegFrameSize) { 1138 // Show update of SP. 1139 MachineLocation SPDst(MachineLocation::VirtualFP); 1140 MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize); 1141 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc)); 1142 } else { 1143 MachineLocation SP(IsPPC64 ? PPC::X31 : PPC::R31); 1144 Moves.push_back(MachineMove(FrameLabelId, SP, SP)); 1145 } 1146 1147 if (HasFP) { 1148 MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset); 1149 MachineLocation FPSrc(IsPPC64 ? PPC::X31 : PPC::R31); 1150 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc)); 1151 } 1152 1153 // Add callee saved registers to move list. 1154 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 1155 for (unsigned I = 0, E = CSI.size(); I != E; ++I) { 1156 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx()); 1157 unsigned Reg = CSI[I].getReg(); 1158 if (Reg == PPC::LR || Reg == PPC::LR8) continue; 1159 MachineLocation CSDst(MachineLocation::VirtualFP, Offset); 1160 MachineLocation CSSrc(Reg); 1161 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc)); 1162 } 1163 1164 MachineLocation LRDst(MachineLocation::VirtualFP, LROffset); 1165 MachineLocation LRSrc(IsPPC64 ? PPC::LR8 : PPC::LR); 1166 Moves.push_back(MachineMove(FrameLabelId, LRDst, LRSrc)); 1167 1168 // Mark effective beginning of when frame pointer is ready. 1169 unsigned ReadyLabelId = MMI->NextLabelID(); 1170 BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(ReadyLabelId); 1171 1172 MachineLocation FPDst(HasFP ? (IsPPC64 ? PPC::X31 : PPC::R31) : 1173 (IsPPC64 ? PPC::X1 : PPC::R1)); 1174 MachineLocation FPSrc(MachineLocation::VirtualFP); 1175 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc)); 1176 } 1177 1178 // If there is a frame pointer, copy R1 into R31 1179 if (HasFP) { 1180 if (!IsPPC64) { 1181 BuildMI(MBB, MBBI, TII.get(PPC::OR), PPC::R31).addReg(PPC::R1) 1182 .addReg(PPC::R1); 1183 } else { 1184 BuildMI(MBB, MBBI, TII.get(PPC::OR8), PPC::X31).addReg(PPC::X1) 1185 .addReg(PPC::X1); 1186 } 1187 } 1188 } 1189 1190 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF, 1191 MachineBasicBlock &MBB) const { 1192 MachineBasicBlock::iterator MBBI = prior(MBB.end()); 1193 assert(MBBI->getOpcode() == PPC::BLR && 1194 "Can only insert epilog into returning blocks"); 1195 1196 // Get alignment info so we know how to restore r1 1197 const MachineFrameInfo *MFI = MF.getFrameInfo(); 1198 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 1199 unsigned MaxAlign = MFI->getMaxAlignment(); 1200 1201 // Get the number of bytes allocated from the FrameInfo. 1202 unsigned FrameSize = MFI->getStackSize(); 1203 1204 // Get processor type. 1205 bool IsPPC64 = Subtarget.isPPC64(); 1206 // Get operating system 1207 bool IsMachoABI = Subtarget.isMachoABI(); 1208 // Check if the link register (LR) has been used. 1209 bool UsesLR = MFI->hasCalls() || usesLR(MF); 1210 // Do we have a frame pointer for this function? 1211 bool HasFP = hasFP(MF) && FrameSize; 1212 1213 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI); 1214 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI); 1215 1216 if (FrameSize) { 1217 // The loaded (or persistent) stack pointer value is offset by the 'stwu' 1218 // on entry to the function. Add this offset back now. 1219 if (!Subtarget.isPPC64()) { 1220 if (isInt16(FrameSize) && TargetAlign >= MaxAlign && 1221 !MFI->hasVarSizedObjects()) { 1222 BuildMI(MBB, MBBI, TII.get(PPC::ADDI), PPC::R1) 1223 .addReg(PPC::R1).addImm(FrameSize); 1224 } else { 1225 BuildMI(MBB, MBBI, TII.get(PPC::LWZ),PPC::R1).addImm(0).addReg(PPC::R1); 1226 } 1227 } else { 1228 if (isInt16(FrameSize) && TargetAlign >= MaxAlign && 1229 !MFI->hasVarSizedObjects()) { 1230 BuildMI(MBB, MBBI, TII.get(PPC::ADDI8), PPC::X1) 1231 .addReg(PPC::X1).addImm(FrameSize); 1232 } else { 1233 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X1).addImm(0).addReg(PPC::X1); 1234 } 1235 } 1236 } 1237 1238 if (IsPPC64) { 1239 if (UsesLR) 1240 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X0) 1241 .addImm(LROffset/4).addReg(PPC::X1); 1242 1243 if (HasFP) 1244 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X31) 1245 .addImm(FPOffset/4).addReg(PPC::X1); 1246 1247 if (UsesLR) 1248 BuildMI(MBB, MBBI, TII.get(PPC::MTLR8)).addReg(PPC::X0); 1249 } else { 1250 if (UsesLR) 1251 BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R0) 1252 .addImm(LROffset).addReg(PPC::R1); 1253 1254 if (HasFP) 1255 BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R31) 1256 .addImm(FPOffset).addReg(PPC::R1); 1257 1258 if (UsesLR) 1259 BuildMI(MBB, MBBI, TII.get(PPC::MTLR)).addReg(PPC::R0); 1260 } 1261 } 1262 1263 unsigned PPCRegisterInfo::getRARegister() const { 1264 return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8; 1265 } 1266 1267 unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const { 1268 if (!Subtarget.isPPC64()) 1269 return hasFP(MF) ? PPC::R31 : PPC::R1; 1270 else 1271 return hasFP(MF) ? PPC::X31 : PPC::X1; 1272 } 1273 1274 void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) 1275 const { 1276 // Initial state of the frame pointer is R1. 1277 MachineLocation Dst(MachineLocation::VirtualFP); 1278 MachineLocation Src(PPC::R1, 0); 1279 Moves.push_back(MachineMove(0, Dst, Src)); 1280 } 1281 1282 unsigned PPCRegisterInfo::getEHExceptionRegister() const { 1283 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3; 1284 } 1285 1286 unsigned PPCRegisterInfo::getEHHandlerRegister() const { 1287 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4; 1288 } 1289 1290 int PPCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { 1291 // FIXME: Most probably dwarf numbers differs for Linux and Darwin 1292 return PPCGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); 1293 } 1294 1295 #include "PPCGenRegisterInfo.inc" 1296 1297