1 //===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the TargetRegisterInfo 11 // class. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #define DEBUG_TYPE "reginfo" 16 #include "PPCRegisterInfo.h" 17 #include "PPC.h" 18 #include "PPCFrameLowering.h" 19 #include "PPCInstrBuilder.h" 20 #include "PPCMachineFunctionInfo.h" 21 #include "PPCSubtarget.h" 22 #include "llvm/ADT/BitVector.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/CodeGen/MachineFrameInfo.h" 25 #include "llvm/CodeGen/MachineFunction.h" 26 #include "llvm/CodeGen/MachineInstrBuilder.h" 27 #include "llvm/CodeGen/MachineModuleInfo.h" 28 #include "llvm/CodeGen/MachineRegisterInfo.h" 29 #include "llvm/CodeGen/RegisterScavenging.h" 30 #include "llvm/CodeGen/ValueTypes.h" 31 #include "llvm/IR/CallingConv.h" 32 #include "llvm/IR/Constants.h" 33 #include "llvm/IR/Function.h" 34 #include "llvm/IR/Type.h" 35 #include "llvm/Support/CommandLine.h" 36 #include "llvm/Support/Debug.h" 37 #include "llvm/Support/ErrorHandling.h" 38 #include "llvm/Support/MathExtras.h" 39 #include "llvm/Support/raw_ostream.h" 40 #include "llvm/Target/TargetFrameLowering.h" 41 #include "llvm/Target/TargetInstrInfo.h" 42 #include "llvm/Target/TargetMachine.h" 43 #include "llvm/Target/TargetOptions.h" 44 #include <cstdlib> 45 46 #define GET_REGINFO_TARGET_DESC 47 #include "PPCGenRegisterInfo.inc" 48 49 using namespace llvm; 50 51 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST, 52 const TargetInstrInfo &tii) 53 : PPCGenRegisterInfo(ST.isPPC64() ? PPC::LR8 : PPC::LR, 54 ST.isPPC64() ? 0 : 1, 55 ST.isPPC64() ? 0 : 1), 56 Subtarget(ST), TII(tii) { 57 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 58 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 59 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 60 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 61 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 62 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 63 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 64 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 65 66 // 64-bit 67 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8; 68 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8; 69 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8; 70 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX; 71 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; 72 } 73 74 /// getPointerRegClass - Return the register class to use to hold pointers. 75 /// This is used for addressing modes. 76 const TargetRegisterClass * 77 PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) 78 const { 79 // Note that PPCInstrInfo::FoldImmediate also directly uses this Kind value 80 // when it checks for ZERO folding. 81 if (Kind == 1) { 82 if (Subtarget.isPPC64()) 83 return &PPC::G8RC_NOX0RegClass; 84 return &PPC::GPRC_NOR0RegClass; 85 } 86 87 if (Subtarget.isPPC64()) 88 return &PPC::G8RCRegClass; 89 return &PPC::GPRCRegClass; 90 } 91 92 const uint16_t* 93 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 94 if (Subtarget.isDarwinABI()) 95 return Subtarget.isPPC64() ? CSR_Darwin64_SaveList : 96 CSR_Darwin32_SaveList; 97 98 return Subtarget.isPPC64() ? CSR_SVR464_SaveList : CSR_SVR432_SaveList; 99 } 100 101 const uint32_t* 102 PPCRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const { 103 if (Subtarget.isDarwinABI()) 104 return Subtarget.isPPC64() ? CSR_Darwin64_RegMask : 105 CSR_Darwin32_RegMask; 106 107 return Subtarget.isPPC64() ? CSR_SVR464_RegMask : CSR_SVR432_RegMask; 108 } 109 110 const uint32_t* 111 PPCRegisterInfo::getNoPreservedMask() const { 112 // The naming here is inverted: The CSR_NoRegs_Altivec has the 113 // Altivec registers masked so that they're not saved and restored around 114 // instructions with this preserved mask. 115 116 if (!Subtarget.hasAltivec()) 117 return CSR_NoRegs_Altivec_RegMask; 118 119 if (Subtarget.isDarwin()) 120 return CSR_NoRegs_Darwin_RegMask; 121 return CSR_NoRegs_RegMask; 122 } 123 124 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 125 BitVector Reserved(getNumRegs()); 126 const PPCFrameLowering *PPCFI = 127 static_cast<const PPCFrameLowering*>(MF.getTarget().getFrameLowering()); 128 129 // The ZERO register is not really a register, but the representation of r0 130 // when used in instructions that treat r0 as the constant 0. 131 Reserved.set(PPC::ZERO); 132 Reserved.set(PPC::ZERO8); 133 134 // The FP register is also not really a register, but is the representation 135 // of the frame pointer register used by ISD::FRAMEADDR. 136 Reserved.set(PPC::FP); 137 Reserved.set(PPC::FP8); 138 139 Reserved.set(PPC::R1); 140 Reserved.set(PPC::LR); 141 Reserved.set(PPC::LR8); 142 Reserved.set(PPC::RM); 143 144 // The SVR4 ABI reserves r2 and r13 145 if (Subtarget.isSVR4ABI()) { 146 Reserved.set(PPC::R2); // System-reserved register 147 Reserved.set(PPC::R13); // Small Data Area pointer register 148 } 149 150 // On PPC64, r13 is the thread pointer. Never allocate this register. 151 if (Subtarget.isPPC64()) { 152 Reserved.set(PPC::R13); 153 154 Reserved.set(PPC::X1); 155 Reserved.set(PPC::X13); 156 157 if (PPCFI->needsFP(MF)) 158 Reserved.set(PPC::X31); 159 160 // The 64-bit SVR4 ABI reserves r2 for the TOC pointer. 161 if (Subtarget.isSVR4ABI()) { 162 Reserved.set(PPC::X2); 163 } 164 } 165 166 if (PPCFI->needsFP(MF)) 167 Reserved.set(PPC::R31); 168 169 return Reserved; 170 } 171 172 unsigned 173 PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 174 MachineFunction &MF) const { 175 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 176 const unsigned DefaultSafety = 1; 177 178 switch (RC->getID()) { 179 default: 180 return 0; 181 case PPC::G8RC_NOX0RegClassID: 182 case PPC::GPRC_NOR0RegClassID: 183 case PPC::G8RCRegClassID: 184 case PPC::GPRCRegClassID: { 185 unsigned FP = TFI->hasFP(MF) ? 1 : 0; 186 return 32 - FP - DefaultSafety; 187 } 188 case PPC::F8RCRegClassID: 189 case PPC::F4RCRegClassID: 190 case PPC::VRRCRegClassID: 191 return 32 - DefaultSafety; 192 case PPC::CRRCRegClassID: 193 return 8 - DefaultSafety; 194 } 195 } 196 197 //===----------------------------------------------------------------------===// 198 // Stack Frame Processing methods 199 //===----------------------------------------------------------------------===// 200 201 /// lowerDynamicAlloc - Generate the code for allocating an object in the 202 /// current frame. The sequence of code with be in the general form 203 /// 204 /// addi R0, SP, \#frameSize ; get the address of the previous frame 205 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size 206 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation 207 /// 208 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const { 209 // Get the instruction. 210 MachineInstr &MI = *II; 211 // Get the instruction's basic block. 212 MachineBasicBlock &MBB = *MI.getParent(); 213 // Get the basic block's function. 214 MachineFunction &MF = *MBB.getParent(); 215 // Get the frame info. 216 MachineFrameInfo *MFI = MF.getFrameInfo(); 217 // Determine whether 64-bit pointers are used. 218 bool LP64 = Subtarget.isPPC64(); 219 DebugLoc dl = MI.getDebugLoc(); 220 221 // Get the maximum call stack size. 222 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 223 // Get the total frame size. 224 unsigned FrameSize = MFI->getStackSize(); 225 226 // Get stack alignments. 227 unsigned TargetAlign = MF.getTarget().getFrameLowering()->getStackAlignment(); 228 unsigned MaxAlign = MFI->getMaxAlignment(); 229 if (MaxAlign > TargetAlign) 230 report_fatal_error("Dynamic alloca with large aligns not supported"); 231 232 // Determine the previous frame's address. If FrameSize can't be 233 // represented as 16 bits or we need special alignment, then we load the 234 // previous frame's address from 0(SP). Why not do an addis of the hi? 235 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. 236 // Constructing the constant and adding would take 3 instructions. 237 // Fortunately, a frame greater than 32K is rare. 238 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 239 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 240 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 241 242 if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) { 243 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) 244 .addReg(PPC::R31) 245 .addImm(FrameSize); 246 } else if (LP64) { 247 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg) 248 .addImm(0) 249 .addReg(PPC::X1); 250 } else { 251 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) 252 .addImm(0) 253 .addReg(PPC::R1); 254 } 255 256 // Grow the stack and update the stack pointer link, then determine the 257 // address of new allocated space. 258 if (LP64) { 259 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1) 260 .addReg(Reg, RegState::Kill) 261 .addReg(PPC::X1) 262 .addReg(MI.getOperand(1).getReg()); 263 if (!MI.getOperand(1).isKill()) 264 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 265 .addReg(PPC::X1) 266 .addImm(maxCallFrameSize); 267 else 268 // Implicitly kill the register. 269 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 270 .addReg(PPC::X1) 271 .addImm(maxCallFrameSize) 272 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill); 273 } else { 274 BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1) 275 .addReg(Reg, RegState::Kill) 276 .addReg(PPC::R1) 277 .addReg(MI.getOperand(1).getReg()); 278 279 if (!MI.getOperand(1).isKill()) 280 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 281 .addReg(PPC::R1) 282 .addImm(maxCallFrameSize); 283 else 284 // Implicitly kill the register. 285 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 286 .addReg(PPC::R1) 287 .addImm(maxCallFrameSize) 288 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill); 289 } 290 291 // Discard the DYNALLOC instruction. 292 MBB.erase(II); 293 } 294 295 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of 296 /// reserving a whole register (R0), we scrounge for one here. This generates 297 /// code like this: 298 /// 299 /// mfcr rA ; Move the conditional register into GPR rA. 300 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot. 301 /// stw rA, FI ; Store rA to the frame. 302 /// 303 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, 304 unsigned FrameIndex) const { 305 // Get the instruction. 306 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset> 307 // Get the instruction's basic block. 308 MachineBasicBlock &MBB = *MI.getParent(); 309 MachineFunction &MF = *MBB.getParent(); 310 DebugLoc dl = MI.getDebugLoc(); 311 312 bool LP64 = Subtarget.isPPC64(); 313 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 314 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 315 316 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 317 unsigned SrcReg = MI.getOperand(0).getReg(); 318 319 // We need to store the CR in the low 4-bits of the saved value. First, issue 320 // an MFCRpsued to save all of the CRBits and, if needed, kill the SrcReg. 321 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFCR8pseud : PPC::MFCRpseud), Reg) 322 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 323 324 // If the saved register wasn't CR0, shift the bits left so that they are in 325 // CR0's slot. 326 if (SrcReg != PPC::CR0) { 327 unsigned Reg1 = Reg; 328 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 329 330 // rlwinm rA, rA, ShiftBits, 0, 31. 331 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 332 .addReg(Reg1, RegState::Kill) 333 .addImm(getEncodingValue(SrcReg) * 4) 334 .addImm(0) 335 .addImm(31); 336 } 337 338 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW)) 339 .addReg(Reg, RegState::Kill), 340 FrameIndex); 341 342 // Discard the pseudo instruction. 343 MBB.erase(II); 344 } 345 346 void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II, 347 unsigned FrameIndex) const { 348 // Get the instruction. 349 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset> 350 // Get the instruction's basic block. 351 MachineBasicBlock &MBB = *MI.getParent(); 352 MachineFunction &MF = *MBB.getParent(); 353 DebugLoc dl = MI.getDebugLoc(); 354 355 bool LP64 = Subtarget.isPPC64(); 356 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 357 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 358 359 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 360 unsigned DestReg = MI.getOperand(0).getReg(); 361 assert(MI.definesRegister(DestReg) && 362 "RESTORE_CR does not define its destination"); 363 364 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), 365 Reg), FrameIndex); 366 367 // If the reloaded register isn't CR0, shift the bits right so that they are 368 // in the right CR's slot. 369 if (DestReg != PPC::CR0) { 370 unsigned Reg1 = Reg; 371 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 372 373 unsigned ShiftBits = getEncodingValue(DestReg)*4; 374 // rlwinm r11, r11, 32-ShiftBits, 0, 31. 375 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 376 .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0) 377 .addImm(31); 378 } 379 380 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTCRF8 : PPC::MTCRF), DestReg) 381 .addReg(Reg, RegState::Kill); 382 383 // Discard the pseudo instruction. 384 MBB.erase(II); 385 } 386 387 void PPCRegisterInfo::lowerVRSAVESpilling(MachineBasicBlock::iterator II, 388 unsigned FrameIndex) const { 389 // Get the instruction. 390 MachineInstr &MI = *II; // ; SPILL_VRSAVE <SrcReg>, <offset> 391 // Get the instruction's basic block. 392 MachineBasicBlock &MBB = *MI.getParent(); 393 MachineFunction &MF = *MBB.getParent(); 394 DebugLoc dl = MI.getDebugLoc(); 395 396 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 397 unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC); 398 unsigned SrcReg = MI.getOperand(0).getReg(); 399 400 BuildMI(MBB, II, dl, TII.get(PPC::MFVRSAVEv), Reg) 401 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 402 403 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::STW)) 404 .addReg(Reg, RegState::Kill), 405 FrameIndex); 406 407 // Discard the pseudo instruction. 408 MBB.erase(II); 409 } 410 411 void PPCRegisterInfo::lowerVRSAVERestore(MachineBasicBlock::iterator II, 412 unsigned FrameIndex) const { 413 // Get the instruction. 414 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_VRSAVE <offset> 415 // Get the instruction's basic block. 416 MachineBasicBlock &MBB = *MI.getParent(); 417 MachineFunction &MF = *MBB.getParent(); 418 DebugLoc dl = MI.getDebugLoc(); 419 420 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 421 unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC); 422 unsigned DestReg = MI.getOperand(0).getReg(); 423 assert(MI.definesRegister(DestReg) && 424 "RESTORE_VRSAVE does not define its destination"); 425 426 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::LWZ), 427 Reg), FrameIndex); 428 429 BuildMI(MBB, II, dl, TII.get(PPC::MTVRSAVEv), DestReg) 430 .addReg(Reg, RegState::Kill); 431 432 // Discard the pseudo instruction. 433 MBB.erase(II); 434 } 435 436 bool 437 PPCRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF, 438 unsigned Reg, int &FrameIdx) const { 439 440 // For the nonvolatile condition registers (CR2, CR3, CR4) in an SVR4 441 // ABI, return true to prevent allocating an additional frame slot. 442 // For 64-bit, the CR save area is at SP+8; the value of FrameIdx = 0 443 // is arbitrary and will be subsequently ignored. For 32-bit, we have 444 // previously created the stack slot if needed, so return its FrameIdx. 445 if (Subtarget.isSVR4ABI() && PPC::CR2 <= Reg && Reg <= PPC::CR4) { 446 if (Subtarget.isPPC64()) 447 FrameIdx = 0; 448 else { 449 const PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 450 FrameIdx = FI->getCRSpillFrameIndex(); 451 } 452 return true; 453 } 454 return false; 455 } 456 457 // Figure out if the offset in the instruction is shifted right two bits. This 458 // is true for instructions like "STD", which the machine implicitly adds two 459 // low zeros to. 460 static bool usesIXAddr(const MachineInstr &MI) { 461 unsigned OpC = MI.getOpcode(); 462 463 switch (OpC) { 464 default: 465 return false; 466 case PPC::LWA: 467 case PPC::LD: 468 case PPC::STD: 469 return true; 470 } 471 } 472 473 // Return the OffsetOperandNo given the FIOperandNum (and the instruction). 474 static unsigned getOffsetONFromFION(const MachineInstr &MI, 475 unsigned FIOperandNum) { 476 // Take into account whether it's an add or mem instruction 477 unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2; 478 if (MI.isInlineAsm()) 479 OffsetOperandNo = FIOperandNum-1; 480 481 return OffsetOperandNo; 482 } 483 484 void 485 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 486 int SPAdj, unsigned FIOperandNum, 487 RegScavenger *RS) const { 488 assert(SPAdj == 0 && "Unexpected"); 489 490 // Get the instruction. 491 MachineInstr &MI = *II; 492 // Get the instruction's basic block. 493 MachineBasicBlock &MBB = *MI.getParent(); 494 // Get the basic block's function. 495 MachineFunction &MF = *MBB.getParent(); 496 // Get the frame info. 497 MachineFrameInfo *MFI = MF.getFrameInfo(); 498 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 499 DebugLoc dl = MI.getDebugLoc(); 500 501 unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum); 502 503 // Get the frame index. 504 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 505 506 // Get the frame pointer save index. Users of this index are primarily 507 // DYNALLOC instructions. 508 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 509 int FPSI = FI->getFramePointerSaveIndex(); 510 // Get the instruction opcode. 511 unsigned OpC = MI.getOpcode(); 512 513 // Special case for dynamic alloca. 514 if (FPSI && FrameIndex == FPSI && 515 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { 516 lowerDynamicAlloc(II); 517 return; 518 } 519 520 // Special case for pseudo-ops SPILL_CR and RESTORE_CR, etc. 521 if (OpC == PPC::SPILL_CR) { 522 lowerCRSpilling(II, FrameIndex); 523 return; 524 } else if (OpC == PPC::RESTORE_CR) { 525 lowerCRRestore(II, FrameIndex); 526 return; 527 } else if (OpC == PPC::SPILL_VRSAVE) { 528 lowerVRSAVESpilling(II, FrameIndex); 529 return; 530 } else if (OpC == PPC::RESTORE_VRSAVE) { 531 lowerVRSAVERestore(II, FrameIndex); 532 return; 533 } 534 535 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 536 537 bool is64Bit = Subtarget.isPPC64(); 538 MI.getOperand(FIOperandNum).ChangeToRegister(TFI->hasFP(MF) ? 539 (is64Bit ? PPC::X31 : PPC::R31) : 540 (is64Bit ? PPC::X1 : PPC::R1), 541 false); 542 543 // Figure out if the offset in the instruction is shifted right two bits. 544 bool isIXAddr = usesIXAddr(MI); 545 546 // If the instruction is not present in ImmToIdxMap, then it has no immediate 547 // form (and must be r+r). 548 bool noImmForm = !MI.isInlineAsm() && !ImmToIdxMap.count(OpC); 549 550 // Now add the frame object offset to the offset from r1. 551 int Offset = MFI->getObjectOffset(FrameIndex); 552 if (!isIXAddr) 553 Offset += MI.getOperand(OffsetOperandNo).getImm(); 554 else 555 Offset += MI.getOperand(OffsetOperandNo).getImm() << 2; 556 557 // If we're not using a Frame Pointer that has been set to the value of the 558 // SP before having the stack size subtracted from it, then add the stack size 559 // to Offset to get the correct offset. 560 // Naked functions have stack size 0, although getStackSize may not reflect that 561 // because we didn't call all the pieces that compute it for naked functions. 562 if (!MF.getFunction()->getAttributes(). 563 hasAttribute(AttributeSet::FunctionIndex, Attribute::Naked)) 564 Offset += MFI->getStackSize(); 565 566 // If we can, encode the offset directly into the instruction. If this is a 567 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If 568 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits 569 // clear can be encoded. This is extremely uncommon, because normally you 570 // only "std" to a stack slot that is at least 4-byte aligned, but it can 571 // happen in invalid code. 572 if (OpC == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm 573 (!noImmForm && 574 isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0))) { 575 if (isIXAddr) 576 Offset >>= 2; // The actual encoded value has the low two bits zero. 577 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 578 return; 579 } 580 581 // The offset doesn't fit into a single register, scavenge one to build the 582 // offset in. 583 584 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 585 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 586 const TargetRegisterClass *RC = is64Bit ? G8RC : GPRC; 587 unsigned SRegHi = MF.getRegInfo().createVirtualRegister(RC), 588 SReg = MF.getRegInfo().createVirtualRegister(RC); 589 590 // Insert a set of rA with the full offset value before the ld, st, or add 591 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SRegHi) 592 .addImm(Offset >> 16); 593 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg) 594 .addReg(SRegHi, RegState::Kill) 595 .addImm(Offset); 596 597 // Convert into indexed form of the instruction: 598 // 599 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 600 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 601 unsigned OperandBase; 602 603 if (noImmForm) 604 OperandBase = 1; 605 else if (OpC != TargetOpcode::INLINEASM) { 606 assert(ImmToIdxMap.count(OpC) && 607 "No indexed form of load or store available!"); 608 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; 609 MI.setDesc(TII.get(NewOpcode)); 610 OperandBase = 1; 611 } else { 612 OperandBase = OffsetOperandNo; 613 } 614 615 unsigned StackReg = MI.getOperand(FIOperandNum).getReg(); 616 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false); 617 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true); 618 } 619 620 unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 621 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 622 623 if (!Subtarget.isPPC64()) 624 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1; 625 else 626 return TFI->hasFP(MF) ? PPC::X31 : PPC::X1; 627 } 628 629 unsigned PPCRegisterInfo::getEHExceptionRegister() const { 630 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3; 631 } 632 633 unsigned PPCRegisterInfo::getEHHandlerRegister() const { 634 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4; 635 } 636 637 /// Returns true if the instruction's frame index 638 /// reference would be better served by a base register other than FP 639 /// or SP. Used by LocalStackFrameAllocation to determine which frame index 640 /// references it should create new base registers for. 641 bool PPCRegisterInfo:: 642 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { 643 assert(Offset < 0 && "Local offset must be negative"); 644 645 unsigned FIOperandNum = 0; 646 while (!MI->getOperand(FIOperandNum).isFI()) { 647 ++FIOperandNum; 648 assert(FIOperandNum < MI->getNumOperands() && 649 "Instr doesn't have FrameIndex operand!"); 650 } 651 652 unsigned OffsetOperandNo = getOffsetONFromFION(*MI, FIOperandNum); 653 654 if (!usesIXAddr(*MI)) 655 Offset += MI->getOperand(OffsetOperandNo).getImm(); 656 else 657 Offset += MI->getOperand(OffsetOperandNo).getImm() << 2; 658 659 // It's the load/store FI references that cause issues, as it can be difficult 660 // to materialize the offset if it won't fit in the literal field. Estimate 661 // based on the size of the local frame and some conservative assumptions 662 // about the rest of the stack frame (note, this is pre-regalloc, so 663 // we don't know everything for certain yet) whether this offset is likely 664 // to be out of range of the immediate. Return true if so. 665 666 // We only generate virtual base registers for loads and stores that have 667 // an r+i form. Return false for everything else. 668 unsigned OpC = MI->getOpcode(); 669 if (!ImmToIdxMap.count(OpC)) 670 return false; 671 672 // Don't generate a new virtual base register just to add zero to it. 673 if ((OpC == PPC::ADDI || OpC == PPC::ADDI8) && 674 MI->getOperand(2).getImm() == 0) 675 return false; 676 677 MachineBasicBlock &MBB = *MI->getParent(); 678 MachineFunction &MF = *MBB.getParent(); 679 680 const PPCFrameLowering *PPCFI = 681 static_cast<const PPCFrameLowering*>(MF.getTarget().getFrameLowering()); 682 unsigned StackEst = 683 PPCFI->determineFrameLayout(MF, false, true); 684 685 // If we likely don't need a stack frame, then we probably don't need a 686 // virtual base register either. 687 if (!StackEst) 688 return false; 689 690 // Estimate an offset from the stack pointer. 691 // The incoming offset is relating to the SP at the start of the function, 692 // but when we access the local it'll be relative to the SP after local 693 // allocation, so adjust our SP-relative offset by that allocation size. 694 Offset += StackEst; 695 696 // The frame pointer will point to the end of the stack, so estimate the 697 // offset as the difference between the object offset and the FP location. 698 return !isFrameOffsetLegal(MI, Offset); 699 } 700 701 /// Insert defining instruction(s) for BaseReg to 702 /// be a pointer to FrameIdx at the beginning of the basic block. 703 void PPCRegisterInfo:: 704 materializeFrameBaseRegister(MachineBasicBlock *MBB, 705 unsigned BaseReg, int FrameIdx, 706 int64_t Offset) const { 707 unsigned ADDriOpc = Subtarget.isPPC64() ? PPC::ADDI8 : PPC::ADDI; 708 709 MachineBasicBlock::iterator Ins = MBB->begin(); 710 DebugLoc DL; // Defaults to "unknown" 711 if (Ins != MBB->end()) 712 DL = Ins->getDebugLoc(); 713 714 const MCInstrDesc &MCID = TII.get(ADDriOpc); 715 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 716 const MachineFunction &MF = *MBB->getParent(); 717 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); 718 719 BuildMI(*MBB, Ins, DL, MCID, BaseReg) 720 .addFrameIndex(FrameIdx).addImm(Offset); 721 } 722 723 void 724 PPCRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I, 725 unsigned BaseReg, int64_t Offset) const { 726 MachineInstr &MI = *I; 727 728 unsigned FIOperandNum = 0; 729 while (!MI.getOperand(FIOperandNum).isFI()) { 730 ++FIOperandNum; 731 assert(FIOperandNum < MI.getNumOperands() && 732 "Instr doesn't have FrameIndex operand!"); 733 } 734 735 MI.getOperand(FIOperandNum).ChangeToRegister(BaseReg, false); 736 unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum); 737 738 bool isIXAddr = usesIXAddr(MI); 739 if (!isIXAddr) 740 Offset += MI.getOperand(OffsetOperandNo).getImm(); 741 else 742 Offset += MI.getOperand(OffsetOperandNo).getImm() << 2; 743 744 // Figure out if the offset in the instruction is shifted right two bits. 745 if (isIXAddr) 746 Offset >>= 2; // The actual encoded value has the low two bits zero. 747 748 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 749 } 750 751 bool PPCRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, 752 int64_t Offset) const { 753 return MI->getOpcode() == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm 754 (isInt<16>(Offset) && (!usesIXAddr(*MI) || (Offset & 3) == 0)); 755 } 756 757