1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the TargetRegisterInfo 11 // class. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #define DEBUG_TYPE "reginfo" 16 #include "PPC.h" 17 #include "PPCInstrBuilder.h" 18 #include "PPCMachineFunctionInfo.h" 19 #include "PPCRegisterInfo.h" 20 #include "PPCFrameLowering.h" 21 #include "PPCSubtarget.h" 22 #include "llvm/CallingConv.h" 23 #include "llvm/Constants.h" 24 #include "llvm/Function.h" 25 #include "llvm/Type.h" 26 #include "llvm/CodeGen/ValueTypes.h" 27 #include "llvm/CodeGen/MachineInstrBuilder.h" 28 #include "llvm/CodeGen/MachineModuleInfo.h" 29 #include "llvm/CodeGen/MachineFunction.h" 30 #include "llvm/CodeGen/MachineFrameInfo.h" 31 #include "llvm/CodeGen/MachineRegisterInfo.h" 32 #include "llvm/CodeGen/RegisterScavenging.h" 33 #include "llvm/Target/TargetFrameLowering.h" 34 #include "llvm/Target/TargetInstrInfo.h" 35 #include "llvm/Target/TargetMachine.h" 36 #include "llvm/Target/TargetOptions.h" 37 #include "llvm/Support/CommandLine.h" 38 #include "llvm/Support/Debug.h" 39 #include "llvm/Support/ErrorHandling.h" 40 #include "llvm/Support/MathExtras.h" 41 #include "llvm/Support/raw_ostream.h" 42 #include "llvm/ADT/BitVector.h" 43 #include "llvm/ADT/STLExtras.h" 44 #include <cstdlib> 45 46 #define GET_REGINFO_TARGET_DESC 47 #include "PPCGenRegisterInfo.inc" 48 49 // FIXME (64-bit): Eventually enable by default. 50 namespace llvm { 51 cl::opt<bool> EnablePPC32RS("enable-ppc32-regscavenger", 52 cl::init(false), 53 cl::desc("Enable PPC32 register scavenger"), 54 cl::Hidden); 55 cl::opt<bool> EnablePPC64RS("enable-ppc64-regscavenger", 56 cl::init(false), 57 cl::desc("Enable PPC64 register scavenger"), 58 cl::Hidden); 59 } 60 61 using namespace llvm; 62 63 // FIXME (64-bit): Should be inlined. 64 bool 65 PPCRegisterInfo::requiresRegisterScavenging(const MachineFunction &) const { 66 return ((EnablePPC32RS && !Subtarget.isPPC64()) || 67 (EnablePPC64RS && Subtarget.isPPC64())); 68 } 69 70 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST, 71 const TargetInstrInfo &tii) 72 : PPCGenRegisterInfo(ST.isPPC64() ? PPC::LR8 : PPC::LR, 73 ST.isPPC64() ? 0 : 1, 74 ST.isPPC64() ? 0 : 1), 75 Subtarget(ST), TII(tii) { 76 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 77 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 78 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 79 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 80 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 81 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 82 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 83 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 84 85 // 64-bit 86 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8; 87 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8; 88 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8; 89 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX; 90 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32; 91 } 92 93 /// getPointerRegClass - Return the register class to use to hold pointers. 94 /// This is used for addressing modes. 95 const TargetRegisterClass * 96 PPCRegisterInfo::getPointerRegClass(unsigned Kind) const { 97 if (Subtarget.isPPC64()) 98 return &PPC::G8RCRegClass; 99 return &PPC::GPRCRegClass; 100 } 101 102 const unsigned* 103 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 104 // 32-bit Darwin calling convention. 105 static const unsigned Darwin32_CalleeSavedRegs[] = { 106 PPC::R13, PPC::R14, PPC::R15, 107 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 108 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 109 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 110 PPC::R28, PPC::R29, PPC::R30, PPC::R31, 111 112 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 113 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 114 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 115 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 116 PPC::F30, PPC::F31, 117 118 PPC::CR2, PPC::CR3, PPC::CR4, 119 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 120 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 121 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 122 123 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 124 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 125 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 126 127 PPC::LR, 0 128 }; 129 130 // 32-bit SVR4 calling convention. 131 static const unsigned SVR4_CalleeSavedRegs[] = { 132 PPC::R14, PPC::R15, 133 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 134 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 135 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 136 PPC::R28, PPC::R29, PPC::R30, PPC::R31, 137 138 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 139 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 140 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 141 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 142 PPC::F30, PPC::F31, 143 144 PPC::CR2, PPC::CR3, PPC::CR4, 145 146 PPC::VRSAVE, 147 148 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 149 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 150 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 151 152 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 153 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 154 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 155 156 0 157 }; 158 // 64-bit Darwin calling convention. 159 static const unsigned Darwin64_CalleeSavedRegs[] = { 160 PPC::X14, PPC::X15, 161 PPC::X16, PPC::X17, PPC::X18, PPC::X19, 162 PPC::X20, PPC::X21, PPC::X22, PPC::X23, 163 PPC::X24, PPC::X25, PPC::X26, PPC::X27, 164 PPC::X28, PPC::X29, PPC::X30, PPC::X31, 165 166 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 167 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 168 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 169 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 170 PPC::F30, PPC::F31, 171 172 PPC::CR2, PPC::CR3, PPC::CR4, 173 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 174 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 175 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 176 177 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 178 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 179 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 180 181 PPC::LR8, 0 182 }; 183 184 // 64-bit SVR4 calling convention. 185 static const unsigned SVR4_64_CalleeSavedRegs[] = { 186 PPC::X14, PPC::X15, 187 PPC::X16, PPC::X17, PPC::X18, PPC::X19, 188 PPC::X20, PPC::X21, PPC::X22, PPC::X23, 189 PPC::X24, PPC::X25, PPC::X26, PPC::X27, 190 PPC::X28, PPC::X29, PPC::X30, PPC::X31, 191 192 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 193 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 194 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 195 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 196 PPC::F30, PPC::F31, 197 198 PPC::CR2, PPC::CR3, PPC::CR4, 199 200 PPC::VRSAVE, 201 202 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 203 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 204 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 205 206 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 207 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 208 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 209 210 0 211 }; 212 213 if (Subtarget.isDarwinABI()) 214 return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegs : 215 Darwin32_CalleeSavedRegs; 216 217 return Subtarget.isPPC64() ? SVR4_64_CalleeSavedRegs : SVR4_CalleeSavedRegs; 218 } 219 220 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 221 BitVector Reserved(getNumRegs()); 222 const PPCFrameLowering *PPCFI = 223 static_cast<const PPCFrameLowering*>(MF.getTarget().getFrameLowering()); 224 225 Reserved.set(PPC::R0); 226 Reserved.set(PPC::R1); 227 Reserved.set(PPC::LR); 228 Reserved.set(PPC::LR8); 229 Reserved.set(PPC::RM); 230 231 // The SVR4 ABI reserves r2 and r13 232 if (Subtarget.isSVR4ABI()) { 233 Reserved.set(PPC::R2); // System-reserved register 234 Reserved.set(PPC::R13); // Small Data Area pointer register 235 } 236 // Reserve R2 on Darwin to hack around the problem of save/restore of CR 237 // when the stack frame is too big to address directly; we need two regs. 238 // This is a hack. 239 if (Subtarget.isDarwinABI()) { 240 Reserved.set(PPC::R2); 241 } 242 243 // On PPC64, r13 is the thread pointer. Never allocate this register. 244 // Note that this is over conservative, as it also prevents allocation of R31 245 // when the FP is not needed. 246 if (Subtarget.isPPC64()) { 247 Reserved.set(PPC::R13); 248 Reserved.set(PPC::R31); 249 250 if (!requiresRegisterScavenging(MF)) 251 Reserved.set(PPC::R0); // FIXME (64-bit): Remove 252 253 Reserved.set(PPC::X0); 254 Reserved.set(PPC::X1); 255 Reserved.set(PPC::X13); 256 Reserved.set(PPC::X31); 257 258 // The 64-bit SVR4 ABI reserves r2 for the TOC pointer. 259 if (Subtarget.isSVR4ABI()) { 260 Reserved.set(PPC::X2); 261 } 262 // Reserve R2 on Darwin to hack around the problem of save/restore of CR 263 // when the stack frame is too big to address directly; we need two regs. 264 // This is a hack. 265 if (Subtarget.isDarwinABI()) { 266 Reserved.set(PPC::X2); 267 } 268 } 269 270 if (PPCFI->needsFP(MF)) 271 Reserved.set(PPC::R31); 272 273 return Reserved; 274 } 275 276 unsigned 277 PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 278 MachineFunction &MF) const { 279 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 280 const unsigned DefaultSafety = 1; 281 282 switch (RC->getID()) { 283 default: 284 return 0; 285 case PPC::G8RCRegClassID: 286 case PPC::GPRCRegClassID: { 287 unsigned FP = TFI->hasFP(MF) ? 1 : 0; 288 return 32 - FP - DefaultSafety; 289 } 290 case PPC::F8RCRegClassID: 291 case PPC::F4RCRegClassID: 292 case PPC::VRRCRegClassID: 293 return 32 - DefaultSafety; 294 case PPC::CRRCRegClassID: 295 return 8 - DefaultSafety; 296 } 297 } 298 299 //===----------------------------------------------------------------------===// 300 // Stack Frame Processing methods 301 //===----------------------------------------------------------------------===// 302 303 void PPCRegisterInfo:: 304 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 305 MachineBasicBlock::iterator I) const { 306 if (MF.getTarget().Options.GuaranteedTailCallOpt && 307 I->getOpcode() == PPC::ADJCALLSTACKUP) { 308 // Add (actually subtract) back the amount the callee popped on return. 309 if (int CalleeAmt = I->getOperand(1).getImm()) { 310 bool is64Bit = Subtarget.isPPC64(); 311 CalleeAmt *= -1; 312 unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1; 313 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0; 314 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI; 315 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4; 316 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS; 317 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI; 318 MachineInstr *MI = I; 319 DebugLoc dl = MI->getDebugLoc(); 320 321 if (isInt<16>(CalleeAmt)) { 322 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg).addReg(StackReg). 323 addImm(CalleeAmt); 324 } else { 325 MachineBasicBlock::iterator MBBI = I; 326 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) 327 .addImm(CalleeAmt >> 16); 328 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) 329 .addReg(TmpReg, RegState::Kill) 330 .addImm(CalleeAmt & 0xFFFF); 331 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr)) 332 .addReg(StackReg) 333 .addReg(StackReg) 334 .addReg(TmpReg); 335 } 336 } 337 } 338 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions. 339 MBB.erase(I); 340 } 341 342 /// findScratchRegister - Find a 'free' PPC register. Try for a call-clobbered 343 /// register first and then a spilled callee-saved register if that fails. 344 static 345 unsigned findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS, 346 const TargetRegisterClass *RC, int SPAdj) { 347 assert(RS && "Register scavenging must be on"); 348 unsigned Reg = RS->FindUnusedReg(RC); 349 // FIXME: move ARM callee-saved reg scan to target independent code, then 350 // search for already spilled CS register here. 351 if (Reg == 0) 352 Reg = RS->scavengeRegister(RC, II, SPAdj); 353 return Reg; 354 } 355 356 /// lowerDynamicAlloc - Generate the code for allocating an object in the 357 /// current frame. The sequence of code with be in the general form 358 /// 359 /// addi R0, SP, \#frameSize ; get the address of the previous frame 360 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size 361 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation 362 /// 363 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II, 364 int SPAdj, RegScavenger *RS) const { 365 // Get the instruction. 366 MachineInstr &MI = *II; 367 // Get the instruction's basic block. 368 MachineBasicBlock &MBB = *MI.getParent(); 369 // Get the basic block's function. 370 MachineFunction &MF = *MBB.getParent(); 371 // Get the frame info. 372 MachineFrameInfo *MFI = MF.getFrameInfo(); 373 // Determine whether 64-bit pointers are used. 374 bool LP64 = Subtarget.isPPC64(); 375 DebugLoc dl = MI.getDebugLoc(); 376 377 // Get the maximum call stack size. 378 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 379 // Get the total frame size. 380 unsigned FrameSize = MFI->getStackSize(); 381 382 // Get stack alignments. 383 unsigned TargetAlign = MF.getTarget().getFrameLowering()->getStackAlignment(); 384 unsigned MaxAlign = MFI->getMaxAlignment(); 385 if (MaxAlign > TargetAlign) 386 report_fatal_error("Dynamic alloca with large aligns not supported"); 387 388 // Determine the previous frame's address. If FrameSize can't be 389 // represented as 16 bits or we need special alignment, then we load the 390 // previous frame's address from 0(SP). Why not do an addis of the hi? 391 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. 392 // Constructing the constant and adding would take 3 instructions. 393 // Fortunately, a frame greater than 32K is rare. 394 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 395 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 396 const TargetRegisterClass *RC = LP64 ? G8RC : GPRC; 397 398 // FIXME (64-bit): Use "findScratchRegister" 399 unsigned Reg; 400 if (requiresRegisterScavenging(MF)) 401 Reg = findScratchRegister(II, RS, RC, SPAdj); 402 else 403 Reg = PPC::R0; 404 405 if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) { 406 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) 407 .addReg(PPC::R31) 408 .addImm(FrameSize); 409 } else if (LP64) { 410 if (requiresRegisterScavenging(MF)) // FIXME (64-bit): Use "true" part. 411 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg) 412 .addImm(0) 413 .addReg(PPC::X1); 414 else 415 BuildMI(MBB, II, dl, TII.get(PPC::LD), PPC::X0) 416 .addImm(0) 417 .addReg(PPC::X1); 418 } else { 419 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) 420 .addImm(0) 421 .addReg(PPC::R1); 422 } 423 424 // Grow the stack and update the stack pointer link, then determine the 425 // address of new allocated space. 426 if (LP64) { 427 if (requiresRegisterScavenging(MF)) // FIXME (64-bit): Use "true" part. 428 BuildMI(MBB, II, dl, TII.get(PPC::STDUX)) 429 .addReg(Reg, RegState::Kill) 430 .addReg(PPC::X1) 431 .addReg(MI.getOperand(1).getReg()); 432 else 433 BuildMI(MBB, II, dl, TII.get(PPC::STDUX)) 434 .addReg(PPC::X0, RegState::Kill) 435 .addReg(PPC::X1) 436 .addReg(MI.getOperand(1).getReg()); 437 438 if (!MI.getOperand(1).isKill()) 439 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 440 .addReg(PPC::X1) 441 .addImm(maxCallFrameSize); 442 else 443 // Implicitly kill the register. 444 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 445 .addReg(PPC::X1) 446 .addImm(maxCallFrameSize) 447 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill); 448 } else { 449 BuildMI(MBB, II, dl, TII.get(PPC::STWUX)) 450 .addReg(Reg, RegState::Kill) 451 .addReg(PPC::R1) 452 .addReg(MI.getOperand(1).getReg()); 453 454 if (!MI.getOperand(1).isKill()) 455 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 456 .addReg(PPC::R1) 457 .addImm(maxCallFrameSize); 458 else 459 // Implicitly kill the register. 460 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 461 .addReg(PPC::R1) 462 .addImm(maxCallFrameSize) 463 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill); 464 } 465 466 // Discard the DYNALLOC instruction. 467 MBB.erase(II); 468 } 469 470 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of 471 /// reserving a whole register (R0), we scrounge for one here. This generates 472 /// code like this: 473 /// 474 /// mfcr rA ; Move the conditional register into GPR rA. 475 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot. 476 /// stw rA, FI ; Store rA to the frame. 477 /// 478 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, 479 unsigned FrameIndex, int SPAdj, 480 RegScavenger *RS) const { 481 // Get the instruction. 482 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>, <FI> 483 // Get the instruction's basic block. 484 MachineBasicBlock &MBB = *MI.getParent(); 485 DebugLoc dl = MI.getDebugLoc(); 486 487 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 488 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 489 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC; 490 unsigned Reg = findScratchRegister(II, RS, RC, SPAdj); 491 unsigned SrcReg = MI.getOperand(0).getReg(); 492 bool LP64 = Subtarget.isPPC64(); 493 494 // We need to store the CR in the low 4-bits of the saved value. First, issue 495 // an MFCRpsued to save all of the CRBits and, if needed, kill the SrcReg. 496 BuildMI(MBB, II, dl, TII.get(PPC::MFCRpseud), Reg) 497 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 498 499 // If the saved register wasn't CR0, shift the bits left so that they are in 500 // CR0's slot. 501 if (SrcReg != PPC::CR0) 502 // rlwinm rA, rA, ShiftBits, 0, 31. 503 BuildMI(MBB, II, dl, TII.get(PPC::RLWINM), Reg) 504 .addReg(Reg, RegState::Kill) 505 .addImm(getPPCRegisterNumbering(SrcReg) * 4) 506 .addImm(0) 507 .addImm(31); 508 509 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW)) 510 .addReg(Reg, getKillRegState(MI.getOperand(1).getImm())), 511 FrameIndex); 512 513 // Discard the pseudo instruction. 514 MBB.erase(II); 515 } 516 517 void 518 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 519 int SPAdj, RegScavenger *RS) const { 520 assert(SPAdj == 0 && "Unexpected"); 521 522 // Get the instruction. 523 MachineInstr &MI = *II; 524 // Get the instruction's basic block. 525 MachineBasicBlock &MBB = *MI.getParent(); 526 // Get the basic block's function. 527 MachineFunction &MF = *MBB.getParent(); 528 // Get the frame info. 529 MachineFrameInfo *MFI = MF.getFrameInfo(); 530 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 531 DebugLoc dl = MI.getDebugLoc(); 532 533 // Find out which operand is the frame index. 534 unsigned FIOperandNo = 0; 535 while (!MI.getOperand(FIOperandNo).isFI()) { 536 ++FIOperandNo; 537 assert(FIOperandNo != MI.getNumOperands() && 538 "Instr doesn't have FrameIndex operand!"); 539 } 540 // Take into account whether it's an add or mem instruction 541 unsigned OffsetOperandNo = (FIOperandNo == 2) ? 1 : 2; 542 if (MI.isInlineAsm()) 543 OffsetOperandNo = FIOperandNo-1; 544 545 // Get the frame index. 546 int FrameIndex = MI.getOperand(FIOperandNo).getIndex(); 547 548 // Get the frame pointer save index. Users of this index are primarily 549 // DYNALLOC instructions. 550 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 551 int FPSI = FI->getFramePointerSaveIndex(); 552 // Get the instruction opcode. 553 unsigned OpC = MI.getOpcode(); 554 555 // Special case for dynamic alloca. 556 if (FPSI && FrameIndex == FPSI && 557 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { 558 lowerDynamicAlloc(II, SPAdj, RS); 559 return; 560 } 561 562 // Special case for pseudo-op SPILL_CR. 563 if (requiresRegisterScavenging(MF)) // FIXME (64-bit): Enable by default. 564 if (OpC == PPC::SPILL_CR) { 565 lowerCRSpilling(II, FrameIndex, SPAdj, RS); 566 return; 567 } 568 569 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 570 MI.getOperand(FIOperandNo).ChangeToRegister(TFI->hasFP(MF) ? 571 PPC::R31 : PPC::R1, 572 false); 573 574 // Figure out if the offset in the instruction is shifted right two bits. This 575 // is true for instructions like "STD", which the machine implicitly adds two 576 // low zeros to. 577 bool isIXAddr = false; 578 switch (OpC) { 579 case PPC::LWA: 580 case PPC::LD: 581 case PPC::STD: 582 case PPC::STD_32: 583 isIXAddr = true; 584 break; 585 } 586 587 // Now add the frame object offset to the offset from r1. 588 int Offset = MFI->getObjectOffset(FrameIndex); 589 if (!isIXAddr) 590 Offset += MI.getOperand(OffsetOperandNo).getImm(); 591 else 592 Offset += MI.getOperand(OffsetOperandNo).getImm() << 2; 593 594 // If we're not using a Frame Pointer that has been set to the value of the 595 // SP before having the stack size subtracted from it, then add the stack size 596 // to Offset to get the correct offset. 597 // Naked functions have stack size 0, although getStackSize may not reflect that 598 // because we didn't call all the pieces that compute it for naked functions. 599 if (!MF.getFunction()->hasFnAttr(Attribute::Naked)) 600 Offset += MFI->getStackSize(); 601 602 // If we can, encode the offset directly into the instruction. If this is a 603 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If 604 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits 605 // clear can be encoded. This is extremely uncommon, because normally you 606 // only "std" to a stack slot that is at least 4-byte aligned, but it can 607 // happen in invalid code. 608 if (isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0)) { 609 if (isIXAddr) 610 Offset >>= 2; // The actual encoded value has the low two bits zero. 611 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 612 return; 613 } 614 615 // The offset doesn't fit into a single register, scavenge one to build the 616 // offset in. 617 // FIXME: figure out what SPAdj is doing here. 618 619 // FIXME (64-bit): Use "findScratchRegister". 620 unsigned SReg; 621 if (requiresRegisterScavenging(MF)) 622 SReg = findScratchRegister(II, RS, &PPC::GPRCRegClass, SPAdj); 623 else 624 SReg = PPC::R0; 625 626 // Insert a set of rA with the full offset value before the ld, st, or add 627 BuildMI(MBB, II, dl, TII.get(PPC::LIS), SReg) 628 .addImm(Offset >> 16); 629 BuildMI(MBB, II, dl, TII.get(PPC::ORI), SReg) 630 .addReg(SReg, RegState::Kill) 631 .addImm(Offset); 632 633 // Convert into indexed form of the instruction: 634 // 635 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 636 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 637 unsigned OperandBase; 638 639 if (OpC != TargetOpcode::INLINEASM) { 640 assert(ImmToIdxMap.count(OpC) && 641 "No indexed form of load or store available!"); 642 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; 643 MI.setDesc(TII.get(NewOpcode)); 644 OperandBase = 1; 645 } else { 646 OperandBase = OffsetOperandNo; 647 } 648 649 unsigned StackReg = MI.getOperand(FIOperandNo).getReg(); 650 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false); 651 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false); 652 } 653 654 unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 655 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 656 657 if (!Subtarget.isPPC64()) 658 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1; 659 else 660 return TFI->hasFP(MF) ? PPC::X31 : PPC::X1; 661 } 662 663 unsigned PPCRegisterInfo::getEHExceptionRegister() const { 664 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3; 665 } 666 667 unsigned PPCRegisterInfo::getEHHandlerRegister() const { 668 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4; 669 } 670