1 //===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the TargetRegisterInfo 11 // class. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "PPCRegisterInfo.h" 16 #include "PPC.h" 17 #include "PPCFrameLowering.h" 18 #include "PPCInstrBuilder.h" 19 #include "PPCMachineFunctionInfo.h" 20 #include "PPCSubtarget.h" 21 #include "PPCTargetMachine.h" 22 #include "llvm/ADT/BitVector.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/CodeGen/MachineFrameInfo.h" 25 #include "llvm/CodeGen/MachineFunction.h" 26 #include "llvm/CodeGen/MachineInstrBuilder.h" 27 #include "llvm/CodeGen/MachineModuleInfo.h" 28 #include "llvm/CodeGen/MachineRegisterInfo.h" 29 #include "llvm/CodeGen/RegisterScavenging.h" 30 #include "llvm/IR/CallingConv.h" 31 #include "llvm/IR/Constants.h" 32 #include "llvm/IR/Function.h" 33 #include "llvm/IR/Type.h" 34 #include "llvm/Support/CommandLine.h" 35 #include "llvm/Support/Debug.h" 36 #include "llvm/Support/ErrorHandling.h" 37 #include "llvm/Support/MathExtras.h" 38 #include "llvm/Support/raw_ostream.h" 39 #include "llvm/Target/TargetFrameLowering.h" 40 #include "llvm/Target/TargetInstrInfo.h" 41 #include "llvm/Target/TargetMachine.h" 42 #include "llvm/Target/TargetOptions.h" 43 #include <cstdlib> 44 45 using namespace llvm; 46 47 #define DEBUG_TYPE "reginfo" 48 49 #define GET_REGINFO_TARGET_DESC 50 #include "PPCGenRegisterInfo.inc" 51 52 static cl::opt<bool> 53 EnableBasePointer("ppc-use-base-pointer", cl::Hidden, cl::init(true), 54 cl::desc("Enable use of a base pointer for complex stack frames")); 55 56 static cl::opt<bool> 57 AlwaysBasePointer("ppc-always-use-base-pointer", cl::Hidden, cl::init(false), 58 cl::desc("Force the use of a base pointer in every function")); 59 60 PPCRegisterInfo::PPCRegisterInfo(const PPCTargetMachine &TM) 61 : PPCGenRegisterInfo(TM.isPPC64() ? PPC::LR8 : PPC::LR, 62 TM.isPPC64() ? 0 : 1, 63 TM.isPPC64() ? 0 : 1), 64 TM(TM) { 65 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 66 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 67 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 68 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 69 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 70 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 71 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 72 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 73 ImmToIdxMap[PPC::LWA_32] = PPC::LWAX_32; 74 75 // 64-bit 76 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8; 77 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8; 78 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8; 79 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX; 80 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; 81 } 82 83 /// getPointerRegClass - Return the register class to use to hold pointers. 84 /// This is used for addressing modes. 85 const TargetRegisterClass * 86 PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) 87 const { 88 // Note that PPCInstrInfo::FoldImmediate also directly uses this Kind value 89 // when it checks for ZERO folding. 90 if (Kind == 1) { 91 if (TM.isPPC64()) 92 return &PPC::G8RC_NOX0RegClass; 93 return &PPC::GPRC_NOR0RegClass; 94 } 95 96 if (TM.isPPC64()) 97 return &PPC::G8RCRegClass; 98 return &PPC::GPRCRegClass; 99 } 100 101 const MCPhysReg* 102 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 103 const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>(); 104 if (MF->getFunction()->getCallingConv() == CallingConv::AnyReg) { 105 if (Subtarget.hasVSX()) 106 return CSR_64_AllRegs_VSX_SaveList; 107 if (Subtarget.hasAltivec()) 108 return CSR_64_AllRegs_Altivec_SaveList; 109 return CSR_64_AllRegs_SaveList; 110 } 111 112 if (Subtarget.isDarwinABI()) 113 return TM.isPPC64() 114 ? (Subtarget.hasAltivec() ? CSR_Darwin64_Altivec_SaveList 115 : CSR_Darwin64_SaveList) 116 : (Subtarget.hasAltivec() ? CSR_Darwin32_Altivec_SaveList 117 : CSR_Darwin32_SaveList); 118 119 // On PPC64, we might need to save r2 (but only if it is not reserved). 120 bool SaveR2 = MF->getRegInfo().isAllocatable(PPC::X2); 121 122 return TM.isPPC64() 123 ? (Subtarget.hasAltivec() 124 ? (SaveR2 ? CSR_SVR464_R2_Altivec_SaveList 125 : CSR_SVR464_Altivec_SaveList) 126 : (SaveR2 ? CSR_SVR464_R2_SaveList : CSR_SVR464_SaveList)) 127 : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_SaveList 128 : CSR_SVR432_SaveList); 129 } 130 131 const uint32_t * 132 PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF, 133 CallingConv::ID CC) const { 134 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 135 if (CC == CallingConv::AnyReg) { 136 if (Subtarget.hasVSX()) 137 return CSR_64_AllRegs_VSX_RegMask; 138 if (Subtarget.hasAltivec()) 139 return CSR_64_AllRegs_Altivec_RegMask; 140 return CSR_64_AllRegs_RegMask; 141 } 142 143 if (Subtarget.isDarwinABI()) 144 return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_Darwin64_Altivec_RegMask 145 : CSR_Darwin64_RegMask) 146 : (Subtarget.hasAltivec() ? CSR_Darwin32_Altivec_RegMask 147 : CSR_Darwin32_RegMask); 148 149 return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR464_Altivec_RegMask 150 : CSR_SVR464_RegMask) 151 : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_RegMask 152 : CSR_SVR432_RegMask); 153 } 154 155 const uint32_t* 156 PPCRegisterInfo::getNoPreservedMask() const { 157 return CSR_NoRegs_RegMask; 158 } 159 160 void PPCRegisterInfo::adjustStackMapLiveOutMask(uint32_t *Mask) const { 161 for (unsigned PseudoReg : {PPC::ZERO, PPC::ZERO8, PPC::RM}) 162 Mask[PseudoReg / 32] &= ~(1u << (PseudoReg % 32)); 163 } 164 165 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 166 BitVector Reserved(getNumRegs()); 167 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 168 const PPCFrameLowering *TFI = getFrameLowering(MF); 169 170 // The ZERO register is not really a register, but the representation of r0 171 // when used in instructions that treat r0 as the constant 0. 172 Reserved.set(PPC::ZERO); 173 Reserved.set(PPC::ZERO8); 174 175 // The FP register is also not really a register, but is the representation 176 // of the frame pointer register used by ISD::FRAMEADDR. 177 Reserved.set(PPC::FP); 178 Reserved.set(PPC::FP8); 179 180 // The BP register is also not really a register, but is the representation 181 // of the base pointer register used by setjmp. 182 Reserved.set(PPC::BP); 183 Reserved.set(PPC::BP8); 184 185 // The counter registers must be reserved so that counter-based loops can 186 // be correctly formed (and the mtctr instructions are not DCE'd). 187 Reserved.set(PPC::CTR); 188 Reserved.set(PPC::CTR8); 189 190 Reserved.set(PPC::R1); 191 Reserved.set(PPC::LR); 192 Reserved.set(PPC::LR8); 193 Reserved.set(PPC::RM); 194 195 if (!Subtarget.isDarwinABI() || !Subtarget.hasAltivec()) 196 Reserved.set(PPC::VRSAVE); 197 198 // The SVR4 ABI reserves r2 and r13 199 if (Subtarget.isSVR4ABI()) { 200 Reserved.set(PPC::R2); // System-reserved register 201 Reserved.set(PPC::R13); // Small Data Area pointer register 202 } 203 204 // On PPC64, r13 is the thread pointer. Never allocate this register. 205 if (TM.isPPC64()) { 206 Reserved.set(PPC::R13); 207 208 Reserved.set(PPC::X1); 209 Reserved.set(PPC::X13); 210 211 if (TFI->needsFP(MF)) 212 Reserved.set(PPC::X31); 213 214 if (hasBasePointer(MF)) 215 Reserved.set(PPC::X30); 216 217 // The 64-bit SVR4 ABI reserves r2 for the TOC pointer. 218 if (Subtarget.isSVR4ABI()) { 219 // We only reserve r2 if we need to use the TOC pointer. If we have no 220 // explicit uses of the TOC pointer (meaning we're a leaf function with 221 // no constant-pool loads, etc.) and we have no potential uses inside an 222 // inline asm block, then we can treat r2 has an ordinary callee-saved 223 // register. 224 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 225 if (FuncInfo->usesTOCBasePtr() || MF.hasInlineAsm()) 226 Reserved.set(PPC::X2); 227 else 228 Reserved.reset(PPC::R2); 229 } 230 } 231 232 if (TFI->needsFP(MF)) 233 Reserved.set(PPC::R31); 234 235 if (hasBasePointer(MF)) { 236 if (Subtarget.isSVR4ABI() && !TM.isPPC64() && 237 TM.getRelocationModel() == Reloc::PIC_) 238 Reserved.set(PPC::R29); 239 else 240 Reserved.set(PPC::R30); 241 } 242 243 if (Subtarget.isSVR4ABI() && !TM.isPPC64() && 244 TM.getRelocationModel() == Reloc::PIC_) 245 Reserved.set(PPC::R30); 246 247 // Reserve Altivec registers when Altivec is unavailable. 248 if (!Subtarget.hasAltivec()) 249 for (TargetRegisterClass::iterator I = PPC::VRRCRegClass.begin(), 250 IE = PPC::VRRCRegClass.end(); I != IE; ++I) 251 Reserved.set(*I); 252 253 return Reserved; 254 } 255 256 unsigned PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 257 MachineFunction &MF) const { 258 const PPCFrameLowering *TFI = getFrameLowering(MF); 259 const unsigned DefaultSafety = 1; 260 261 switch (RC->getID()) { 262 default: 263 return 0; 264 case PPC::G8RC_NOX0RegClassID: 265 case PPC::GPRC_NOR0RegClassID: 266 case PPC::G8RCRegClassID: 267 case PPC::GPRCRegClassID: { 268 unsigned FP = TFI->hasFP(MF) ? 1 : 0; 269 return 32 - FP - DefaultSafety; 270 } 271 case PPC::F8RCRegClassID: 272 case PPC::F4RCRegClassID: 273 case PPC::QFRCRegClassID: 274 case PPC::QSRCRegClassID: 275 case PPC::QBRCRegClassID: 276 case PPC::VRRCRegClassID: 277 case PPC::VFRCRegClassID: 278 case PPC::VSLRCRegClassID: 279 case PPC::VSHRCRegClassID: 280 return 32 - DefaultSafety; 281 case PPC::VSRCRegClassID: 282 case PPC::VSFRCRegClassID: 283 case PPC::VSSRCRegClassID: 284 return 64 - DefaultSafety; 285 case PPC::CRRCRegClassID: 286 return 8 - DefaultSafety; 287 } 288 } 289 290 const TargetRegisterClass * 291 PPCRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC, 292 const MachineFunction &MF) const { 293 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 294 if (Subtarget.hasVSX()) { 295 // With VSX, we can inflate various sub-register classes to the full VSX 296 // register set. 297 298 if (RC == &PPC::F8RCRegClass) 299 return &PPC::VSFRCRegClass; 300 else if (RC == &PPC::VRRCRegClass) 301 return &PPC::VSRCRegClass; 302 else if (RC == &PPC::F4RCRegClass && Subtarget.hasP8Vector()) 303 return &PPC::VSSRCRegClass; 304 } 305 306 return TargetRegisterInfo::getLargestLegalSuperClass(RC, MF); 307 } 308 309 //===----------------------------------------------------------------------===// 310 // Stack Frame Processing methods 311 //===----------------------------------------------------------------------===// 312 313 /// lowerDynamicAlloc - Generate the code for allocating an object in the 314 /// current frame. The sequence of code with be in the general form 315 /// 316 /// addi R0, SP, \#frameSize ; get the address of the previous frame 317 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size 318 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation 319 /// 320 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const { 321 // Get the instruction. 322 MachineInstr &MI = *II; 323 // Get the instruction's basic block. 324 MachineBasicBlock &MBB = *MI.getParent(); 325 // Get the basic block's function. 326 MachineFunction &MF = *MBB.getParent(); 327 // Get the frame info. 328 MachineFrameInfo *MFI = MF.getFrameInfo(); 329 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 330 // Get the instruction info. 331 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 332 // Determine whether 64-bit pointers are used. 333 bool LP64 = TM.isPPC64(); 334 DebugLoc dl = MI.getDebugLoc(); 335 336 // Get the maximum call stack size. 337 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 338 // Get the total frame size. 339 unsigned FrameSize = MFI->getStackSize(); 340 341 // Get stack alignments. 342 const PPCFrameLowering *TFI = getFrameLowering(MF); 343 unsigned TargetAlign = TFI->getStackAlignment(); 344 unsigned MaxAlign = MFI->getMaxAlignment(); 345 assert((maxCallFrameSize & (MaxAlign-1)) == 0 && 346 "Maximum call-frame size not sufficiently aligned"); 347 348 // Determine the previous frame's address. If FrameSize can't be 349 // represented as 16 bits or we need special alignment, then we load the 350 // previous frame's address from 0(SP). Why not do an addis of the hi? 351 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. 352 // Constructing the constant and adding would take 3 instructions. 353 // Fortunately, a frame greater than 32K is rare. 354 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 355 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 356 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 357 358 if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) { 359 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) 360 .addReg(PPC::R31) 361 .addImm(FrameSize); 362 } else if (LP64) { 363 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg) 364 .addImm(0) 365 .addReg(PPC::X1); 366 } else { 367 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) 368 .addImm(0) 369 .addReg(PPC::R1); 370 } 371 372 bool KillNegSizeReg = MI.getOperand(1).isKill(); 373 unsigned NegSizeReg = MI.getOperand(1).getReg(); 374 375 // Grow the stack and update the stack pointer link, then determine the 376 // address of new allocated space. 377 if (LP64) { 378 if (MaxAlign > TargetAlign) { 379 unsigned UnalNegSizeReg = NegSizeReg; 380 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC); 381 382 // Unfortunately, there is no andi, only andi., and we can't insert that 383 // here because we might clobber cr0 while it is live. 384 BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg) 385 .addImm(~(MaxAlign-1)); 386 387 unsigned NegSizeReg1 = NegSizeReg; 388 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC); 389 BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg) 390 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg)) 391 .addReg(NegSizeReg1, RegState::Kill); 392 KillNegSizeReg = true; 393 } 394 395 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1) 396 .addReg(Reg, RegState::Kill) 397 .addReg(PPC::X1) 398 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg)); 399 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 400 .addReg(PPC::X1) 401 .addImm(maxCallFrameSize); 402 } else { 403 if (MaxAlign > TargetAlign) { 404 unsigned UnalNegSizeReg = NegSizeReg; 405 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); 406 407 // Unfortunately, there is no andi, only andi., and we can't insert that 408 // here because we might clobber cr0 while it is live. 409 BuildMI(MBB, II, dl, TII.get(PPC::LI), NegSizeReg) 410 .addImm(~(MaxAlign-1)); 411 412 unsigned NegSizeReg1 = NegSizeReg; 413 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); 414 BuildMI(MBB, II, dl, TII.get(PPC::AND), NegSizeReg) 415 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg)) 416 .addReg(NegSizeReg1, RegState::Kill); 417 KillNegSizeReg = true; 418 } 419 420 BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1) 421 .addReg(Reg, RegState::Kill) 422 .addReg(PPC::R1) 423 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg)); 424 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 425 .addReg(PPC::R1) 426 .addImm(maxCallFrameSize); 427 } 428 429 // Discard the DYNALLOC instruction. 430 MBB.erase(II); 431 } 432 433 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of 434 /// reserving a whole register (R0), we scrounge for one here. This generates 435 /// code like this: 436 /// 437 /// mfcr rA ; Move the conditional register into GPR rA. 438 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot. 439 /// stw rA, FI ; Store rA to the frame. 440 /// 441 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, 442 unsigned FrameIndex) const { 443 // Get the instruction. 444 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset> 445 // Get the instruction's basic block. 446 MachineBasicBlock &MBB = *MI.getParent(); 447 MachineFunction &MF = *MBB.getParent(); 448 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 449 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 450 DebugLoc dl = MI.getDebugLoc(); 451 452 bool LP64 = TM.isPPC64(); 453 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 454 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 455 456 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 457 unsigned SrcReg = MI.getOperand(0).getReg(); 458 459 // We need to store the CR in the low 4-bits of the saved value. First, issue 460 // an MFOCRF to save all of the CRBits and, if needed, kill the SrcReg. 461 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg) 462 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 463 464 // If the saved register wasn't CR0, shift the bits left so that they are in 465 // CR0's slot. 466 if (SrcReg != PPC::CR0) { 467 unsigned Reg1 = Reg; 468 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 469 470 // rlwinm rA, rA, ShiftBits, 0, 31. 471 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 472 .addReg(Reg1, RegState::Kill) 473 .addImm(getEncodingValue(SrcReg) * 4) 474 .addImm(0) 475 .addImm(31); 476 } 477 478 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW)) 479 .addReg(Reg, RegState::Kill), 480 FrameIndex); 481 482 // Discard the pseudo instruction. 483 MBB.erase(II); 484 } 485 486 void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II, 487 unsigned FrameIndex) const { 488 // Get the instruction. 489 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset> 490 // Get the instruction's basic block. 491 MachineBasicBlock &MBB = *MI.getParent(); 492 MachineFunction &MF = *MBB.getParent(); 493 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 494 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 495 DebugLoc dl = MI.getDebugLoc(); 496 497 bool LP64 = TM.isPPC64(); 498 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 499 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 500 501 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 502 unsigned DestReg = MI.getOperand(0).getReg(); 503 assert(MI.definesRegister(DestReg) && 504 "RESTORE_CR does not define its destination"); 505 506 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), 507 Reg), FrameIndex); 508 509 // If the reloaded register isn't CR0, shift the bits right so that they are 510 // in the right CR's slot. 511 if (DestReg != PPC::CR0) { 512 unsigned Reg1 = Reg; 513 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 514 515 unsigned ShiftBits = getEncodingValue(DestReg)*4; 516 // rlwinm r11, r11, 32-ShiftBits, 0, 31. 517 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 518 .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0) 519 .addImm(31); 520 } 521 522 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), DestReg) 523 .addReg(Reg, RegState::Kill); 524 525 // Discard the pseudo instruction. 526 MBB.erase(II); 527 } 528 529 void PPCRegisterInfo::lowerCRBitSpilling(MachineBasicBlock::iterator II, 530 unsigned FrameIndex) const { 531 // Get the instruction. 532 MachineInstr &MI = *II; // ; SPILL_CRBIT <SrcReg>, <offset> 533 // Get the instruction's basic block. 534 MachineBasicBlock &MBB = *MI.getParent(); 535 MachineFunction &MF = *MBB.getParent(); 536 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 537 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 538 DebugLoc dl = MI.getDebugLoc(); 539 540 bool LP64 = TM.isPPC64(); 541 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 542 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 543 544 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 545 unsigned SrcReg = MI.getOperand(0).getReg(); 546 547 BuildMI(MBB, II, dl, TII.get(TargetOpcode::KILL), 548 getCRFromCRBit(SrcReg)) 549 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 550 551 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg) 552 .addReg(getCRFromCRBit(SrcReg)); 553 554 // If the saved register wasn't CR0LT, shift the bits left so that the bit to 555 // store is the first one. Mask all but that bit. 556 unsigned Reg1 = Reg; 557 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 558 559 // rlwinm rA, rA, ShiftBits, 0, 0. 560 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 561 .addReg(Reg1, RegState::Kill) 562 .addImm(getEncodingValue(SrcReg)) 563 .addImm(0).addImm(0); 564 565 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW)) 566 .addReg(Reg, RegState::Kill), 567 FrameIndex); 568 569 // Discard the pseudo instruction. 570 MBB.erase(II); 571 } 572 573 void PPCRegisterInfo::lowerCRBitRestore(MachineBasicBlock::iterator II, 574 unsigned FrameIndex) const { 575 // Get the instruction. 576 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CRBIT <offset> 577 // Get the instruction's basic block. 578 MachineBasicBlock &MBB = *MI.getParent(); 579 MachineFunction &MF = *MBB.getParent(); 580 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 581 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 582 DebugLoc dl = MI.getDebugLoc(); 583 584 bool LP64 = TM.isPPC64(); 585 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 586 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 587 588 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 589 unsigned DestReg = MI.getOperand(0).getReg(); 590 assert(MI.definesRegister(DestReg) && 591 "RESTORE_CRBIT does not define its destination"); 592 593 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), 594 Reg), FrameIndex); 595 596 BuildMI(MBB, II, dl, TII.get(TargetOpcode::IMPLICIT_DEF), DestReg); 597 598 unsigned RegO = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 599 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), RegO) 600 .addReg(getCRFromCRBit(DestReg)); 601 602 unsigned ShiftBits = getEncodingValue(DestReg); 603 // rlwimi r11, r10, 32-ShiftBits, ..., ... 604 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWIMI8 : PPC::RLWIMI), RegO) 605 .addReg(RegO, RegState::Kill) 606 .addReg(Reg, RegState::Kill) 607 .addImm(ShiftBits ? 32 - ShiftBits : 0) 608 .addImm(ShiftBits) 609 .addImm(ShiftBits); 610 611 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), 612 getCRFromCRBit(DestReg)) 613 .addReg(RegO, RegState::Kill) 614 // Make sure we have a use dependency all the way through this 615 // sequence of instructions. We can't have the other bits in the CR 616 // modified in between the mfocrf and the mtocrf. 617 .addReg(getCRFromCRBit(DestReg), RegState::Implicit); 618 619 // Discard the pseudo instruction. 620 MBB.erase(II); 621 } 622 623 void PPCRegisterInfo::lowerVRSAVESpilling(MachineBasicBlock::iterator II, 624 unsigned FrameIndex) const { 625 // Get the instruction. 626 MachineInstr &MI = *II; // ; SPILL_VRSAVE <SrcReg>, <offset> 627 // Get the instruction's basic block. 628 MachineBasicBlock &MBB = *MI.getParent(); 629 MachineFunction &MF = *MBB.getParent(); 630 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 631 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 632 DebugLoc dl = MI.getDebugLoc(); 633 634 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 635 unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC); 636 unsigned SrcReg = MI.getOperand(0).getReg(); 637 638 BuildMI(MBB, II, dl, TII.get(PPC::MFVRSAVEv), Reg) 639 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 640 641 addFrameReference( 642 BuildMI(MBB, II, dl, TII.get(PPC::STW)).addReg(Reg, RegState::Kill), 643 FrameIndex); 644 645 // Discard the pseudo instruction. 646 MBB.erase(II); 647 } 648 649 void PPCRegisterInfo::lowerVRSAVERestore(MachineBasicBlock::iterator II, 650 unsigned FrameIndex) const { 651 // Get the instruction. 652 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_VRSAVE <offset> 653 // Get the instruction's basic block. 654 MachineBasicBlock &MBB = *MI.getParent(); 655 MachineFunction &MF = *MBB.getParent(); 656 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 657 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 658 DebugLoc dl = MI.getDebugLoc(); 659 660 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 661 unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC); 662 unsigned DestReg = MI.getOperand(0).getReg(); 663 assert(MI.definesRegister(DestReg) && 664 "RESTORE_VRSAVE does not define its destination"); 665 666 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::LWZ), 667 Reg), FrameIndex); 668 669 BuildMI(MBB, II, dl, TII.get(PPC::MTVRSAVEv), DestReg) 670 .addReg(Reg, RegState::Kill); 671 672 // Discard the pseudo instruction. 673 MBB.erase(II); 674 } 675 676 bool 677 PPCRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF, 678 unsigned Reg, int &FrameIdx) const { 679 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 680 // For the nonvolatile condition registers (CR2, CR3, CR4) in an SVR4 681 // ABI, return true to prevent allocating an additional frame slot. 682 // For 64-bit, the CR save area is at SP+8; the value of FrameIdx = 0 683 // is arbitrary and will be subsequently ignored. For 32-bit, we have 684 // previously created the stack slot if needed, so return its FrameIdx. 685 if (Subtarget.isSVR4ABI() && PPC::CR2 <= Reg && Reg <= PPC::CR4) { 686 if (TM.isPPC64()) 687 FrameIdx = 0; 688 else { 689 const PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 690 FrameIdx = FI->getCRSpillFrameIndex(); 691 } 692 return true; 693 } 694 return false; 695 } 696 697 // Figure out if the offset in the instruction must be a multiple of 4. 698 // This is true for instructions like "STD". 699 static bool usesIXAddr(const MachineInstr &MI) { 700 unsigned OpC = MI.getOpcode(); 701 702 switch (OpC) { 703 default: 704 return false; 705 case PPC::LWA: 706 case PPC::LWA_32: 707 case PPC::LD: 708 case PPC::STD: 709 return true; 710 } 711 } 712 713 // Return the OffsetOperandNo given the FIOperandNum (and the instruction). 714 static unsigned getOffsetONFromFION(const MachineInstr &MI, 715 unsigned FIOperandNum) { 716 // Take into account whether it's an add or mem instruction 717 unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2; 718 if (MI.isInlineAsm()) 719 OffsetOperandNo = FIOperandNum - 1; 720 else if (MI.getOpcode() == TargetOpcode::STACKMAP || 721 MI.getOpcode() == TargetOpcode::PATCHPOINT) 722 OffsetOperandNo = FIOperandNum + 1; 723 724 return OffsetOperandNo; 725 } 726 727 void 728 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 729 int SPAdj, unsigned FIOperandNum, 730 RegScavenger *RS) const { 731 assert(SPAdj == 0 && "Unexpected"); 732 733 // Get the instruction. 734 MachineInstr &MI = *II; 735 // Get the instruction's basic block. 736 MachineBasicBlock &MBB = *MI.getParent(); 737 // Get the basic block's function. 738 MachineFunction &MF = *MBB.getParent(); 739 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 740 // Get the instruction info. 741 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 742 // Get the frame info. 743 MachineFrameInfo *MFI = MF.getFrameInfo(); 744 DebugLoc dl = MI.getDebugLoc(); 745 746 unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum); 747 748 // Get the frame index. 749 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 750 751 // Get the frame pointer save index. Users of this index are primarily 752 // DYNALLOC instructions. 753 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 754 int FPSI = FI->getFramePointerSaveIndex(); 755 // Get the instruction opcode. 756 unsigned OpC = MI.getOpcode(); 757 758 // Special case for dynamic alloca. 759 if (FPSI && FrameIndex == FPSI && 760 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { 761 lowerDynamicAlloc(II); 762 return; 763 } 764 765 // Special case for pseudo-ops SPILL_CR and RESTORE_CR, etc. 766 if (OpC == PPC::SPILL_CR) { 767 lowerCRSpilling(II, FrameIndex); 768 return; 769 } else if (OpC == PPC::RESTORE_CR) { 770 lowerCRRestore(II, FrameIndex); 771 return; 772 } else if (OpC == PPC::SPILL_CRBIT) { 773 lowerCRBitSpilling(II, FrameIndex); 774 return; 775 } else if (OpC == PPC::RESTORE_CRBIT) { 776 lowerCRBitRestore(II, FrameIndex); 777 return; 778 } else if (OpC == PPC::SPILL_VRSAVE) { 779 lowerVRSAVESpilling(II, FrameIndex); 780 return; 781 } else if (OpC == PPC::RESTORE_VRSAVE) { 782 lowerVRSAVERestore(II, FrameIndex); 783 return; 784 } 785 786 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 787 MI.getOperand(FIOperandNum).ChangeToRegister( 788 FrameIndex < 0 ? getBaseRegister(MF) : getFrameRegister(MF), false); 789 790 // Figure out if the offset in the instruction is shifted right two bits. 791 bool isIXAddr = usesIXAddr(MI); 792 793 // If the instruction is not present in ImmToIdxMap, then it has no immediate 794 // form (and must be r+r). 795 bool noImmForm = !MI.isInlineAsm() && OpC != TargetOpcode::STACKMAP && 796 OpC != TargetOpcode::PATCHPOINT && !ImmToIdxMap.count(OpC); 797 798 // Now add the frame object offset to the offset from r1. 799 int Offset = MFI->getObjectOffset(FrameIndex); 800 Offset += MI.getOperand(OffsetOperandNo).getImm(); 801 802 // If we're not using a Frame Pointer that has been set to the value of the 803 // SP before having the stack size subtracted from it, then add the stack size 804 // to Offset to get the correct offset. 805 // Naked functions have stack size 0, although getStackSize may not reflect 806 // that because we didn't call all the pieces that compute it for naked 807 // functions. 808 if (!MF.getFunction()->hasFnAttribute(Attribute::Naked)) { 809 if (!(hasBasePointer(MF) && FrameIndex < 0)) 810 Offset += MFI->getStackSize(); 811 } 812 813 // If we can, encode the offset directly into the instruction. If this is a 814 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If 815 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits 816 // clear can be encoded. This is extremely uncommon, because normally you 817 // only "std" to a stack slot that is at least 4-byte aligned, but it can 818 // happen in invalid code. 819 assert(OpC != PPC::DBG_VALUE && 820 "This should be handled in a target-independent way"); 821 if (!noImmForm && ((isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0)) || 822 OpC == TargetOpcode::STACKMAP || 823 OpC == TargetOpcode::PATCHPOINT)) { 824 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 825 return; 826 } 827 828 // The offset doesn't fit into a single register, scavenge one to build the 829 // offset in. 830 831 bool is64Bit = TM.isPPC64(); 832 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 833 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 834 const TargetRegisterClass *RC = is64Bit ? G8RC : GPRC; 835 unsigned SRegHi = MF.getRegInfo().createVirtualRegister(RC), 836 SReg = MF.getRegInfo().createVirtualRegister(RC); 837 838 // Insert a set of rA with the full offset value before the ld, st, or add 839 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SRegHi) 840 .addImm(Offset >> 16); 841 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg) 842 .addReg(SRegHi, RegState::Kill) 843 .addImm(Offset); 844 845 // Convert into indexed form of the instruction: 846 // 847 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 848 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 849 unsigned OperandBase; 850 851 if (noImmForm) 852 OperandBase = 1; 853 else if (OpC != TargetOpcode::INLINEASM) { 854 assert(ImmToIdxMap.count(OpC) && 855 "No indexed form of load or store available!"); 856 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; 857 MI.setDesc(TII.get(NewOpcode)); 858 OperandBase = 1; 859 } else { 860 OperandBase = OffsetOperandNo; 861 } 862 863 unsigned StackReg = MI.getOperand(FIOperandNum).getReg(); 864 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false); 865 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true); 866 } 867 868 unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 869 const PPCFrameLowering *TFI = getFrameLowering(MF); 870 871 if (!TM.isPPC64()) 872 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1; 873 else 874 return TFI->hasFP(MF) ? PPC::X31 : PPC::X1; 875 } 876 877 unsigned PPCRegisterInfo::getBaseRegister(const MachineFunction &MF) const { 878 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 879 if (!hasBasePointer(MF)) 880 return getFrameRegister(MF); 881 882 if (TM.isPPC64()) 883 return PPC::X30; 884 885 if (Subtarget.isSVR4ABI() && 886 TM.getRelocationModel() == Reloc::PIC_) 887 return PPC::R29; 888 889 return PPC::R30; 890 } 891 892 bool PPCRegisterInfo::hasBasePointer(const MachineFunction &MF) const { 893 if (!EnableBasePointer) 894 return false; 895 if (AlwaysBasePointer) 896 return true; 897 898 // If we need to realign the stack, then the stack pointer can no longer 899 // serve as an offset into the caller's stack space. As a result, we need a 900 // base pointer. 901 return needsStackRealignment(MF); 902 } 903 904 /// Returns true if the instruction's frame index 905 /// reference would be better served by a base register other than FP 906 /// or SP. Used by LocalStackFrameAllocation to determine which frame index 907 /// references it should create new base registers for. 908 bool PPCRegisterInfo:: 909 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { 910 assert(Offset < 0 && "Local offset must be negative"); 911 912 // It's the load/store FI references that cause issues, as it can be difficult 913 // to materialize the offset if it won't fit in the literal field. Estimate 914 // based on the size of the local frame and some conservative assumptions 915 // about the rest of the stack frame (note, this is pre-regalloc, so 916 // we don't know everything for certain yet) whether this offset is likely 917 // to be out of range of the immediate. Return true if so. 918 919 // We only generate virtual base registers for loads and stores that have 920 // an r+i form. Return false for everything else. 921 unsigned OpC = MI->getOpcode(); 922 if (!ImmToIdxMap.count(OpC)) 923 return false; 924 925 // Don't generate a new virtual base register just to add zero to it. 926 if ((OpC == PPC::ADDI || OpC == PPC::ADDI8) && 927 MI->getOperand(2).getImm() == 0) 928 return false; 929 930 MachineBasicBlock &MBB = *MI->getParent(); 931 MachineFunction &MF = *MBB.getParent(); 932 const PPCFrameLowering *TFI = getFrameLowering(MF); 933 unsigned StackEst = TFI->determineFrameLayout(MF, false, true); 934 935 // If we likely don't need a stack frame, then we probably don't need a 936 // virtual base register either. 937 if (!StackEst) 938 return false; 939 940 // Estimate an offset from the stack pointer. 941 // The incoming offset is relating to the SP at the start of the function, 942 // but when we access the local it'll be relative to the SP after local 943 // allocation, so adjust our SP-relative offset by that allocation size. 944 Offset += StackEst; 945 946 // The frame pointer will point to the end of the stack, so estimate the 947 // offset as the difference between the object offset and the FP location. 948 return !isFrameOffsetLegal(MI, getBaseRegister(MF), Offset); 949 } 950 951 /// Insert defining instruction(s) for BaseReg to 952 /// be a pointer to FrameIdx at the beginning of the basic block. 953 void PPCRegisterInfo:: 954 materializeFrameBaseRegister(MachineBasicBlock *MBB, 955 unsigned BaseReg, int FrameIdx, 956 int64_t Offset) const { 957 unsigned ADDriOpc = TM.isPPC64() ? PPC::ADDI8 : PPC::ADDI; 958 959 MachineBasicBlock::iterator Ins = MBB->begin(); 960 DebugLoc DL; // Defaults to "unknown" 961 if (Ins != MBB->end()) 962 DL = Ins->getDebugLoc(); 963 964 const MachineFunction &MF = *MBB->getParent(); 965 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 966 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 967 const MCInstrDesc &MCID = TII.get(ADDriOpc); 968 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 969 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); 970 971 BuildMI(*MBB, Ins, DL, MCID, BaseReg) 972 .addFrameIndex(FrameIdx).addImm(Offset); 973 } 974 975 void PPCRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, 976 int64_t Offset) const { 977 unsigned FIOperandNum = 0; 978 while (!MI.getOperand(FIOperandNum).isFI()) { 979 ++FIOperandNum; 980 assert(FIOperandNum < MI.getNumOperands() && 981 "Instr doesn't have FrameIndex operand!"); 982 } 983 984 MI.getOperand(FIOperandNum).ChangeToRegister(BaseReg, false); 985 unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum); 986 Offset += MI.getOperand(OffsetOperandNo).getImm(); 987 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 988 989 MachineBasicBlock &MBB = *MI.getParent(); 990 MachineFunction &MF = *MBB.getParent(); 991 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 992 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 993 const MCInstrDesc &MCID = MI.getDesc(); 994 MachineRegisterInfo &MRI = MF.getRegInfo(); 995 MRI.constrainRegClass(BaseReg, 996 TII.getRegClass(MCID, FIOperandNum, this, MF)); 997 } 998 999 bool PPCRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, 1000 unsigned BaseReg, 1001 int64_t Offset) const { 1002 unsigned FIOperandNum = 0; 1003 while (!MI->getOperand(FIOperandNum).isFI()) { 1004 ++FIOperandNum; 1005 assert(FIOperandNum < MI->getNumOperands() && 1006 "Instr doesn't have FrameIndex operand!"); 1007 } 1008 1009 unsigned OffsetOperandNo = getOffsetONFromFION(*MI, FIOperandNum); 1010 Offset += MI->getOperand(OffsetOperandNo).getImm(); 1011 1012 return MI->getOpcode() == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm 1013 MI->getOpcode() == TargetOpcode::STACKMAP || 1014 MI->getOpcode() == TargetOpcode::PATCHPOINT || 1015 (isInt<16>(Offset) && (!usesIXAddr(*MI) || (Offset & 3) == 0)); 1016 } 1017