1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file was developed by the LLVM research group and is distributed under 6 // the University of Illinois Open Source License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the MRegisterInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #define DEBUG_TYPE "reginfo" 15 #include "PPC.h" 16 #include "PPCInstrBuilder.h" 17 #include "PPCMachineFunctionInfo.h" 18 #include "PPCRegisterInfo.h" 19 #include "PPCFrameInfo.h" 20 #include "PPCSubtarget.h" 21 #include "llvm/Constants.h" 22 #include "llvm/Type.h" 23 #include "llvm/CodeGen/ValueTypes.h" 24 #include "llvm/CodeGen/MachineInstrBuilder.h" 25 #include "llvm/CodeGen/MachineDebugInfo.h" 26 #include "llvm/CodeGen/MachineFunction.h" 27 #include "llvm/CodeGen/MachineFrameInfo.h" 28 #include "llvm/CodeGen/MachineLocation.h" 29 #include "llvm/CodeGen/SelectionDAGNodes.h" 30 #include "llvm/Target/TargetFrameInfo.h" 31 #include "llvm/Target/TargetInstrInfo.h" 32 #include "llvm/Target/TargetMachine.h" 33 #include "llvm/Target/TargetOptions.h" 34 #include "llvm/Support/CommandLine.h" 35 #include "llvm/Support/Debug.h" 36 #include "llvm/Support/MathExtras.h" 37 #include "llvm/ADT/STLExtras.h" 38 #include <cstdlib> 39 #include <iostream> 40 using namespace llvm; 41 42 /// getRegisterNumbering - Given the enum value for some register, e.g. 43 /// PPC::F14, return the number that it corresponds to (e.g. 14). 44 unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) { 45 using namespace PPC; 46 switch (RegEnum) { 47 case R0 : case X0 : case F0 : case V0 : case CR0: return 0; 48 case R1 : case X1 : case F1 : case V1 : case CR1: return 1; 49 case R2 : case X2 : case F2 : case V2 : case CR2: return 2; 50 case R3 : case X3 : case F3 : case V3 : case CR3: return 3; 51 case R4 : case X4 : case F4 : case V4 : case CR4: return 4; 52 case R5 : case X5 : case F5 : case V5 : case CR5: return 5; 53 case R6 : case X6 : case F6 : case V6 : case CR6: return 6; 54 case R7 : case X7 : case F7 : case V7 : case CR7: return 7; 55 case R8 : case X8 : case F8 : case V8 : return 8; 56 case R9 : case X9 : case F9 : case V9 : return 9; 57 case R10: case X10: case F10: case V10: return 10; 58 case R11: case X11: case F11: case V11: return 11; 59 case R12: case X12: case F12: case V12: return 12; 60 case R13: case X13: case F13: case V13: return 13; 61 case R14: case X14: case F14: case V14: return 14; 62 case R15: case X15: case F15: case V15: return 15; 63 case R16: case X16: case F16: case V16: return 16; 64 case R17: case X17: case F17: case V17: return 17; 65 case R18: case X18: case F18: case V18: return 18; 66 case R19: case X19: case F19: case V19: return 19; 67 case R20: case X20: case F20: case V20: return 20; 68 case R21: case X21: case F21: case V21: return 21; 69 case R22: case X22: case F22: case V22: return 22; 70 case R23: case X23: case F23: case V23: return 23; 71 case R24: case X24: case F24: case V24: return 24; 72 case R25: case X25: case F25: case V25: return 25; 73 case R26: case X26: case F26: case V26: return 26; 74 case R27: case X27: case F27: case V27: return 27; 75 case R28: case X28: case F28: case V28: return 28; 76 case R29: case X29: case F29: case V29: return 29; 77 case R30: case X30: case F30: case V30: return 30; 78 case R31: case X31: case F31: case V31: return 31; 79 default: 80 std::cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n"; 81 abort(); 82 } 83 } 84 85 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST, 86 const TargetInstrInfo &tii) 87 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP), 88 Subtarget(ST), TII(tii) { 89 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 90 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 91 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 92 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 93 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 94 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 95 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 96 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 97 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; 98 } 99 100 void 101 PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 102 MachineBasicBlock::iterator MI, 103 unsigned SrcReg, int FrameIdx, 104 const TargetRegisterClass *RC) const { 105 if (RC == PPC::GPRCRegisterClass) { 106 if (SrcReg != PPC::LR) { 107 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW)).addReg(SrcReg), 108 FrameIdx); 109 } else { 110 // FIXME: this spills LR immediately to memory in one step. To do this, 111 // we use R11, which we know cannot be used in the prolog/epilog. This is 112 // a hack. 113 BuildMI(MBB, MI, TII.get(PPC::MFLR), PPC::R11); 114 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW)).addReg(PPC::R11), 115 FrameIdx); 116 } 117 } else if (RC == PPC::G8RCRegisterClass) { 118 if (SrcReg != PPC::LR8) { 119 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STD)).addReg(SrcReg), 120 FrameIdx); 121 } else { 122 // FIXME: this spills LR immediately to memory in one step. To do this, 123 // we use R11, which we know cannot be used in the prolog/epilog. This is 124 // a hack. 125 BuildMI(MBB, MI, TII.get(PPC::MFLR8), PPC::X11); 126 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STD)).addReg(PPC::X11), 127 FrameIdx); 128 } 129 } else if (RC == PPC::F8RCRegisterClass) { 130 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STFD)).addReg(SrcReg), 131 FrameIdx); 132 } else if (RC == PPC::F4RCRegisterClass) { 133 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STFS)).addReg(SrcReg), 134 FrameIdx); 135 } else if (RC == PPC::CRRCRegisterClass) { 136 // FIXME: We use R0 here, because it isn't available for RA. 137 // We need to store the CR in the low 4-bits of the saved value. First, 138 // issue a MFCR to save all of the CRBits. 139 BuildMI(MBB, MI, TII.get(PPC::MFCR), PPC::R0); 140 141 // If the saved register wasn't CR0, shift the bits left so that they are in 142 // CR0's slot. 143 if (SrcReg != PPC::CR0) { 144 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4; 145 // rlwinm r0, r0, ShiftBits, 0, 31. 146 BuildMI(MBB, MI, TII.get(PPC::RLWINM), PPC::R0) 147 .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31); 148 } 149 150 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW)).addReg(PPC::R0), 151 FrameIdx); 152 } else if (RC == PPC::VRRCRegisterClass) { 153 // We don't have indexed addressing for vector loads. Emit: 154 // R11 = ADDI FI# 155 // Dest = LVX R0, R11 156 // 157 // FIXME: We use R0 here, because it isn't available for RA. 158 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::ADDI), PPC::R0), 159 FrameIdx, 0, 0); 160 BuildMI(MBB, MI, TII.get(PPC::STVX)) 161 .addReg(SrcReg).addReg(PPC::R0).addReg(PPC::R0); 162 } else { 163 assert(0 && "Unknown regclass!"); 164 abort(); 165 } 166 } 167 168 void 169 PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 170 MachineBasicBlock::iterator MI, 171 unsigned DestReg, int FrameIdx, 172 const TargetRegisterClass *RC) const { 173 if (RC == PPC::GPRCRegisterClass) { 174 if (DestReg != PPC::LR) { 175 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LWZ), DestReg), FrameIdx); 176 } else { 177 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LWZ), PPC::R11),FrameIdx); 178 BuildMI(MBB, MI, TII.get(PPC::MTLR)).addReg(PPC::R11); 179 } 180 } else if (RC == PPC::G8RCRegisterClass) { 181 if (DestReg != PPC::LR8) { 182 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LD), DestReg), FrameIdx); 183 } else { 184 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LD), PPC::R11), FrameIdx); 185 BuildMI(MBB, MI, TII.get(PPC::MTLR8)).addReg(PPC::R11); 186 } 187 } else if (RC == PPC::F8RCRegisterClass) { 188 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LFD), DestReg), FrameIdx); 189 } else if (RC == PPC::F4RCRegisterClass) { 190 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LFS), DestReg), FrameIdx); 191 } else if (RC == PPC::CRRCRegisterClass) { 192 // FIXME: We use R0 here, because it isn't available for RA. 193 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LWZ), PPC::R0), FrameIdx); 194 195 // If the reloaded register isn't CR0, shift the bits right so that they are 196 // in the right CR's slot. 197 if (DestReg != PPC::CR0) { 198 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4; 199 // rlwinm r11, r11, 32-ShiftBits, 0, 31. 200 BuildMI(MBB, MI, TII.get(PPC::RLWINM), PPC::R0) 201 .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31); 202 } 203 204 BuildMI(MBB, MI, TII.get(PPC::MTCRF), DestReg).addReg(PPC::R0); 205 } else if (RC == PPC::VRRCRegisterClass) { 206 // We don't have indexed addressing for vector loads. Emit: 207 // R11 = ADDI FI# 208 // Dest = LVX R0, R11 209 // 210 // FIXME: We use R0 here, because it isn't available for RA. 211 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::ADDI), PPC::R0), 212 FrameIdx, 0, 0); 213 BuildMI(MBB, MI, TII.get(PPC::LVX),DestReg).addReg(PPC::R0).addReg(PPC::R0); 214 } else { 215 assert(0 && "Unknown regclass!"); 216 abort(); 217 } 218 } 219 220 void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, 221 MachineBasicBlock::iterator MI, 222 unsigned DestReg, unsigned SrcReg, 223 const TargetRegisterClass *RC) const { 224 if (RC == PPC::GPRCRegisterClass) { 225 BuildMI(MBB, MI, TII.get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg); 226 } else if (RC == PPC::G8RCRegisterClass) { 227 BuildMI(MBB, MI, TII.get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg); 228 } else if (RC == PPC::F4RCRegisterClass) { 229 BuildMI(MBB, MI, TII.get(PPC::FMRS), DestReg).addReg(SrcReg); 230 } else if (RC == PPC::F8RCRegisterClass) { 231 BuildMI(MBB, MI, TII.get(PPC::FMRD), DestReg).addReg(SrcReg); 232 } else if (RC == PPC::CRRCRegisterClass) { 233 BuildMI(MBB, MI, TII.get(PPC::MCRF), DestReg).addReg(SrcReg); 234 } else if (RC == PPC::VRRCRegisterClass) { 235 BuildMI(MBB, MI, TII.get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg); 236 } else { 237 std::cerr << "Attempt to copy register that is not GPR or FPR"; 238 abort(); 239 } 240 } 241 242 const unsigned* PPCRegisterInfo::getCalleeSaveRegs() const { 243 // 32-bit Darwin calling convention. 244 static const unsigned Darwin32_CalleeSaveRegs[] = { 245 PPC::R13, PPC::R14, PPC::R15, 246 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 247 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 248 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 249 PPC::R28, PPC::R29, PPC::R30, PPC::R31, 250 251 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 252 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 253 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 254 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 255 PPC::F30, PPC::F31, 256 257 PPC::CR2, PPC::CR3, PPC::CR4, 258 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 259 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 260 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 261 262 PPC::LR, 0 263 }; 264 // 64-bit Darwin calling convention. 265 static const unsigned Darwin64_CalleeSaveRegs[] = { 266 PPC::X14, PPC::X15, 267 PPC::X16, PPC::X17, PPC::X18, PPC::X19, 268 PPC::X20, PPC::X21, PPC::X22, PPC::X23, 269 PPC::X24, PPC::X25, PPC::X26, PPC::X27, 270 PPC::X28, PPC::X29, PPC::X30, PPC::X31, 271 272 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 273 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 274 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 275 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 276 PPC::F30, PPC::F31, 277 278 PPC::CR2, PPC::CR3, PPC::CR4, 279 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 280 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 281 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 282 283 PPC::LR8, 0 284 }; 285 286 return Subtarget.isPPC64() ? Darwin64_CalleeSaveRegs : 287 Darwin32_CalleeSaveRegs; 288 } 289 290 const TargetRegisterClass* const* 291 PPCRegisterInfo::getCalleeSaveRegClasses() const { 292 // 32-bit Darwin calling convention. 293 static const TargetRegisterClass * const Darwin32_CalleeSaveRegClasses[] = { 294 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 295 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 296 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 297 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 298 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 299 300 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 301 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 302 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 303 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 304 &PPC::F8RCRegClass,&PPC::F8RCRegClass, 305 306 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, 307 308 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 309 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 310 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 311 312 &PPC::GPRCRegClass, 0 313 }; 314 315 // 64-bit Darwin calling convention. 316 static const TargetRegisterClass * const Darwin64_CalleeSaveRegClasses[] = { 317 &PPC::G8RCRegClass,&PPC::G8RCRegClass, 318 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 319 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 320 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 321 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 322 323 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 324 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 325 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 326 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 327 &PPC::F8RCRegClass,&PPC::F8RCRegClass, 328 329 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, 330 331 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 332 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 333 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 334 335 &PPC::G8RCRegClass, 0 336 }; 337 338 return Subtarget.isPPC64() ? Darwin64_CalleeSaveRegClasses : 339 Darwin32_CalleeSaveRegClasses; 340 } 341 342 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into 343 /// copy instructions, turning them into load/store instructions. 344 MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI, 345 unsigned OpNum, 346 int FrameIndex) const { 347 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because 348 // it takes more than one instruction to store it. 349 unsigned Opc = MI->getOpcode(); 350 351 MachineInstr *NewMI = NULL; 352 if ((Opc == PPC::OR && 353 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { 354 if (OpNum == 0) { // move -> store 355 unsigned InReg = MI->getOperand(1).getReg(); 356 NewMI = addFrameReference(BuildMI(TII.get(PPC::STW)).addReg(InReg), 357 FrameIndex); 358 } else { // move -> load 359 unsigned OutReg = MI->getOperand(0).getReg(); 360 NewMI = addFrameReference(BuildMI(TII.get(PPC::LWZ), OutReg), 361 FrameIndex); 362 } 363 } else if ((Opc == PPC::OR8 && 364 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { 365 if (OpNum == 0) { // move -> store 366 unsigned InReg = MI->getOperand(1).getReg(); 367 NewMI = addFrameReference(BuildMI(TII.get(PPC::STD)).addReg(InReg), 368 FrameIndex); 369 } else { // move -> load 370 unsigned OutReg = MI->getOperand(0).getReg(); 371 NewMI = addFrameReference(BuildMI(TII.get(PPC::LD), OutReg), FrameIndex); 372 } 373 } else if (Opc == PPC::FMRD) { 374 if (OpNum == 0) { // move -> store 375 unsigned InReg = MI->getOperand(1).getReg(); 376 NewMI = addFrameReference(BuildMI(TII.get(PPC::STFD)).addReg(InReg), 377 FrameIndex); 378 } else { // move -> load 379 unsigned OutReg = MI->getOperand(0).getReg(); 380 NewMI = addFrameReference(BuildMI(TII.get(PPC::LFD), OutReg), FrameIndex); 381 } 382 } else if (Opc == PPC::FMRS) { 383 if (OpNum == 0) { // move -> store 384 unsigned InReg = MI->getOperand(1).getReg(); 385 NewMI = addFrameReference(BuildMI(TII.get(PPC::STFS)).addReg(InReg), 386 FrameIndex); 387 } else { // move -> load 388 unsigned OutReg = MI->getOperand(0).getReg(); 389 NewMI = addFrameReference(BuildMI(TII.get(PPC::LFS), OutReg), FrameIndex); 390 } 391 } 392 393 if (NewMI) 394 NewMI->copyKillDeadInfo(MI); 395 return NewMI; 396 } 397 398 //===----------------------------------------------------------------------===// 399 // Stack Frame Processing methods 400 //===----------------------------------------------------------------------===// 401 402 // needsFP - Return true if the specified function should have a dedicated frame 403 // pointer register. This is true if the function has variable sized allocas or 404 // if frame pointer elimination is disabled. 405 // 406 static bool needsFP(const MachineFunction &MF) { 407 const MachineFrameInfo *MFI = MF.getFrameInfo(); 408 return NoFramePointerElim || MFI->hasVarSizedObjects(); 409 } 410 411 // hasFP - Return true if the specified function actually has a dedicated frame 412 // pointer register. This is true if the function needs a frame pointer and has 413 // a non-zero stack size. 414 static bool hasFP(const MachineFunction &MF) { 415 const MachineFrameInfo *MFI = MF.getFrameInfo(); 416 return MFI->getStackSize() && needsFP(MF); 417 } 418 419 /// usesLR - Returns if the link registers (LR) has been used in the function. 420 /// 421 bool PPCRegisterInfo::usesLR(MachineFunction &MF) const { 422 const bool *PhysRegsUsed = MF.getUsedPhysregs(); 423 return PhysRegsUsed[getRARegister()]; 424 } 425 426 void PPCRegisterInfo:: 427 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 428 MachineBasicBlock::iterator I) const { 429 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions. 430 MBB.erase(I); 431 } 432 433 /// LowerDynamicAlloc - Generate the code for allocating an object in the 434 /// current frame. The sequence of code with be in the general form 435 /// 436 /// addi R0, SP, #frameSize ; get the address of the previous frame 437 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size 438 /// addi Rnew, SP, #maxCalFrameSize ; get the top of the allocation 439 /// 440 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const { 441 // Get the instruction. 442 MachineInstr &MI = *II; 443 // Get the instruction's basic block. 444 MachineBasicBlock &MBB = *MI.getParent(); 445 // Get the basic block's function. 446 MachineFunction &MF = *MBB.getParent(); 447 // Get the frame info. 448 MachineFrameInfo *MFI = MF.getFrameInfo(); 449 // Determine whether 64-bit pointers are used. 450 bool LP64 = Subtarget.isPPC64(); 451 452 // Determine the maximum call stack size. maxCallFrameSize may be 453 // less than the minimum. 454 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 455 unsigned getMinCallFrameSize = 456 PPCFrameInfo::getMinCallFrameSize(LP64); 457 maxCallFrameSize = std::max(maxCallFrameSize, getMinCallFrameSize); 458 // Get the total frame size. 459 unsigned FrameSize = MFI->getStackSize(); 460 461 // Get stack alignments. 462 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 463 unsigned MaxAlign = MFI->getMaxAlignment(); 464 assert(MaxAlign <= TargetAlign && 465 "Dynamic alloca with large aligns not supported"); 466 467 // Determine the previous frame's address. If FrameSize can't be 468 // represented as 16 bits or we need special alignment, then we load the 469 // previous frame's address from 0(SP). Why not do an addis of the hi? 470 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. 471 // Constructing the constant and adding would take 3 instructions. 472 // Fortunately, a frame greater than 32K is rare. 473 if (MaxAlign < TargetAlign && isInt16(FrameSize)) { 474 BuildMI(MBB, II, TII.get(PPC::ADDI), PPC::R0) 475 .addReg(PPC::R31) 476 .addImm(FrameSize); 477 } else if (LP64) { 478 BuildMI(MBB, II, TII.get(PPC::LD), PPC::X0) 479 .addImm(0) 480 .addReg(PPC::X1); 481 } else { 482 BuildMI(MBB, II, TII.get(PPC::LWZ), PPC::R0) 483 .addImm(0) 484 .addReg(PPC::R1); 485 } 486 487 // Grow the stack and update the stack pointer link, then 488 // determine the address of new allocated space. 489 if (LP64) { 490 BuildMI(MBB, II, TII.get(PPC::STDUX)) 491 .addReg(PPC::X0) 492 .addReg(PPC::X1) 493 .addReg(MI.getOperand(1).getReg()); 494 BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 495 .addReg(PPC::X1) 496 .addImm(maxCallFrameSize); 497 } else { 498 BuildMI(MBB, II, TII.get(PPC::STWUX)) 499 .addReg(PPC::R0) 500 .addReg(PPC::R1) 501 .addReg(MI.getOperand(1).getReg()); 502 BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 503 .addReg(PPC::R1) 504 .addImm(maxCallFrameSize); 505 } 506 507 // Discard the DYNALLOC instruction. 508 MBB.erase(II); 509 } 510 511 void 512 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { 513 // Get the instruction. 514 MachineInstr &MI = *II; 515 // Get the instruction's basic block. 516 MachineBasicBlock &MBB = *MI.getParent(); 517 // Get the basic block's function. 518 MachineFunction &MF = *MBB.getParent(); 519 // Get the frame info. 520 MachineFrameInfo *MFI = MF.getFrameInfo(); 521 522 // Find out which operand is the frame index. 523 unsigned i = 0; 524 while (!MI.getOperand(i).isFrameIndex()) { 525 ++i; 526 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 527 } 528 // Take into account whether it's an add or mem instruction 529 unsigned OffIdx = (i == 2) ? 1 : 2; 530 // Get the frame index. 531 int FrameIndex = MI.getOperand(i).getFrameIndex(); 532 533 // Get the frame pointer save index. Users of this index are primarily 534 // DYNALLOC instructions. 535 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 536 int FPSI = FI->getFramePointerSaveIndex(); 537 // Get the instruction opcode. 538 unsigned OpC = MI.getOpcode(); 539 540 // Special case for dynamic alloca. 541 if (FPSI && FrameIndex == FPSI && 542 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { 543 lowerDynamicAlloc(II); 544 return; 545 } 546 547 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 548 MI.getOperand(i).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1, false); 549 550 // Figure out if the offset in the instruction is shifted right two bits. This 551 // is true for instructions like "STD", which the machine implicitly adds two 552 // low zeros to. 553 bool isIXAddr = false; 554 switch (OpC) { 555 case PPC::LWA: 556 case PPC::LD: 557 case PPC::STD: 558 case PPC::STD_32: 559 isIXAddr = true; 560 break; 561 } 562 563 // Now add the frame object offset to the offset from r1. 564 int Offset = MFI->getObjectOffset(FrameIndex); 565 566 if (!isIXAddr) 567 Offset += MI.getOperand(OffIdx).getImmedValue(); 568 else 569 Offset += MI.getOperand(OffIdx).getImmedValue() << 2; 570 571 // If we're not using a Frame Pointer that has been set to the value of the 572 // SP before having the stack size subtracted from it, then add the stack size 573 // to Offset to get the correct offset. 574 Offset += MFI->getStackSize(); 575 576 if (!isInt16(Offset)) { 577 // Insert a set of r0 with the full offset value before the ld, st, or add 578 BuildMI(MBB, II, TII.get(PPC::LIS), PPC::R0).addImm(Offset >> 16); 579 BuildMI(MBB, II, TII.get(PPC::ORI), PPC::R0).addReg(PPC::R0).addImm(Offset); 580 581 // convert into indexed form of the instruction 582 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 583 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 584 assert(ImmToIdxMap.count(OpC) && 585 "No indexed form of load or store available!"); 586 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; 587 MI.setInstrDescriptor(TII.get(NewOpcode)); 588 MI.getOperand(1).ChangeToRegister(MI.getOperand(i).getReg(), false); 589 MI.getOperand(2).ChangeToRegister(PPC::R0, false); 590 } else { 591 if (isIXAddr) { 592 assert((Offset & 3) == 0 && "Invalid frame offset!"); 593 Offset >>= 2; // The actual encoded value has the low two bits zero. 594 } 595 MI.getOperand(OffIdx).ChangeToImmediate(Offset); 596 } 597 } 598 599 /// VRRegNo - Map from a numbered VR register to its enum value. 600 /// 601 static const unsigned short VRRegNo[] = { 602 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 , 603 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, 604 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, 605 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31 606 }; 607 608 /// RemoveVRSaveCode - We have found that this function does not need any code 609 /// to manipulate the VRSAVE register, even though it uses vector registers. 610 /// This can happen when the only registers used are known to be live in or out 611 /// of the function. Remove all of the VRSAVE related code from the function. 612 static void RemoveVRSaveCode(MachineInstr *MI) { 613 MachineBasicBlock *Entry = MI->getParent(); 614 MachineFunction *MF = Entry->getParent(); 615 616 // We know that the MTVRSAVE instruction immediately follows MI. Remove it. 617 MachineBasicBlock::iterator MBBI = MI; 618 ++MBBI; 619 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE); 620 MBBI->eraseFromParent(); 621 622 bool RemovedAllMTVRSAVEs = true; 623 // See if we can find and remove the MTVRSAVE instruction from all of the 624 // epilog blocks. 625 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); 626 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) { 627 // If last instruction is a return instruction, add an epilogue 628 if (!I->empty() && TII.isReturn(I->back().getOpcode())) { 629 bool FoundIt = false; 630 for (MBBI = I->end(); MBBI != I->begin(); ) { 631 --MBBI; 632 if (MBBI->getOpcode() == PPC::MTVRSAVE) { 633 MBBI->eraseFromParent(); // remove it. 634 FoundIt = true; 635 break; 636 } 637 } 638 RemovedAllMTVRSAVEs &= FoundIt; 639 } 640 } 641 642 // If we found and removed all MTVRSAVE instructions, remove the read of 643 // VRSAVE as well. 644 if (RemovedAllMTVRSAVEs) { 645 MBBI = MI; 646 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?"); 647 --MBBI; 648 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?"); 649 MBBI->eraseFromParent(); 650 } 651 652 // Finally, nuke the UPDATE_VRSAVE. 653 MI->eraseFromParent(); 654 } 655 656 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the 657 // instruction selector. Based on the vector registers that have been used, 658 // transform this into the appropriate ORI instruction. 659 static void HandleVRSaveUpdate(MachineInstr *MI, const bool *UsedRegs, 660 const TargetInstrInfo &TII) { 661 unsigned UsedRegMask = 0; 662 for (unsigned i = 0; i != 32; ++i) 663 if (UsedRegs[VRRegNo[i]]) 664 UsedRegMask |= 1 << (31-i); 665 666 // Live in and live out values already must be in the mask, so don't bother 667 // marking them. 668 MachineFunction *MF = MI->getParent()->getParent(); 669 for (MachineFunction::livein_iterator I = 670 MF->livein_begin(), E = MF->livein_end(); I != E; ++I) { 671 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first); 672 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg. 673 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 674 } 675 for (MachineFunction::liveout_iterator I = 676 MF->liveout_begin(), E = MF->liveout_end(); I != E; ++I) { 677 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I); 678 if (VRRegNo[RegNo] == *I) // If this really is a vector reg. 679 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 680 } 681 682 unsigned SrcReg = MI->getOperand(1).getReg(); 683 unsigned DstReg = MI->getOperand(0).getReg(); 684 // If no registers are used, turn this into a copy. 685 if (UsedRegMask == 0) { 686 // Remove all VRSAVE code. 687 RemoveVRSaveCode(MI); 688 return; 689 } else if ((UsedRegMask & 0xFFFF) == UsedRegMask) { 690 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg) 691 .addReg(SrcReg).addImm(UsedRegMask); 692 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { 693 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) 694 .addReg(SrcReg).addImm(UsedRegMask >> 16); 695 } else { 696 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) 697 .addReg(SrcReg).addImm(UsedRegMask >> 16); 698 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg) 699 .addReg(DstReg).addImm(UsedRegMask & 0xFFFF); 700 } 701 702 // Remove the old UPDATE_VRSAVE instruction. 703 MI->eraseFromParent(); 704 } 705 706 /// determineFrameLayout - Determine the size of the frame and maximum call 707 /// frame size. 708 void PPCRegisterInfo::determineFrameLayout(MachineFunction &MF) const { 709 MachineFrameInfo *MFI = MF.getFrameInfo(); 710 711 // Get the number of bytes to allocate from the FrameInfo 712 unsigned FrameSize = MFI->getStackSize(); 713 714 // Get the alignments provided by the target, and the maximum alignment 715 // (if any) of the fixed frame objects. 716 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 717 unsigned MaxAlign = MFI->getMaxAlignment(); 718 unsigned Align = std::max(TargetAlign, MaxAlign); 719 assert(isPowerOf2_32(Align) && "Alignment is not power of 2"); 720 unsigned AlignMask = Align - 1; // 721 722 // If we are a leaf function, and use up to 224 bytes of stack space, 723 // don't have a frame pointer, calls, or dynamic alloca then we do not need 724 // to adjust the stack pointer (we fit in the Red Zone). 725 if (FrameSize <= 224 && // Fits in red zone. 726 !MFI->hasVarSizedObjects() && // No dynamic alloca. 727 !MFI->hasCalls() && // No calls. 728 MaxAlign <= TargetAlign) { // No special alignment. 729 // No need for frame 730 MFI->setStackSize(0); 731 return; 732 } 733 734 // Get the maximum call frame size of all the calls. 735 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 736 737 // Maximum call frame needs to be at least big enough for linkage and 8 args. 738 unsigned minCallFrameSize = 739 PPCFrameInfo::getMinCallFrameSize(Subtarget.isPPC64()); 740 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize); 741 742 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so 743 // that allocations will be aligned. 744 if (MFI->hasVarSizedObjects()) 745 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask; 746 747 // Update maximum call frame size. 748 MFI->setMaxCallFrameSize(maxCallFrameSize); 749 750 // Include call frame size in total. 751 FrameSize += maxCallFrameSize; 752 753 // Make sure the frame is aligned. 754 FrameSize = (FrameSize + AlignMask) & ~AlignMask; 755 756 // Update frame info. 757 MFI->setStackSize(FrameSize); 758 } 759 760 void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const { 761 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB 762 MachineBasicBlock::iterator MBBI = MBB.begin(); 763 MachineFrameInfo *MFI = MF.getFrameInfo(); 764 MachineDebugInfo *DebugInfo = MFI->getMachineDebugInfo(); 765 766 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it, 767 // process it. 768 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { 769 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) { 770 HandleVRSaveUpdate(MBBI, MF.getUsedPhysregs(), TII); 771 break; 772 } 773 } 774 775 // Move MBBI back to the beginning of the function. 776 MBBI = MBB.begin(); 777 778 // Work out frame sizes. 779 determineFrameLayout(MF); 780 unsigned FrameSize = MFI->getStackSize(); 781 782 // Skip if a leaf routine. 783 if (!FrameSize) return; 784 785 int NegFrameSize = -FrameSize; 786 787 // Get processor type. 788 bool IsPPC64 = Subtarget.isPPC64(); 789 // Check if the link register (LR) has been used. 790 bool UsesLR = MFI->hasCalls() || usesLR(MF); 791 // Do we have a frame pointer for this function? 792 bool HasFP = hasFP(MF); 793 794 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64); 795 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64); 796 797 if (IsPPC64) { 798 if (UsesLR) 799 BuildMI(MBB, MBBI, TII.get(PPC::MFLR8), PPC::X0); 800 801 if (HasFP) 802 BuildMI(MBB, MBBI, TII.get(PPC::STD)) 803 .addReg(PPC::X31).addImm(FPOffset/4).addReg(PPC::X1); 804 805 if (UsesLR) 806 BuildMI(MBB, MBBI, TII.get(PPC::STD)) 807 .addReg(PPC::X0).addImm(LROffset/4).addReg(PPC::X1); 808 } else { 809 if (UsesLR) 810 BuildMI(MBB, MBBI, TII.get(PPC::MFLR), PPC::R0); 811 812 if (HasFP) 813 BuildMI(MBB, MBBI, TII.get(PPC::STW)) 814 .addReg(PPC::R31).addImm(FPOffset).addReg(PPC::R1); 815 816 if (UsesLR) 817 BuildMI(MBB, MBBI, TII.get(PPC::STW)) 818 .addReg(PPC::R0).addImm(LROffset).addReg(PPC::R1); 819 } 820 821 // Get stack alignments. 822 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 823 unsigned MaxAlign = MFI->getMaxAlignment(); 824 825 // Adjust stack pointer: r1 += NegFrameSize. 826 // If there is a preferred stack alignment, align R1 now 827 if (!IsPPC64) { 828 // PPC32. 829 if (MaxAlign > TargetAlign) { 830 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!"); 831 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!"); 832 BuildMI(MBB, MBBI, TII.get(PPC::RLWINM), PPC::R0) 833 .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31); 834 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC) ,PPC::R0).addReg(PPC::R0) 835 .addImm(NegFrameSize); 836 BuildMI(MBB, MBBI, TII.get(PPC::STWUX)) 837 .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0); 838 } else if (isInt16(NegFrameSize)) { 839 BuildMI(MBB, MBBI, TII.get(PPC::STWU), 840 PPC::R1).addReg(PPC::R1).addImm(NegFrameSize).addReg(PPC::R1); 841 } else { 842 BuildMI(MBB, MBBI, TII.get(PPC::LIS), PPC::R0).addImm(NegFrameSize >> 16); 843 BuildMI(MBB, MBBI, TII.get(PPC::ORI), PPC::R0).addReg(PPC::R0) 844 .addImm(NegFrameSize & 0xFFFF); 845 BuildMI(MBB, MBBI, TII.get(PPC::STWUX)).addReg(PPC::R1).addReg(PPC::R1) 846 .addReg(PPC::R0); 847 } 848 } else { // PPC64. 849 if (MaxAlign > TargetAlign) { 850 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!"); 851 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!"); 852 BuildMI(MBB, MBBI, TII.get(PPC::RLDICL), PPC::X0) 853 .addReg(PPC::X1).addImm(0).addImm(64-Log2_32(MaxAlign)); 854 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC8), PPC::X0).addReg(PPC::X0) 855 .addImm(NegFrameSize); 856 BuildMI(MBB, MBBI, TII.get(PPC::STDUX)) 857 .addReg(PPC::X1).addReg(PPC::X1).addReg(PPC::X0); 858 } else if (isInt16(NegFrameSize)) { 859 BuildMI(MBB, MBBI, TII.get(PPC::STDU), PPC::X1) 860 .addReg(PPC::X1).addImm(NegFrameSize/4).addReg(PPC::X1); 861 } else { 862 BuildMI(MBB, MBBI, TII.get(PPC::LIS8), PPC::X0).addImm(NegFrameSize >>16); 863 BuildMI(MBB, MBBI, TII.get(PPC::ORI8), PPC::X0).addReg(PPC::X0) 864 .addImm(NegFrameSize & 0xFFFF); 865 BuildMI(MBB, MBBI, TII.get(PPC::STDUX)).addReg(PPC::X1).addReg(PPC::X1) 866 .addReg(PPC::X0); 867 } 868 } 869 870 if (DebugInfo && DebugInfo->hasInfo()) { 871 std::vector<MachineMove *> &Moves = DebugInfo->getFrameMoves(); 872 unsigned LabelID = DebugInfo->NextLabelID(); 873 874 // Mark effective beginning of when frame pointer becomes valid. 875 BuildMI(MBB, MBBI, TII.get(PPC::DWARF_LABEL)).addImm(LabelID); 876 877 // Show update of SP. 878 MachineLocation SPDst(MachineLocation::VirtualFP); 879 MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize); 880 Moves.push_back(new MachineMove(LabelID, SPDst, SPSrc)); 881 882 // Add callee saved registers to move list. 883 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 884 for (unsigned I = 0, E = CSI.size(); I != E; ++I) { 885 MachineLocation CSDst(MachineLocation::VirtualFP, 886 MFI->getObjectOffset(CSI[I].getFrameIdx())); 887 MachineLocation CSSrc(CSI[I].getReg()); 888 Moves.push_back(new MachineMove(LabelID, CSDst, CSSrc)); 889 } 890 } 891 892 // If there is a frame pointer, copy R1 into R31 893 if (HasFP) { 894 if (!IsPPC64) { 895 BuildMI(MBB, MBBI, TII.get(PPC::OR), PPC::R31).addReg(PPC::R1) 896 .addReg(PPC::R1); 897 } else { 898 BuildMI(MBB, MBBI, TII.get(PPC::OR8), PPC::X31).addReg(PPC::X1) 899 .addReg(PPC::X1); 900 } 901 } 902 } 903 904 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF, 905 MachineBasicBlock &MBB) const { 906 MachineBasicBlock::iterator MBBI = prior(MBB.end()); 907 assert(MBBI->getOpcode() == PPC::BLR && 908 "Can only insert epilog into returning blocks"); 909 910 // Get alignment info so we know how to restore r1 911 const MachineFrameInfo *MFI = MF.getFrameInfo(); 912 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 913 unsigned MaxAlign = MFI->getMaxAlignment(); 914 915 // Get the number of bytes allocated from the FrameInfo. 916 unsigned FrameSize = MFI->getStackSize(); 917 918 if (!FrameSize) return; 919 920 // Get processor type. 921 bool IsPPC64 = Subtarget.isPPC64(); 922 // Check if the link register (LR) has been used. 923 bool UsesLR = MFI->hasCalls() || usesLR(MF); 924 // Do we have a frame pointer for this function? 925 bool HasFP = hasFP(MF); 926 927 // The loaded (or persistent) stack pointer value is offset by the 'stwu' 928 // on entry to the function. Add this offset back now. 929 if (!Subtarget.isPPC64()) { 930 if (isInt16(FrameSize) && TargetAlign >= MaxAlign && 931 !MFI->hasVarSizedObjects()) { 932 BuildMI(MBB, MBBI, TII.get(PPC::ADDI), PPC::R1) 933 .addReg(PPC::R1).addImm(FrameSize); 934 } else { 935 BuildMI(MBB, MBBI, TII.get(PPC::LWZ),PPC::R1).addImm(0).addReg(PPC::R1); 936 } 937 } else { 938 if (isInt16(FrameSize) && TargetAlign >= MaxAlign && 939 !MFI->hasVarSizedObjects()) { 940 BuildMI(MBB, MBBI, TII.get(PPC::ADDI8), PPC::X1) 941 .addReg(PPC::X1).addImm(FrameSize); 942 } else { 943 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X1).addImm(0).addReg(PPC::X1); 944 } 945 } 946 947 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64); 948 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64); 949 950 if (IsPPC64) { 951 if (UsesLR) 952 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X0) 953 .addImm(LROffset/4).addReg(PPC::X1); 954 955 if (HasFP) 956 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X31) 957 .addImm(FPOffset/4).addReg(PPC::X1); 958 959 if (UsesLR) 960 BuildMI(MBB, MBBI, TII.get(PPC::MTLR8)).addReg(PPC::X0); 961 } else { 962 if (UsesLR) 963 BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R0) 964 .addImm(LROffset).addReg(PPC::R1); 965 966 if (HasFP) 967 BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R31) 968 .addImm(FPOffset).addReg(PPC::R1); 969 970 if (UsesLR) 971 BuildMI(MBB, MBBI, TII.get(PPC::MTLR)).addReg(PPC::R0); 972 } 973 } 974 975 unsigned PPCRegisterInfo::getRARegister() const { 976 return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8; 977 978 } 979 980 unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const { 981 if (!Subtarget.isPPC64()) 982 return hasFP(MF) ? PPC::R31 : PPC::R1; 983 else 984 return hasFP(MF) ? PPC::X31 : PPC::X1; 985 } 986 987 void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove *> &Moves) 988 const { 989 // Initial state of the frame pointer is R1. 990 MachineLocation Dst(MachineLocation::VirtualFP); 991 MachineLocation Src(PPC::R1, 0); 992 Moves.push_back(new MachineMove(0, Dst, Src)); 993 } 994 995 #include "PPCGenRegisterInfo.inc" 996 997