1 //===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the TargetRegisterInfo 11 // class. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "PPCRegisterInfo.h" 16 #include "PPC.h" 17 #include "PPCFrameLowering.h" 18 #include "PPCInstrBuilder.h" 19 #include "PPCMachineFunctionInfo.h" 20 #include "PPCSubtarget.h" 21 #include "llvm/ADT/BitVector.h" 22 #include "llvm/ADT/STLExtras.h" 23 #include "llvm/CodeGen/MachineFrameInfo.h" 24 #include "llvm/CodeGen/MachineFunction.h" 25 #include "llvm/CodeGen/MachineInstrBuilder.h" 26 #include "llvm/CodeGen/MachineModuleInfo.h" 27 #include "llvm/CodeGen/MachineRegisterInfo.h" 28 #include "llvm/CodeGen/RegisterScavenging.h" 29 #include "llvm/IR/CallingConv.h" 30 #include "llvm/IR/Constants.h" 31 #include "llvm/IR/Function.h" 32 #include "llvm/IR/Type.h" 33 #include "llvm/Support/CommandLine.h" 34 #include "llvm/Support/Debug.h" 35 #include "llvm/Support/ErrorHandling.h" 36 #include "llvm/Support/MathExtras.h" 37 #include "llvm/Support/raw_ostream.h" 38 #include "llvm/Target/TargetFrameLowering.h" 39 #include "llvm/Target/TargetInstrInfo.h" 40 #include "llvm/Target/TargetMachine.h" 41 #include "llvm/Target/TargetOptions.h" 42 #include <cstdlib> 43 44 using namespace llvm; 45 46 #define DEBUG_TYPE "reginfo" 47 48 #define GET_REGINFO_TARGET_DESC 49 #include "PPCGenRegisterInfo.inc" 50 51 static cl::opt<bool> 52 EnableBasePointer("ppc-use-base-pointer", cl::Hidden, cl::init(true), 53 cl::desc("Enable use of a base pointer for complex stack frames")); 54 55 static cl::opt<bool> 56 AlwaysBasePointer("ppc-always-use-base-pointer", cl::Hidden, cl::init(false), 57 cl::desc("Force the use of a base pointer in every function")); 58 59 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST) 60 : PPCGenRegisterInfo(ST.isPPC64() ? PPC::LR8 : PPC::LR, 61 ST.isPPC64() ? 0 : 1, 62 ST.isPPC64() ? 0 : 1), 63 Subtarget(ST) { 64 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 65 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 66 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 67 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 68 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 69 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 70 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 71 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 72 ImmToIdxMap[PPC::LWA_32] = PPC::LWAX_32; 73 74 // 64-bit 75 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8; 76 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8; 77 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8; 78 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX; 79 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; 80 } 81 82 /// getPointerRegClass - Return the register class to use to hold pointers. 83 /// This is used for addressing modes. 84 const TargetRegisterClass * 85 PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) 86 const { 87 // Note that PPCInstrInfo::FoldImmediate also directly uses this Kind value 88 // when it checks for ZERO folding. 89 if (Kind == 1) { 90 if (Subtarget.isPPC64()) 91 return &PPC::G8RC_NOX0RegClass; 92 return &PPC::GPRC_NOR0RegClass; 93 } 94 95 if (Subtarget.isPPC64()) 96 return &PPC::G8RCRegClass; 97 return &PPC::GPRCRegClass; 98 } 99 100 const MCPhysReg* 101 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 102 if (MF->getFunction()->getCallingConv() == CallingConv::AnyReg) { 103 if (Subtarget.hasVSX()) 104 return CSR_64_AllRegs_VSX_SaveList; 105 if (Subtarget.hasAltivec()) 106 return CSR_64_AllRegs_Altivec_SaveList; 107 return CSR_64_AllRegs_SaveList; 108 } 109 110 if (Subtarget.isDarwinABI()) 111 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ? 112 CSR_Darwin64_Altivec_SaveList : 113 CSR_Darwin64_SaveList) : 114 (Subtarget.hasAltivec() ? 115 CSR_Darwin32_Altivec_SaveList : 116 CSR_Darwin32_SaveList); 117 118 // On PPC64, we might need to save r2 (but only if it is not reserved). 119 bool SaveR2 = MF->getRegInfo().isAllocatable(PPC::X2); 120 121 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ? 122 (SaveR2 ? CSR_SVR464_R2_Altivec_SaveList : 123 CSR_SVR464_Altivec_SaveList) : 124 (SaveR2 ? CSR_SVR464_R2_SaveList : 125 CSR_SVR464_SaveList)) : 126 (Subtarget.hasAltivec() ? 127 CSR_SVR432_Altivec_SaveList : 128 CSR_SVR432_SaveList); 129 } 130 131 const uint32_t * 132 PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF, 133 CallingConv::ID CC) const { 134 if (CC == CallingConv::AnyReg) { 135 if (Subtarget.hasVSX()) 136 return CSR_64_AllRegs_VSX_RegMask; 137 if (Subtarget.hasAltivec()) 138 return CSR_64_AllRegs_Altivec_RegMask; 139 return CSR_64_AllRegs_RegMask; 140 } 141 142 if (Subtarget.isDarwinABI()) 143 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ? 144 CSR_Darwin64_Altivec_RegMask : 145 CSR_Darwin64_RegMask) : 146 (Subtarget.hasAltivec() ? 147 CSR_Darwin32_Altivec_RegMask : 148 CSR_Darwin32_RegMask); 149 150 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ? 151 CSR_SVR464_Altivec_RegMask : 152 CSR_SVR464_RegMask) : 153 (Subtarget.hasAltivec() ? 154 CSR_SVR432_Altivec_RegMask : 155 CSR_SVR432_RegMask); 156 } 157 158 const uint32_t* 159 PPCRegisterInfo::getNoPreservedMask() const { 160 return CSR_NoRegs_RegMask; 161 } 162 163 void PPCRegisterInfo::adjustStackMapLiveOutMask(uint32_t *Mask) const { 164 for (unsigned PseudoReg : {PPC::ZERO, PPC::ZERO8, PPC::RM}) 165 Mask[PseudoReg / 32] &= ~(1u << (PseudoReg % 32)); 166 } 167 168 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 169 BitVector Reserved(getNumRegs()); 170 const PPCFrameLowering *PPCFI = 171 static_cast<const PPCFrameLowering *>(Subtarget.getFrameLowering()); 172 173 // The ZERO register is not really a register, but the representation of r0 174 // when used in instructions that treat r0 as the constant 0. 175 Reserved.set(PPC::ZERO); 176 Reserved.set(PPC::ZERO8); 177 178 // The FP register is also not really a register, but is the representation 179 // of the frame pointer register used by ISD::FRAMEADDR. 180 Reserved.set(PPC::FP); 181 Reserved.set(PPC::FP8); 182 183 // The BP register is also not really a register, but is the representation 184 // of the base pointer register used by setjmp. 185 Reserved.set(PPC::BP); 186 Reserved.set(PPC::BP8); 187 188 // The counter registers must be reserved so that counter-based loops can 189 // be correctly formed (and the mtctr instructions are not DCE'd). 190 Reserved.set(PPC::CTR); 191 Reserved.set(PPC::CTR8); 192 193 Reserved.set(PPC::R1); 194 Reserved.set(PPC::LR); 195 Reserved.set(PPC::LR8); 196 Reserved.set(PPC::RM); 197 198 if (!Subtarget.isDarwinABI() || !Subtarget.hasAltivec()) 199 Reserved.set(PPC::VRSAVE); 200 201 // The SVR4 ABI reserves r2 and r13 202 if (Subtarget.isSVR4ABI()) { 203 Reserved.set(PPC::R2); // System-reserved register 204 Reserved.set(PPC::R13); // Small Data Area pointer register 205 } 206 207 // On PPC64, r13 is the thread pointer. Never allocate this register. 208 if (Subtarget.isPPC64()) { 209 Reserved.set(PPC::R13); 210 211 Reserved.set(PPC::X1); 212 Reserved.set(PPC::X13); 213 214 if (PPCFI->needsFP(MF)) 215 Reserved.set(PPC::X31); 216 217 if (hasBasePointer(MF)) 218 Reserved.set(PPC::X30); 219 220 // The 64-bit SVR4 ABI reserves r2 for the TOC pointer. 221 if (Subtarget.isSVR4ABI()) { 222 // We only reserve r2 if we need to use the TOC pointer. If we have no 223 // explicit uses of the TOC pointer (meaning we're a leaf function with 224 // no constant-pool loads, etc.) and we have no potential uses inside an 225 // inline asm block, then we can treat r2 has an ordinary callee-saved 226 // register. 227 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 228 if (FuncInfo->usesTOCBasePtr() || MF.hasInlineAsm()) 229 Reserved.set(PPC::X2); 230 else 231 Reserved.reset(PPC::R2); 232 } 233 } 234 235 if (PPCFI->needsFP(MF)) 236 Reserved.set(PPC::R31); 237 238 if (hasBasePointer(MF)) { 239 if (Subtarget.isSVR4ABI() && !Subtarget.isPPC64() && 240 MF.getTarget().getRelocationModel() == Reloc::PIC_) 241 Reserved.set(PPC::R29); 242 else 243 Reserved.set(PPC::R30); 244 } 245 246 if (Subtarget.isSVR4ABI() && !Subtarget.isPPC64() && 247 MF.getTarget().getRelocationModel() == Reloc::PIC_) 248 Reserved.set(PPC::R30); 249 250 // Reserve Altivec registers when Altivec is unavailable. 251 if (!Subtarget.hasAltivec()) 252 for (TargetRegisterClass::iterator I = PPC::VRRCRegClass.begin(), 253 IE = PPC::VRRCRegClass.end(); I != IE; ++I) 254 Reserved.set(*I); 255 256 return Reserved; 257 } 258 259 unsigned PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 260 MachineFunction &MF) const { 261 const TargetFrameLowering *TFI = Subtarget.getFrameLowering(); 262 const unsigned DefaultSafety = 1; 263 264 switch (RC->getID()) { 265 default: 266 return 0; 267 case PPC::G8RC_NOX0RegClassID: 268 case PPC::GPRC_NOR0RegClassID: 269 case PPC::G8RCRegClassID: 270 case PPC::GPRCRegClassID: { 271 unsigned FP = TFI->hasFP(MF) ? 1 : 0; 272 return 32 - FP - DefaultSafety; 273 } 274 case PPC::F8RCRegClassID: 275 case PPC::F4RCRegClassID: 276 case PPC::QFRCRegClassID: 277 case PPC::QSRCRegClassID: 278 case PPC::QBRCRegClassID: 279 case PPC::VRRCRegClassID: 280 case PPC::VFRCRegClassID: 281 case PPC::VSLRCRegClassID: 282 case PPC::VSHRCRegClassID: 283 return 32 - DefaultSafety; 284 case PPC::VSRCRegClassID: 285 case PPC::VSFRCRegClassID: 286 return 64 - DefaultSafety; 287 case PPC::CRRCRegClassID: 288 return 8 - DefaultSafety; 289 } 290 } 291 292 const TargetRegisterClass * 293 PPCRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC, 294 const MachineFunction &MF) const { 295 if (Subtarget.hasVSX()) { 296 // With VSX, we can inflate various sub-register classes to the full VSX 297 // register set. 298 299 if (RC == &PPC::F8RCRegClass) 300 return &PPC::VSFRCRegClass; 301 else if (RC == &PPC::VRRCRegClass) 302 return &PPC::VSRCRegClass; 303 } 304 305 return TargetRegisterInfo::getLargestLegalSuperClass(RC, MF); 306 } 307 308 //===----------------------------------------------------------------------===// 309 // Stack Frame Processing methods 310 //===----------------------------------------------------------------------===// 311 312 /// lowerDynamicAlloc - Generate the code for allocating an object in the 313 /// current frame. The sequence of code with be in the general form 314 /// 315 /// addi R0, SP, \#frameSize ; get the address of the previous frame 316 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size 317 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation 318 /// 319 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const { 320 // Get the instruction. 321 MachineInstr &MI = *II; 322 // Get the instruction's basic block. 323 MachineBasicBlock &MBB = *MI.getParent(); 324 // Get the basic block's function. 325 MachineFunction &MF = *MBB.getParent(); 326 // Get the frame info. 327 MachineFrameInfo *MFI = MF.getFrameInfo(); 328 // Get the instruction info. 329 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 330 // Determine whether 64-bit pointers are used. 331 bool LP64 = Subtarget.isPPC64(); 332 DebugLoc dl = MI.getDebugLoc(); 333 334 // Get the maximum call stack size. 335 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 336 // Get the total frame size. 337 unsigned FrameSize = MFI->getStackSize(); 338 339 // Get stack alignments. 340 unsigned TargetAlign = Subtarget.getFrameLowering()->getStackAlignment(); 341 unsigned MaxAlign = MFI->getMaxAlignment(); 342 assert((maxCallFrameSize & (MaxAlign-1)) == 0 && 343 "Maximum call-frame size not sufficiently aligned"); 344 345 // Determine the previous frame's address. If FrameSize can't be 346 // represented as 16 bits or we need special alignment, then we load the 347 // previous frame's address from 0(SP). Why not do an addis of the hi? 348 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. 349 // Constructing the constant and adding would take 3 instructions. 350 // Fortunately, a frame greater than 32K is rare. 351 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 352 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 353 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 354 355 if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) { 356 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) 357 .addReg(PPC::R31) 358 .addImm(FrameSize); 359 } else if (LP64) { 360 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg) 361 .addImm(0) 362 .addReg(PPC::X1); 363 } else { 364 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) 365 .addImm(0) 366 .addReg(PPC::R1); 367 } 368 369 bool KillNegSizeReg = MI.getOperand(1).isKill(); 370 unsigned NegSizeReg = MI.getOperand(1).getReg(); 371 372 // Grow the stack and update the stack pointer link, then determine the 373 // address of new allocated space. 374 if (LP64) { 375 if (MaxAlign > TargetAlign) { 376 unsigned UnalNegSizeReg = NegSizeReg; 377 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC); 378 379 // Unfortunately, there is no andi, only andi., and we can't insert that 380 // here because we might clobber cr0 while it is live. 381 BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg) 382 .addImm(~(MaxAlign-1)); 383 384 unsigned NegSizeReg1 = NegSizeReg; 385 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC); 386 BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg) 387 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg)) 388 .addReg(NegSizeReg1, RegState::Kill); 389 KillNegSizeReg = true; 390 } 391 392 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1) 393 .addReg(Reg, RegState::Kill) 394 .addReg(PPC::X1) 395 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg)); 396 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 397 .addReg(PPC::X1) 398 .addImm(maxCallFrameSize); 399 } else { 400 if (MaxAlign > TargetAlign) { 401 unsigned UnalNegSizeReg = NegSizeReg; 402 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); 403 404 // Unfortunately, there is no andi, only andi., and we can't insert that 405 // here because we might clobber cr0 while it is live. 406 BuildMI(MBB, II, dl, TII.get(PPC::LI), NegSizeReg) 407 .addImm(~(MaxAlign-1)); 408 409 unsigned NegSizeReg1 = NegSizeReg; 410 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); 411 BuildMI(MBB, II, dl, TII.get(PPC::AND), NegSizeReg) 412 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg)) 413 .addReg(NegSizeReg1, RegState::Kill); 414 KillNegSizeReg = true; 415 } 416 417 BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1) 418 .addReg(Reg, RegState::Kill) 419 .addReg(PPC::R1) 420 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg)); 421 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 422 .addReg(PPC::R1) 423 .addImm(maxCallFrameSize); 424 } 425 426 // Discard the DYNALLOC instruction. 427 MBB.erase(II); 428 } 429 430 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of 431 /// reserving a whole register (R0), we scrounge for one here. This generates 432 /// code like this: 433 /// 434 /// mfcr rA ; Move the conditional register into GPR rA. 435 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot. 436 /// stw rA, FI ; Store rA to the frame. 437 /// 438 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, 439 unsigned FrameIndex) const { 440 // Get the instruction. 441 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset> 442 // Get the instruction's basic block. 443 MachineBasicBlock &MBB = *MI.getParent(); 444 MachineFunction &MF = *MBB.getParent(); 445 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 446 DebugLoc dl = MI.getDebugLoc(); 447 448 bool LP64 = Subtarget.isPPC64(); 449 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 450 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 451 452 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 453 unsigned SrcReg = MI.getOperand(0).getReg(); 454 455 // We need to store the CR in the low 4-bits of the saved value. First, issue 456 // an MFOCRF to save all of the CRBits and, if needed, kill the SrcReg. 457 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg) 458 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 459 460 // If the saved register wasn't CR0, shift the bits left so that they are in 461 // CR0's slot. 462 if (SrcReg != PPC::CR0) { 463 unsigned Reg1 = Reg; 464 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 465 466 // rlwinm rA, rA, ShiftBits, 0, 31. 467 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 468 .addReg(Reg1, RegState::Kill) 469 .addImm(getEncodingValue(SrcReg) * 4) 470 .addImm(0) 471 .addImm(31); 472 } 473 474 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW)) 475 .addReg(Reg, RegState::Kill), 476 FrameIndex); 477 478 // Discard the pseudo instruction. 479 MBB.erase(II); 480 } 481 482 void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II, 483 unsigned FrameIndex) const { 484 // Get the instruction. 485 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset> 486 // Get the instruction's basic block. 487 MachineBasicBlock &MBB = *MI.getParent(); 488 MachineFunction &MF = *MBB.getParent(); 489 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 490 DebugLoc dl = MI.getDebugLoc(); 491 492 bool LP64 = Subtarget.isPPC64(); 493 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 494 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 495 496 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 497 unsigned DestReg = MI.getOperand(0).getReg(); 498 assert(MI.definesRegister(DestReg) && 499 "RESTORE_CR does not define its destination"); 500 501 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), 502 Reg), FrameIndex); 503 504 // If the reloaded register isn't CR0, shift the bits right so that they are 505 // in the right CR's slot. 506 if (DestReg != PPC::CR0) { 507 unsigned Reg1 = Reg; 508 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 509 510 unsigned ShiftBits = getEncodingValue(DestReg)*4; 511 // rlwinm r11, r11, 32-ShiftBits, 0, 31. 512 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 513 .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0) 514 .addImm(31); 515 } 516 517 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), DestReg) 518 .addReg(Reg, RegState::Kill); 519 520 // Discard the pseudo instruction. 521 MBB.erase(II); 522 } 523 524 static unsigned getCRFromCRBit(unsigned SrcReg) { 525 unsigned Reg = 0; 526 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT || 527 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN) 528 Reg = PPC::CR0; 529 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT || 530 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN) 531 Reg = PPC::CR1; 532 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT || 533 SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN) 534 Reg = PPC::CR2; 535 else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT || 536 SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN) 537 Reg = PPC::CR3; 538 else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT || 539 SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN) 540 Reg = PPC::CR4; 541 else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT || 542 SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN) 543 Reg = PPC::CR5; 544 else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT || 545 SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN) 546 Reg = PPC::CR6; 547 else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT || 548 SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN) 549 Reg = PPC::CR7; 550 551 assert(Reg != 0 && "Invalid CR bit register"); 552 return Reg; 553 } 554 555 void PPCRegisterInfo::lowerCRBitSpilling(MachineBasicBlock::iterator II, 556 unsigned FrameIndex) const { 557 // Get the instruction. 558 MachineInstr &MI = *II; // ; SPILL_CRBIT <SrcReg>, <offset> 559 // Get the instruction's basic block. 560 MachineBasicBlock &MBB = *MI.getParent(); 561 MachineFunction &MF = *MBB.getParent(); 562 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 563 DebugLoc dl = MI.getDebugLoc(); 564 565 bool LP64 = Subtarget.isPPC64(); 566 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 567 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 568 569 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 570 unsigned SrcReg = MI.getOperand(0).getReg(); 571 572 BuildMI(MBB, II, dl, TII.get(TargetOpcode::KILL), 573 getCRFromCRBit(SrcReg)) 574 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 575 576 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg) 577 .addReg(getCRFromCRBit(SrcReg)); 578 579 // If the saved register wasn't CR0LT, shift the bits left so that the bit to 580 // store is the first one. Mask all but that bit. 581 unsigned Reg1 = Reg; 582 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 583 584 // rlwinm rA, rA, ShiftBits, 0, 0. 585 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 586 .addReg(Reg1, RegState::Kill) 587 .addImm(getEncodingValue(SrcReg)) 588 .addImm(0).addImm(0); 589 590 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW)) 591 .addReg(Reg, RegState::Kill), 592 FrameIndex); 593 594 // Discard the pseudo instruction. 595 MBB.erase(II); 596 } 597 598 void PPCRegisterInfo::lowerCRBitRestore(MachineBasicBlock::iterator II, 599 unsigned FrameIndex) const { 600 // Get the instruction. 601 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CRBIT <offset> 602 // Get the instruction's basic block. 603 MachineBasicBlock &MBB = *MI.getParent(); 604 MachineFunction &MF = *MBB.getParent(); 605 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 606 DebugLoc dl = MI.getDebugLoc(); 607 608 bool LP64 = Subtarget.isPPC64(); 609 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 610 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 611 612 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 613 unsigned DestReg = MI.getOperand(0).getReg(); 614 assert(MI.definesRegister(DestReg) && 615 "RESTORE_CRBIT does not define its destination"); 616 617 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), 618 Reg), FrameIndex); 619 620 BuildMI(MBB, II, dl, TII.get(TargetOpcode::IMPLICIT_DEF), DestReg); 621 622 unsigned RegO = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 623 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), RegO) 624 .addReg(getCRFromCRBit(DestReg)); 625 626 unsigned ShiftBits = getEncodingValue(DestReg); 627 // rlwimi r11, r10, 32-ShiftBits, ..., ... 628 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWIMI8 : PPC::RLWIMI), RegO) 629 .addReg(RegO, RegState::Kill).addReg(Reg, RegState::Kill) 630 .addImm(ShiftBits ? 32-ShiftBits : 0) 631 .addImm(ShiftBits).addImm(ShiftBits); 632 633 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), 634 getCRFromCRBit(DestReg)) 635 .addReg(RegO, RegState::Kill) 636 // Make sure we have a use dependency all the way through this 637 // sequence of instructions. We can't have the other bits in the CR 638 // modified in between the mfocrf and the mtocrf. 639 .addReg(getCRFromCRBit(DestReg), RegState::Implicit); 640 641 // Discard the pseudo instruction. 642 MBB.erase(II); 643 } 644 645 void PPCRegisterInfo::lowerVRSAVESpilling(MachineBasicBlock::iterator II, 646 unsigned FrameIndex) const { 647 // Get the instruction. 648 MachineInstr &MI = *II; // ; SPILL_VRSAVE <SrcReg>, <offset> 649 // Get the instruction's basic block. 650 MachineBasicBlock &MBB = *MI.getParent(); 651 MachineFunction &MF = *MBB.getParent(); 652 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 653 DebugLoc dl = MI.getDebugLoc(); 654 655 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 656 unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC); 657 unsigned SrcReg = MI.getOperand(0).getReg(); 658 659 BuildMI(MBB, II, dl, TII.get(PPC::MFVRSAVEv), Reg) 660 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 661 662 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::STW)) 663 .addReg(Reg, RegState::Kill), 664 FrameIndex); 665 666 // Discard the pseudo instruction. 667 MBB.erase(II); 668 } 669 670 void PPCRegisterInfo::lowerVRSAVERestore(MachineBasicBlock::iterator II, 671 unsigned FrameIndex) const { 672 // Get the instruction. 673 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_VRSAVE <offset> 674 // Get the instruction's basic block. 675 MachineBasicBlock &MBB = *MI.getParent(); 676 MachineFunction &MF = *MBB.getParent(); 677 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 678 DebugLoc dl = MI.getDebugLoc(); 679 680 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 681 unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC); 682 unsigned DestReg = MI.getOperand(0).getReg(); 683 assert(MI.definesRegister(DestReg) && 684 "RESTORE_VRSAVE does not define its destination"); 685 686 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::LWZ), 687 Reg), FrameIndex); 688 689 BuildMI(MBB, II, dl, TII.get(PPC::MTVRSAVEv), DestReg) 690 .addReg(Reg, RegState::Kill); 691 692 // Discard the pseudo instruction. 693 MBB.erase(II); 694 } 695 696 bool 697 PPCRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF, 698 unsigned Reg, int &FrameIdx) const { 699 700 // For the nonvolatile condition registers (CR2, CR3, CR4) in an SVR4 701 // ABI, return true to prevent allocating an additional frame slot. 702 // For 64-bit, the CR save area is at SP+8; the value of FrameIdx = 0 703 // is arbitrary and will be subsequently ignored. For 32-bit, we have 704 // previously created the stack slot if needed, so return its FrameIdx. 705 if (Subtarget.isSVR4ABI() && PPC::CR2 <= Reg && Reg <= PPC::CR4) { 706 if (Subtarget.isPPC64()) 707 FrameIdx = 0; 708 else { 709 const PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 710 FrameIdx = FI->getCRSpillFrameIndex(); 711 } 712 return true; 713 } 714 return false; 715 } 716 717 // Figure out if the offset in the instruction must be a multiple of 4. 718 // This is true for instructions like "STD". 719 static bool usesIXAddr(const MachineInstr &MI) { 720 unsigned OpC = MI.getOpcode(); 721 722 switch (OpC) { 723 default: 724 return false; 725 case PPC::LWA: 726 case PPC::LWA_32: 727 case PPC::LD: 728 case PPC::STD: 729 return true; 730 } 731 } 732 733 // Return the OffsetOperandNo given the FIOperandNum (and the instruction). 734 static unsigned getOffsetONFromFION(const MachineInstr &MI, 735 unsigned FIOperandNum) { 736 // Take into account whether it's an add or mem instruction 737 unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2; 738 if (MI.isInlineAsm()) 739 OffsetOperandNo = FIOperandNum - 1; 740 else if (MI.getOpcode() == TargetOpcode::STACKMAP || 741 MI.getOpcode() == TargetOpcode::PATCHPOINT) 742 OffsetOperandNo = FIOperandNum + 1; 743 744 return OffsetOperandNo; 745 } 746 747 void 748 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 749 int SPAdj, unsigned FIOperandNum, 750 RegScavenger *RS) const { 751 assert(SPAdj == 0 && "Unexpected"); 752 753 // Get the instruction. 754 MachineInstr &MI = *II; 755 // Get the instruction's basic block. 756 MachineBasicBlock &MBB = *MI.getParent(); 757 // Get the basic block's function. 758 MachineFunction &MF = *MBB.getParent(); 759 // Get the instruction info. 760 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 761 // Get the frame info. 762 MachineFrameInfo *MFI = MF.getFrameInfo(); 763 DebugLoc dl = MI.getDebugLoc(); 764 765 unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum); 766 767 // Get the frame index. 768 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 769 770 // Get the frame pointer save index. Users of this index are primarily 771 // DYNALLOC instructions. 772 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 773 int FPSI = FI->getFramePointerSaveIndex(); 774 // Get the instruction opcode. 775 unsigned OpC = MI.getOpcode(); 776 777 // Special case for dynamic alloca. 778 if (FPSI && FrameIndex == FPSI && 779 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { 780 lowerDynamicAlloc(II); 781 return; 782 } 783 784 // Special case for pseudo-ops SPILL_CR and RESTORE_CR, etc. 785 if (OpC == PPC::SPILL_CR) { 786 lowerCRSpilling(II, FrameIndex); 787 return; 788 } else if (OpC == PPC::RESTORE_CR) { 789 lowerCRRestore(II, FrameIndex); 790 return; 791 } else if (OpC == PPC::SPILL_CRBIT) { 792 lowerCRBitSpilling(II, FrameIndex); 793 return; 794 } else if (OpC == PPC::RESTORE_CRBIT) { 795 lowerCRBitRestore(II, FrameIndex); 796 return; 797 } else if (OpC == PPC::SPILL_VRSAVE) { 798 lowerVRSAVESpilling(II, FrameIndex); 799 return; 800 } else if (OpC == PPC::RESTORE_VRSAVE) { 801 lowerVRSAVERestore(II, FrameIndex); 802 return; 803 } 804 805 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 806 MI.getOperand(FIOperandNum).ChangeToRegister( 807 FrameIndex < 0 ? getBaseRegister(MF) : getFrameRegister(MF), false); 808 809 // Figure out if the offset in the instruction is shifted right two bits. 810 bool isIXAddr = usesIXAddr(MI); 811 812 // If the instruction is not present in ImmToIdxMap, then it has no immediate 813 // form (and must be r+r). 814 bool noImmForm = !MI.isInlineAsm() && OpC != TargetOpcode::STACKMAP && 815 OpC != TargetOpcode::PATCHPOINT && !ImmToIdxMap.count(OpC); 816 817 // Now add the frame object offset to the offset from r1. 818 int Offset = MFI->getObjectOffset(FrameIndex); 819 Offset += MI.getOperand(OffsetOperandNo).getImm(); 820 821 // If we're not using a Frame Pointer that has been set to the value of the 822 // SP before having the stack size subtracted from it, then add the stack size 823 // to Offset to get the correct offset. 824 // Naked functions have stack size 0, although getStackSize may not reflect that 825 // because we didn't call all the pieces that compute it for naked functions. 826 if (!MF.getFunction()->hasFnAttribute(Attribute::Naked)) { 827 if (!(hasBasePointer(MF) && FrameIndex < 0)) 828 Offset += MFI->getStackSize(); 829 } 830 831 // If we can, encode the offset directly into the instruction. If this is a 832 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If 833 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits 834 // clear can be encoded. This is extremely uncommon, because normally you 835 // only "std" to a stack slot that is at least 4-byte aligned, but it can 836 // happen in invalid code. 837 assert(OpC != PPC::DBG_VALUE && 838 "This should be handled in a target-independent way"); 839 if (!noImmForm && ((isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0)) || 840 OpC == TargetOpcode::STACKMAP || 841 OpC == TargetOpcode::PATCHPOINT)) { 842 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 843 return; 844 } 845 846 // The offset doesn't fit into a single register, scavenge one to build the 847 // offset in. 848 849 bool is64Bit = Subtarget.isPPC64(); 850 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 851 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 852 const TargetRegisterClass *RC = is64Bit ? G8RC : GPRC; 853 unsigned SRegHi = MF.getRegInfo().createVirtualRegister(RC), 854 SReg = MF.getRegInfo().createVirtualRegister(RC); 855 856 // Insert a set of rA with the full offset value before the ld, st, or add 857 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SRegHi) 858 .addImm(Offset >> 16); 859 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg) 860 .addReg(SRegHi, RegState::Kill) 861 .addImm(Offset); 862 863 // Convert into indexed form of the instruction: 864 // 865 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 866 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 867 unsigned OperandBase; 868 869 if (noImmForm) 870 OperandBase = 1; 871 else if (OpC != TargetOpcode::INLINEASM) { 872 assert(ImmToIdxMap.count(OpC) && 873 "No indexed form of load or store available!"); 874 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; 875 MI.setDesc(TII.get(NewOpcode)); 876 OperandBase = 1; 877 } else { 878 OperandBase = OffsetOperandNo; 879 } 880 881 unsigned StackReg = MI.getOperand(FIOperandNum).getReg(); 882 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false); 883 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true); 884 } 885 886 unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 887 const TargetFrameLowering *TFI = Subtarget.getFrameLowering(); 888 889 if (!Subtarget.isPPC64()) 890 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1; 891 else 892 return TFI->hasFP(MF) ? PPC::X31 : PPC::X1; 893 } 894 895 unsigned PPCRegisterInfo::getBaseRegister(const MachineFunction &MF) const { 896 if (!hasBasePointer(MF)) 897 return getFrameRegister(MF); 898 899 if (Subtarget.isPPC64()) 900 return PPC::X30; 901 902 if (Subtarget.isSVR4ABI() && 903 MF.getTarget().getRelocationModel() == Reloc::PIC_) 904 return PPC::R29; 905 906 return PPC::R30; 907 } 908 909 bool PPCRegisterInfo::hasBasePointer(const MachineFunction &MF) const { 910 if (!EnableBasePointer) 911 return false; 912 if (AlwaysBasePointer) 913 return true; 914 915 // If we need to realign the stack, then the stack pointer can no longer 916 // serve as an offset into the caller's stack space. As a result, we need a 917 // base pointer. 918 return needsStackRealignment(MF); 919 } 920 921 bool PPCRegisterInfo::canRealignStack(const MachineFunction &MF) const { 922 if (MF.getFunction()->hasFnAttribute("no-realign-stack")) 923 return false; 924 925 return true; 926 } 927 928 bool PPCRegisterInfo::needsStackRealignment(const MachineFunction &MF) const { 929 const MachineFrameInfo *MFI = MF.getFrameInfo(); 930 const Function *F = MF.getFunction(); 931 unsigned StackAlign = Subtarget.getFrameLowering()->getStackAlignment(); 932 bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) || 933 F->hasFnAttribute(Attribute::StackAlignment)); 934 935 return requiresRealignment && canRealignStack(MF); 936 } 937 938 /// Returns true if the instruction's frame index 939 /// reference would be better served by a base register other than FP 940 /// or SP. Used by LocalStackFrameAllocation to determine which frame index 941 /// references it should create new base registers for. 942 bool PPCRegisterInfo:: 943 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { 944 assert(Offset < 0 && "Local offset must be negative"); 945 946 // It's the load/store FI references that cause issues, as it can be difficult 947 // to materialize the offset if it won't fit in the literal field. Estimate 948 // based on the size of the local frame and some conservative assumptions 949 // about the rest of the stack frame (note, this is pre-regalloc, so 950 // we don't know everything for certain yet) whether this offset is likely 951 // to be out of range of the immediate. Return true if so. 952 953 // We only generate virtual base registers for loads and stores that have 954 // an r+i form. Return false for everything else. 955 unsigned OpC = MI->getOpcode(); 956 if (!ImmToIdxMap.count(OpC)) 957 return false; 958 959 // Don't generate a new virtual base register just to add zero to it. 960 if ((OpC == PPC::ADDI || OpC == PPC::ADDI8) && 961 MI->getOperand(2).getImm() == 0) 962 return false; 963 964 MachineBasicBlock &MBB = *MI->getParent(); 965 MachineFunction &MF = *MBB.getParent(); 966 967 const PPCFrameLowering *PPCFI = 968 static_cast<const PPCFrameLowering *>(Subtarget.getFrameLowering()); 969 unsigned StackEst = 970 PPCFI->determineFrameLayout(MF, false, true); 971 972 // If we likely don't need a stack frame, then we probably don't need a 973 // virtual base register either. 974 if (!StackEst) 975 return false; 976 977 // Estimate an offset from the stack pointer. 978 // The incoming offset is relating to the SP at the start of the function, 979 // but when we access the local it'll be relative to the SP after local 980 // allocation, so adjust our SP-relative offset by that allocation size. 981 Offset += StackEst; 982 983 // The frame pointer will point to the end of the stack, so estimate the 984 // offset as the difference between the object offset and the FP location. 985 return !isFrameOffsetLegal(MI, Offset); 986 } 987 988 /// Insert defining instruction(s) for BaseReg to 989 /// be a pointer to FrameIdx at the beginning of the basic block. 990 void PPCRegisterInfo:: 991 materializeFrameBaseRegister(MachineBasicBlock *MBB, 992 unsigned BaseReg, int FrameIdx, 993 int64_t Offset) const { 994 unsigned ADDriOpc = Subtarget.isPPC64() ? PPC::ADDI8 : PPC::ADDI; 995 996 MachineBasicBlock::iterator Ins = MBB->begin(); 997 DebugLoc DL; // Defaults to "unknown" 998 if (Ins != MBB->end()) 999 DL = Ins->getDebugLoc(); 1000 1001 const MachineFunction &MF = *MBB->getParent(); 1002 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 1003 const MCInstrDesc &MCID = TII.get(ADDriOpc); 1004 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 1005 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); 1006 1007 BuildMI(*MBB, Ins, DL, MCID, BaseReg) 1008 .addFrameIndex(FrameIdx).addImm(Offset); 1009 } 1010 1011 void PPCRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, 1012 int64_t Offset) const { 1013 unsigned FIOperandNum = 0; 1014 while (!MI.getOperand(FIOperandNum).isFI()) { 1015 ++FIOperandNum; 1016 assert(FIOperandNum < MI.getNumOperands() && 1017 "Instr doesn't have FrameIndex operand!"); 1018 } 1019 1020 MI.getOperand(FIOperandNum).ChangeToRegister(BaseReg, false); 1021 unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum); 1022 Offset += MI.getOperand(OffsetOperandNo).getImm(); 1023 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 1024 1025 MachineBasicBlock &MBB = *MI.getParent(); 1026 MachineFunction &MF = *MBB.getParent(); 1027 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 1028 const MCInstrDesc &MCID = MI.getDesc(); 1029 MachineRegisterInfo &MRI = MF.getRegInfo(); 1030 MRI.constrainRegClass(BaseReg, 1031 TII.getRegClass(MCID, FIOperandNum, this, MF)); 1032 } 1033 1034 bool PPCRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, 1035 int64_t Offset) const { 1036 unsigned FIOperandNum = 0; 1037 while (!MI->getOperand(FIOperandNum).isFI()) { 1038 ++FIOperandNum; 1039 assert(FIOperandNum < MI->getNumOperands() && 1040 "Instr doesn't have FrameIndex operand!"); 1041 } 1042 1043 unsigned OffsetOperandNo = getOffsetONFromFION(*MI, FIOperandNum); 1044 Offset += MI->getOperand(OffsetOperandNo).getImm(); 1045 1046 return MI->getOpcode() == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm 1047 MI->getOpcode() == TargetOpcode::STACKMAP || 1048 MI->getOpcode() == TargetOpcode::PATCHPOINT || 1049 (isInt<16>(Offset) && (!usesIXAddr(*MI) || (Offset & 3) == 0)); 1050 } 1051 1052