1 //===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the TargetRegisterInfo 11 // class. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #define DEBUG_TYPE "reginfo" 16 #include "PPCRegisterInfo.h" 17 #include "PPC.h" 18 #include "PPCInstrBuilder.h" 19 #include "PPCMachineFunctionInfo.h" 20 #include "PPCFrameLowering.h" 21 #include "PPCSubtarget.h" 22 #include "llvm/CallingConv.h" 23 #include "llvm/Constants.h" 24 #include "llvm/Function.h" 25 #include "llvm/Type.h" 26 #include "llvm/CodeGen/ValueTypes.h" 27 #include "llvm/CodeGen/MachineInstrBuilder.h" 28 #include "llvm/CodeGen/MachineModuleInfo.h" 29 #include "llvm/CodeGen/MachineFunction.h" 30 #include "llvm/CodeGen/MachineFrameInfo.h" 31 #include "llvm/CodeGen/MachineRegisterInfo.h" 32 #include "llvm/CodeGen/RegisterScavenging.h" 33 #include "llvm/Target/TargetFrameLowering.h" 34 #include "llvm/Target/TargetInstrInfo.h" 35 #include "llvm/Target/TargetMachine.h" 36 #include "llvm/Target/TargetOptions.h" 37 #include "llvm/Support/CommandLine.h" 38 #include "llvm/Support/Debug.h" 39 #include "llvm/Support/ErrorHandling.h" 40 #include "llvm/Support/MathExtras.h" 41 #include "llvm/Support/raw_ostream.h" 42 #include "llvm/ADT/BitVector.h" 43 #include "llvm/ADT/STLExtras.h" 44 #include <cstdlib> 45 46 #define GET_REGINFO_TARGET_DESC 47 #include "PPCGenRegisterInfo.inc" 48 49 namespace llvm { 50 cl::opt<bool> DisablePPC32RS("disable-ppc32-regscavenger", 51 cl::init(false), 52 cl::desc("Disable PPC32 register scavenger"), 53 cl::Hidden); 54 cl::opt<bool> DisablePPC64RS("disable-ppc64-regscavenger", 55 cl::init(false), 56 cl::desc("Disable PPC64 register scavenger"), 57 cl::Hidden); 58 } 59 60 using namespace llvm; 61 62 // FIXME (64-bit): Should be inlined. 63 bool 64 PPCRegisterInfo::requiresRegisterScavenging(const MachineFunction &) const { 65 return ((!DisablePPC32RS && !Subtarget.isPPC64()) || 66 (!DisablePPC64RS && Subtarget.isPPC64())); 67 } 68 69 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST, 70 const TargetInstrInfo &tii) 71 : PPCGenRegisterInfo(ST.isPPC64() ? PPC::LR8 : PPC::LR, 72 ST.isPPC64() ? 0 : 1, 73 ST.isPPC64() ? 0 : 1), 74 Subtarget(ST), TII(tii) { 75 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 76 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 77 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 78 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 79 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 80 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 81 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 82 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 83 84 // 64-bit 85 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8; 86 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8; 87 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8; 88 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX; 89 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32; 90 } 91 92 bool 93 PPCRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const { 94 return requiresRegisterScavenging(MF); 95 } 96 97 98 /// getPointerRegClass - Return the register class to use to hold pointers. 99 /// This is used for addressing modes. 100 const TargetRegisterClass * 101 PPCRegisterInfo::getPointerRegClass(unsigned Kind) const { 102 if (Subtarget.isPPC64()) 103 return &PPC::G8RCRegClass; 104 return &PPC::GPRCRegClass; 105 } 106 107 const uint16_t* 108 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 109 if (Subtarget.isDarwinABI()) 110 return Subtarget.isPPC64() ? CSR_Darwin64_SaveList : 111 CSR_Darwin32_SaveList; 112 113 return Subtarget.isPPC64() ? CSR_SVR464_SaveList : CSR_SVR432_SaveList; 114 } 115 116 const unsigned* 117 PPCRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const { 118 if (Subtarget.isDarwinABI()) 119 return Subtarget.isPPC64() ? CSR_Darwin64_RegMask : 120 CSR_Darwin32_RegMask; 121 122 return Subtarget.isPPC64() ? CSR_SVR464_RegMask : CSR_SVR432_RegMask; 123 } 124 125 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 126 BitVector Reserved(getNumRegs()); 127 const PPCFrameLowering *PPCFI = 128 static_cast<const PPCFrameLowering*>(MF.getTarget().getFrameLowering()); 129 130 Reserved.set(PPC::R0); 131 Reserved.set(PPC::R1); 132 Reserved.set(PPC::LR); 133 Reserved.set(PPC::LR8); 134 Reserved.set(PPC::RM); 135 136 // The SVR4 ABI reserves r2 and r13 137 if (Subtarget.isSVR4ABI()) { 138 Reserved.set(PPC::R2); // System-reserved register 139 Reserved.set(PPC::R13); // Small Data Area pointer register 140 } 141 // Reserve R2 on Darwin to hack around the problem of save/restore of CR 142 // when the stack frame is too big to address directly; we need two regs. 143 // This is a hack. 144 if (Subtarget.isDarwinABI()) { 145 Reserved.set(PPC::R2); 146 } 147 148 // On PPC64, r13 is the thread pointer. Never allocate this register. 149 // Note that this is over conservative, as it also prevents allocation of R31 150 // when the FP is not needed. 151 if (Subtarget.isPPC64()) { 152 Reserved.set(PPC::R13); 153 Reserved.set(PPC::R31); 154 155 Reserved.set(PPC::X0); 156 Reserved.set(PPC::X1); 157 Reserved.set(PPC::X13); 158 Reserved.set(PPC::X31); 159 160 // The 64-bit SVR4 ABI reserves r2 for the TOC pointer. 161 if (Subtarget.isSVR4ABI()) { 162 Reserved.set(PPC::X2); 163 } 164 // Reserve X2 on Darwin to hack around the problem of save/restore of CR 165 // when the stack frame is too big to address directly; we need two regs. 166 // This is a hack. 167 if (Subtarget.isDarwinABI()) { 168 Reserved.set(PPC::X2); 169 } 170 } 171 172 if (PPCFI->needsFP(MF)) 173 Reserved.set(PPC::R31); 174 175 return Reserved; 176 } 177 178 unsigned 179 PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 180 MachineFunction &MF) const { 181 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 182 const unsigned DefaultSafety = 1; 183 184 switch (RC->getID()) { 185 default: 186 return 0; 187 case PPC::G8RCRegClassID: 188 case PPC::GPRCRegClassID: { 189 unsigned FP = TFI->hasFP(MF) ? 1 : 0; 190 return 32 - FP - DefaultSafety; 191 } 192 case PPC::F8RCRegClassID: 193 case PPC::F4RCRegClassID: 194 case PPC::VRRCRegClassID: 195 return 32 - DefaultSafety; 196 case PPC::CRRCRegClassID: 197 return 8 - DefaultSafety; 198 } 199 } 200 201 //===----------------------------------------------------------------------===// 202 // Stack Frame Processing methods 203 //===----------------------------------------------------------------------===// 204 205 void PPCRegisterInfo:: 206 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 207 MachineBasicBlock::iterator I) const { 208 if (MF.getTarget().Options.GuaranteedTailCallOpt && 209 I->getOpcode() == PPC::ADJCALLSTACKUP) { 210 // Add (actually subtract) back the amount the callee popped on return. 211 if (int CalleeAmt = I->getOperand(1).getImm()) { 212 bool is64Bit = Subtarget.isPPC64(); 213 CalleeAmt *= -1; 214 unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1; 215 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0; 216 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI; 217 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4; 218 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS; 219 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI; 220 MachineInstr *MI = I; 221 DebugLoc dl = MI->getDebugLoc(); 222 223 if (isInt<16>(CalleeAmt)) { 224 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg) 225 .addReg(StackReg, RegState::Kill) 226 .addImm(CalleeAmt); 227 } else { 228 MachineBasicBlock::iterator MBBI = I; 229 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) 230 .addImm(CalleeAmt >> 16); 231 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) 232 .addReg(TmpReg, RegState::Kill) 233 .addImm(CalleeAmt & 0xFFFF); 234 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg) 235 .addReg(StackReg, RegState::Kill) 236 .addReg(TmpReg); 237 } 238 } 239 } 240 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions. 241 MBB.erase(I); 242 } 243 244 /// findScratchRegister - Find a 'free' PPC register. Try for a call-clobbered 245 /// register first and then a spilled callee-saved register if that fails. 246 static 247 unsigned findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS, 248 const TargetRegisterClass *RC, int SPAdj) { 249 assert(RS && "Register scavenging must be on"); 250 unsigned Reg = RS->FindUnusedReg(RC); 251 // FIXME: move ARM callee-saved reg scan to target independent code, then 252 // search for already spilled CS register here. 253 if (Reg == 0) 254 Reg = RS->scavengeRegister(RC, II, SPAdj); 255 return Reg; 256 } 257 258 /// lowerDynamicAlloc - Generate the code for allocating an object in the 259 /// current frame. The sequence of code with be in the general form 260 /// 261 /// addi R0, SP, \#frameSize ; get the address of the previous frame 262 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size 263 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation 264 /// 265 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II, 266 int SPAdj, RegScavenger *RS) const { 267 // Get the instruction. 268 MachineInstr &MI = *II; 269 // Get the instruction's basic block. 270 MachineBasicBlock &MBB = *MI.getParent(); 271 // Get the basic block's function. 272 MachineFunction &MF = *MBB.getParent(); 273 // Get the frame info. 274 MachineFrameInfo *MFI = MF.getFrameInfo(); 275 // Determine whether 64-bit pointers are used. 276 bool LP64 = Subtarget.isPPC64(); 277 DebugLoc dl = MI.getDebugLoc(); 278 279 // Get the maximum call stack size. 280 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 281 // Get the total frame size. 282 unsigned FrameSize = MFI->getStackSize(); 283 284 // Get stack alignments. 285 unsigned TargetAlign = MF.getTarget().getFrameLowering()->getStackAlignment(); 286 unsigned MaxAlign = MFI->getMaxAlignment(); 287 if (MaxAlign > TargetAlign) 288 report_fatal_error("Dynamic alloca with large aligns not supported"); 289 290 // Determine the previous frame's address. If FrameSize can't be 291 // represented as 16 bits or we need special alignment, then we load the 292 // previous frame's address from 0(SP). Why not do an addis of the hi? 293 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. 294 // Constructing the constant and adding would take 3 instructions. 295 // Fortunately, a frame greater than 32K is rare. 296 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 297 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 298 const TargetRegisterClass *RC = LP64 ? G8RC : GPRC; 299 300 // FIXME (64-bit): Use "findScratchRegister" 301 unsigned Reg; 302 if (requiresRegisterScavenging(MF)) 303 Reg = findScratchRegister(II, RS, RC, SPAdj); 304 else 305 Reg = PPC::R0; 306 307 if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) { 308 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) 309 .addReg(PPC::R31) 310 .addImm(FrameSize); 311 } else if (LP64) { 312 if (requiresRegisterScavenging(MF)) // FIXME (64-bit): Use "true" part. 313 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg) 314 .addImm(0) 315 .addReg(PPC::X1); 316 else 317 BuildMI(MBB, II, dl, TII.get(PPC::LD), PPC::X0) 318 .addImm(0) 319 .addReg(PPC::X1); 320 } else { 321 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) 322 .addImm(0) 323 .addReg(PPC::R1); 324 } 325 326 // Grow the stack and update the stack pointer link, then determine the 327 // address of new allocated space. 328 if (LP64) { 329 if (requiresRegisterScavenging(MF)) // FIXME (64-bit): Use "true" part. 330 BuildMI(MBB, II, dl, TII.get(PPC::STDUX)) 331 .addReg(Reg, RegState::Kill) 332 .addReg(PPC::X1, RegState::Define) 333 .addReg(MI.getOperand(1).getReg()); 334 else 335 BuildMI(MBB, II, dl, TII.get(PPC::STDUX)) 336 .addReg(PPC::X0, RegState::Kill) 337 .addReg(PPC::X1, RegState::Define) 338 .addReg(MI.getOperand(1).getReg()); 339 340 if (!MI.getOperand(1).isKill()) 341 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 342 .addReg(PPC::X1) 343 .addImm(maxCallFrameSize); 344 else 345 // Implicitly kill the register. 346 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 347 .addReg(PPC::X1) 348 .addImm(maxCallFrameSize) 349 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill); 350 } else { 351 BuildMI(MBB, II, dl, TII.get(PPC::STWUX)) 352 .addReg(Reg, RegState::Kill) 353 .addReg(PPC::R1, RegState::Define) 354 .addReg(MI.getOperand(1).getReg()); 355 356 if (!MI.getOperand(1).isKill()) 357 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 358 .addReg(PPC::R1) 359 .addImm(maxCallFrameSize); 360 else 361 // Implicitly kill the register. 362 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 363 .addReg(PPC::R1) 364 .addImm(maxCallFrameSize) 365 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill); 366 } 367 368 // Discard the DYNALLOC instruction. 369 MBB.erase(II); 370 } 371 372 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of 373 /// reserving a whole register (R0), we scrounge for one here. This generates 374 /// code like this: 375 /// 376 /// mfcr rA ; Move the conditional register into GPR rA. 377 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot. 378 /// stw rA, FI ; Store rA to the frame. 379 /// 380 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, 381 unsigned FrameIndex, int SPAdj, 382 RegScavenger *RS) const { 383 // Get the instruction. 384 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset> 385 // Get the instruction's basic block. 386 MachineBasicBlock &MBB = *MI.getParent(); 387 DebugLoc dl = MI.getDebugLoc(); 388 389 // FIXME: Once LLVM supports creating virtual registers here, or the register 390 // scavenger can return multiple registers, stop using reserved registers 391 // here. 392 (void) SPAdj; 393 (void) RS; 394 395 bool LP64 = Subtarget.isPPC64(); 396 unsigned Reg = Subtarget.isDarwinABI() ? (LP64 ? PPC::X2 : PPC::R2) : 397 (LP64 ? PPC::X0 : PPC::R0); 398 unsigned SrcReg = MI.getOperand(0).getReg(); 399 400 // We need to store the CR in the low 4-bits of the saved value. First, issue 401 // an MFCRpsued to save all of the CRBits and, if needed, kill the SrcReg. 402 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFCR8pseud : PPC::MFCRpseud), Reg) 403 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 404 405 // If the saved register wasn't CR0, shift the bits left so that they are in 406 // CR0's slot. 407 if (SrcReg != PPC::CR0) 408 // rlwinm rA, rA, ShiftBits, 0, 31. 409 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 410 .addReg(Reg, RegState::Kill) 411 .addImm(getPPCRegisterNumbering(SrcReg) * 4) 412 .addImm(0) 413 .addImm(31); 414 415 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW)) 416 .addReg(Reg, getKillRegState(MI.getOperand(1).getImm())), 417 FrameIndex); 418 419 // Discard the pseudo instruction. 420 MBB.erase(II); 421 } 422 423 void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II, 424 unsigned FrameIndex, int SPAdj, 425 RegScavenger *RS) const { 426 // Get the instruction. 427 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset> 428 // Get the instruction's basic block. 429 MachineBasicBlock &MBB = *MI.getParent(); 430 DebugLoc dl = MI.getDebugLoc(); 431 432 // FIXME: Once LLVM supports creating virtual registers here, or the register 433 // scavenger can return multiple registers, stop using reserved registers 434 // here. 435 (void) SPAdj; 436 (void) RS; 437 438 bool LP64 = Subtarget.isPPC64(); 439 unsigned Reg = Subtarget.isDarwinABI() ? (LP64 ? PPC::X2 : PPC::R2) : 440 (LP64 ? PPC::X0 : PPC::R0); 441 unsigned DestReg = MI.getOperand(0).getReg(); 442 assert(MI.definesRegister(DestReg) && 443 "RESTORE_CR does not define its destination"); 444 445 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), 446 Reg), FrameIndex); 447 448 // If the reloaded register isn't CR0, shift the bits right so that they are 449 // in the right CR's slot. 450 if (DestReg != PPC::CR0) { 451 unsigned ShiftBits = getPPCRegisterNumbering(DestReg)*4; 452 // rlwinm r11, r11, 32-ShiftBits, 0, 31. 453 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 454 .addReg(Reg).addImm(32-ShiftBits).addImm(0) 455 .addImm(31); 456 } 457 458 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTCRF8 : PPC::MTCRF), DestReg) 459 .addReg(Reg); 460 461 // Discard the pseudo instruction. 462 MBB.erase(II); 463 } 464 465 void 466 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 467 int SPAdj, RegScavenger *RS) const { 468 assert(SPAdj == 0 && "Unexpected"); 469 470 // Get the instruction. 471 MachineInstr &MI = *II; 472 // Get the instruction's basic block. 473 MachineBasicBlock &MBB = *MI.getParent(); 474 // Get the basic block's function. 475 MachineFunction &MF = *MBB.getParent(); 476 // Get the frame info. 477 MachineFrameInfo *MFI = MF.getFrameInfo(); 478 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 479 DebugLoc dl = MI.getDebugLoc(); 480 481 // Find out which operand is the frame index. 482 unsigned FIOperandNo = 0; 483 while (!MI.getOperand(FIOperandNo).isFI()) { 484 ++FIOperandNo; 485 assert(FIOperandNo != MI.getNumOperands() && 486 "Instr doesn't have FrameIndex operand!"); 487 } 488 // Take into account whether it's an add or mem instruction 489 unsigned OffsetOperandNo = (FIOperandNo == 2) ? 1 : 2; 490 if (MI.isInlineAsm()) 491 OffsetOperandNo = FIOperandNo-1; 492 493 // Get the frame index. 494 int FrameIndex = MI.getOperand(FIOperandNo).getIndex(); 495 496 // Get the frame pointer save index. Users of this index are primarily 497 // DYNALLOC instructions. 498 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 499 int FPSI = FI->getFramePointerSaveIndex(); 500 // Get the instruction opcode. 501 unsigned OpC = MI.getOpcode(); 502 503 // Special case for dynamic alloca. 504 if (FPSI && FrameIndex == FPSI && 505 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { 506 lowerDynamicAlloc(II, SPAdj, RS); 507 return; 508 } 509 510 // Special case for pseudo-ops SPILL_CR and RESTORE_CR. 511 if (requiresRegisterScavenging(MF)) { 512 if (OpC == PPC::SPILL_CR) { 513 lowerCRSpilling(II, FrameIndex, SPAdj, RS); 514 return; 515 } else if (OpC == PPC::RESTORE_CR) { 516 lowerCRRestore(II, FrameIndex, SPAdj, RS); 517 return; 518 } 519 } 520 521 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 522 523 bool is64Bit = Subtarget.isPPC64(); 524 MI.getOperand(FIOperandNo).ChangeToRegister(TFI->hasFP(MF) ? 525 (is64Bit ? PPC::X31 : PPC::R31) : 526 (is64Bit ? PPC::X1 : PPC::R1), 527 false); 528 529 // Figure out if the offset in the instruction is shifted right two bits. This 530 // is true for instructions like "STD", which the machine implicitly adds two 531 // low zeros to. 532 bool isIXAddr = false; 533 switch (OpC) { 534 case PPC::LWA: 535 case PPC::LD: 536 case PPC::STD: 537 case PPC::STD_32: 538 isIXAddr = true; 539 break; 540 } 541 542 // Now add the frame object offset to the offset from r1. 543 int Offset = MFI->getObjectOffset(FrameIndex); 544 if (!isIXAddr) 545 Offset += MI.getOperand(OffsetOperandNo).getImm(); 546 else 547 Offset += MI.getOperand(OffsetOperandNo).getImm() << 2; 548 549 // If we're not using a Frame Pointer that has been set to the value of the 550 // SP before having the stack size subtracted from it, then add the stack size 551 // to Offset to get the correct offset. 552 // Naked functions have stack size 0, although getStackSize may not reflect that 553 // because we didn't call all the pieces that compute it for naked functions. 554 if (!MF.getFunction()->hasFnAttr(Attribute::Naked)) 555 Offset += MFI->getStackSize(); 556 557 // If we can, encode the offset directly into the instruction. If this is a 558 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If 559 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits 560 // clear can be encoded. This is extremely uncommon, because normally you 561 // only "std" to a stack slot that is at least 4-byte aligned, but it can 562 // happen in invalid code. 563 if (OpC == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm 564 (isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0))) { 565 if (isIXAddr) 566 Offset >>= 2; // The actual encoded value has the low two bits zero. 567 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 568 return; 569 } 570 571 // The offset doesn't fit into a single register, scavenge one to build the 572 // offset in. 573 574 unsigned SReg; 575 if (requiresRegisterScavenging(MF)) { 576 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 577 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 578 SReg = findScratchRegister(II, RS, is64Bit ? G8RC : GPRC, SPAdj); 579 } else 580 SReg = is64Bit ? PPC::X0 : PPC::R0; 581 582 // Insert a set of rA with the full offset value before the ld, st, or add 583 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SReg) 584 .addImm(Offset >> 16); 585 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg) 586 .addReg(SReg, RegState::Kill) 587 .addImm(Offset); 588 589 // Convert into indexed form of the instruction: 590 // 591 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 592 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 593 unsigned OperandBase; 594 595 if (OpC != TargetOpcode::INLINEASM) { 596 assert(ImmToIdxMap.count(OpC) && 597 "No indexed form of load or store available!"); 598 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; 599 MI.setDesc(TII.get(NewOpcode)); 600 OperandBase = 1; 601 } else { 602 OperandBase = OffsetOperandNo; 603 } 604 605 unsigned StackReg = MI.getOperand(FIOperandNo).getReg(); 606 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false); 607 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true); 608 } 609 610 unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 611 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 612 613 if (!Subtarget.isPPC64()) 614 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1; 615 else 616 return TFI->hasFP(MF) ? PPC::X31 : PPC::X1; 617 } 618 619 unsigned PPCRegisterInfo::getEHExceptionRegister() const { 620 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3; 621 } 622 623 unsigned PPCRegisterInfo::getEHHandlerRegister() const { 624 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4; 625 } 626