1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file was developed by the LLVM research group and is distributed under 6 // the University of Illinois Open Source License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the MRegisterInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #define DEBUG_TYPE "reginfo" 15 #include "PPC.h" 16 #include "PPCInstrBuilder.h" 17 #include "PPCRegisterInfo.h" 18 #include "llvm/Constants.h" 19 #include "llvm/Type.h" 20 #include "llvm/CodeGen/ValueTypes.h" 21 #include "llvm/CodeGen/MachineInstrBuilder.h" 22 #include "llvm/CodeGen/MachineFunction.h" 23 #include "llvm/CodeGen/MachineFrameInfo.h" 24 #include "llvm/Target/TargetFrameInfo.h" 25 #include "llvm/Target/TargetMachine.h" 26 #include "llvm/Target/TargetOptions.h" 27 #include "llvm/Support/CommandLine.h" 28 #include "llvm/Support/Debug.h" 29 #include "llvm/Support/MathExtras.h" 30 #include "llvm/ADT/STLExtras.h" 31 #include <cstdlib> 32 #include <iostream> 33 using namespace llvm; 34 35 PPCRegisterInfo::PPCRegisterInfo() 36 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP) { 37 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 38 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 39 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 40 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 41 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 42 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 43 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 44 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 45 } 46 47 void 48 PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 49 MachineBasicBlock::iterator MI, 50 unsigned SrcReg, int FrameIdx, 51 const TargetRegisterClass *RC) const { 52 if (SrcReg == PPC::LR) { 53 // FIXME: this spills LR immediately to memory in one step. To do this, we 54 // use R11, which we know cannot be used in the prolog/epilog. This is a 55 // hack. 56 BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11); 57 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx); 58 } else if (RC == PPC::CRRCRegisterClass) { 59 BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R11); 60 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx); 61 } else if (RC == PPC::GPRCRegisterClass) { 62 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(SrcReg),FrameIdx); 63 } else if (RC == PPC::G8RCRegisterClass) { 64 addFrameReference(BuildMI(MBB, MI, PPC::STD, 3).addReg(SrcReg),FrameIdx); 65 } else if (RC == PPC::F8RCRegisterClass) { 66 addFrameReference(BuildMI(MBB, MI, PPC::STFD, 3).addReg(SrcReg),FrameIdx); 67 } else if (RC == PPC::F4RCRegisterClass) { 68 addFrameReference(BuildMI(MBB, MI, PPC::STFS, 3).addReg(SrcReg),FrameIdx); 69 } else if (RC == PPC::VRRCRegisterClass) { 70 // We don't have indexed addressing for vector loads. Emit: 71 // R11 = ADDI FI# 72 // Dest = LVX R0, R11 73 // 74 // FIXME: We use R0 here, because it isn't available for RA. 75 addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0); 76 BuildMI(MBB, MI, PPC::STVX, 3) 77 .addReg(SrcReg).addReg(PPC::R0).addReg(PPC::R0); 78 } else { 79 assert(0 && "Unknown regclass!"); 80 abort(); 81 } 82 } 83 84 void 85 PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 86 MachineBasicBlock::iterator MI, 87 unsigned DestReg, int FrameIdx, 88 const TargetRegisterClass *RC) const { 89 if (DestReg == PPC::LR) { 90 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx); 91 BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11); 92 } else if (RC == PPC::CRRCRegisterClass) { 93 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx); 94 BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R11); 95 } else if (RC == PPC::GPRCRegisterClass) { 96 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, DestReg), FrameIdx); 97 } else if (RC == PPC::G8RCRegisterClass) { 98 addFrameReference(BuildMI(MBB, MI, PPC::LD, 2, DestReg), FrameIdx); 99 } else if (RC == PPC::F8RCRegisterClass) { 100 addFrameReference(BuildMI(MBB, MI, PPC::LFD, 2, DestReg), FrameIdx); 101 } else if (RC == PPC::F4RCRegisterClass) { 102 addFrameReference(BuildMI(MBB, MI, PPC::LFS, 2, DestReg), FrameIdx); 103 } else if (RC == PPC::VRRCRegisterClass) { 104 // We don't have indexed addressing for vector loads. Emit: 105 // R11 = ADDI FI# 106 // Dest = LVX R0, R11 107 // 108 // FIXME: We use R0 here, because it isn't available for RA. 109 addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0); 110 BuildMI(MBB, MI, PPC::LVX, 2, DestReg).addReg(PPC::R0).addReg(PPC::R0); 111 } else { 112 assert(0 && "Unknown regclass!"); 113 abort(); 114 } 115 } 116 117 void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, 118 MachineBasicBlock::iterator MI, 119 unsigned DestReg, unsigned SrcReg, 120 const TargetRegisterClass *RC) const { 121 if (RC == PPC::GPRCRegisterClass) { 122 BuildMI(MBB, MI, PPC::OR4, 2, DestReg).addReg(SrcReg).addReg(SrcReg); 123 } else if (RC == PPC::G8RCRegisterClass) { 124 BuildMI(MBB, MI, PPC::OR8, 2, DestReg).addReg(SrcReg).addReg(SrcReg); 125 } else if (RC == PPC::F4RCRegisterClass) { 126 BuildMI(MBB, MI, PPC::FMRS, 1, DestReg).addReg(SrcReg); 127 } else if (RC == PPC::F8RCRegisterClass) { 128 BuildMI(MBB, MI, PPC::FMRD, 1, DestReg).addReg(SrcReg); 129 } else if (RC == PPC::CRRCRegisterClass) { 130 BuildMI(MBB, MI, PPC::MCRF, 1, DestReg).addReg(SrcReg); 131 } else if (RC == PPC::VRRCRegisterClass) { 132 BuildMI(MBB, MI, PPC::VOR, 2, DestReg).addReg(SrcReg).addReg(SrcReg); 133 } else { 134 std::cerr << "Attempt to copy register that is not GPR or FPR"; 135 abort(); 136 } 137 } 138 139 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into 140 /// copy instructions, turning them into load/store instructions. 141 MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI, 142 unsigned OpNum, 143 int FrameIndex) const { 144 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because 145 // it takes more than one instruction to store it. 146 unsigned Opc = MI->getOpcode(); 147 148 if ((Opc == PPC::OR4 && 149 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { 150 if (OpNum == 0) { // move -> store 151 unsigned InReg = MI->getOperand(1).getReg(); 152 return addFrameReference(BuildMI(PPC::STW, 153 3).addReg(InReg), FrameIndex); 154 } else { // move -> load 155 unsigned OutReg = MI->getOperand(0).getReg(); 156 return addFrameReference(BuildMI(PPC::LWZ, 2, OutReg), FrameIndex); 157 } 158 } else if ((Opc == PPC::OR8 && 159 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { 160 if (OpNum == 0) { // move -> store 161 unsigned InReg = MI->getOperand(1).getReg(); 162 return addFrameReference(BuildMI(PPC::STD, 163 3).addReg(InReg), FrameIndex); 164 } else { // move -> load 165 unsigned OutReg = MI->getOperand(0).getReg(); 166 return addFrameReference(BuildMI(PPC::LD, 2, OutReg), FrameIndex); 167 } 168 } else if (Opc == PPC::FMRD) { 169 if (OpNum == 0) { // move -> store 170 unsigned InReg = MI->getOperand(1).getReg(); 171 return addFrameReference(BuildMI(PPC::STFD, 172 3).addReg(InReg), FrameIndex); 173 } else { // move -> load 174 unsigned OutReg = MI->getOperand(0).getReg(); 175 return addFrameReference(BuildMI(PPC::LFD, 2, OutReg), FrameIndex); 176 } 177 } else if (Opc == PPC::FMRS) { 178 if (OpNum == 0) { // move -> store 179 unsigned InReg = MI->getOperand(1).getReg(); 180 return addFrameReference(BuildMI(PPC::STFS, 181 3).addReg(InReg), FrameIndex); 182 } else { // move -> load 183 unsigned OutReg = MI->getOperand(0).getReg(); 184 return addFrameReference(BuildMI(PPC::LFS, 2, OutReg), FrameIndex); 185 } 186 } 187 return 0; 188 } 189 190 //===----------------------------------------------------------------------===// 191 // Stack Frame Processing methods 192 //===----------------------------------------------------------------------===// 193 194 // hasFP - Return true if the specified function should have a dedicated frame 195 // pointer register. This is true if the function has variable sized allocas or 196 // if frame pointer elimination is disabled. 197 // 198 static bool hasFP(MachineFunction &MF) { 199 return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects(); 200 } 201 202 void PPCRegisterInfo:: 203 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 204 MachineBasicBlock::iterator I) const { 205 if (hasFP(MF)) { 206 // If we have a frame pointer, convert as follows: 207 // ADJCALLSTACKDOWN -> addi, r1, r1, -amount 208 // ADJCALLSTACKUP -> addi, r1, r1, amount 209 MachineInstr *Old = I; 210 unsigned Amount = Old->getOperand(0).getImmedValue(); 211 if (Amount != 0) { 212 // We need to keep the stack aligned properly. To do this, we round the 213 // amount of space needed for the outgoing arguments up to the next 214 // alignment boundary. 215 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 216 Amount = (Amount+Align-1)/Align*Align; 217 218 // Replace the pseudo instruction with a new instruction... 219 if (Old->getOpcode() == PPC::ADJCALLSTACKDOWN) { 220 BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addSImm(-Amount); 221 } else { 222 assert(Old->getOpcode() == PPC::ADJCALLSTACKUP); 223 BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addSImm(Amount); 224 } 225 } 226 } 227 MBB.erase(I); 228 } 229 230 void 231 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { 232 unsigned i = 0; 233 MachineInstr &MI = *II; 234 MachineBasicBlock &MBB = *MI.getParent(); 235 MachineFunction &MF = *MBB.getParent(); 236 237 while (!MI.getOperand(i).isFrameIndex()) { 238 ++i; 239 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 240 } 241 242 int FrameIndex = MI.getOperand(i).getFrameIndex(); 243 244 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 245 MI.SetMachineOperandReg(i, hasFP(MF) ? PPC::R31 : PPC::R1); 246 247 // Take into account whether it's an add or mem instruction 248 unsigned OffIdx = (i == 2) ? 1 : 2; 249 250 // Now add the frame object offset to the offset from r1. 251 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + 252 MI.getOperand(OffIdx).getImmedValue(); 253 254 // If we're not using a Frame Pointer that has been set to the value of the 255 // SP before having the stack size subtracted from it, then add the stack size 256 // to Offset to get the correct offset. 257 Offset += MF.getFrameInfo()->getStackSize(); 258 259 if (Offset > 32767 || Offset < -32768) { 260 // Insert a set of r0 with the full offset value before the ld, st, or add 261 MachineBasicBlock *MBB = MI.getParent(); 262 BuildMI(*MBB, II, PPC::LIS, 1, PPC::R0).addSImm(Offset >> 16); 263 BuildMI(*MBB, II, PPC::ORI, 2, PPC::R0).addReg(PPC::R0).addImm(Offset); 264 265 // convert into indexed form of the instruction 266 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 267 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 268 assert(ImmToIdxMap.count(MI.getOpcode()) && 269 "No indexed form of load or store available!"); 270 unsigned NewOpcode = ImmToIdxMap.find(MI.getOpcode())->second; 271 MI.setOpcode(NewOpcode); 272 MI.SetMachineOperandReg(1, MI.getOperand(i).getReg()); 273 MI.SetMachineOperandReg(2, PPC::R0); 274 } else { 275 switch (MI.getOpcode()) { 276 case PPC::LWA: 277 case PPC::LD: 278 case PPC::STD: 279 case PPC::STDU: 280 assert((Offset & 3) == 0 && "Invalid frame offset!"); 281 Offset >>= 2; // The actual encoded value has the low two bits zero. 282 break; 283 } 284 MI.SetMachineOperandConst(OffIdx, MachineOperand::MO_SignExtendedImmed, 285 Offset); 286 } 287 } 288 289 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the 290 // instruction selector. Based on the vector registers that have been used, 291 // transform this into the appropriate ORI instruction. 292 static void HandleVRSaveUpdate(MachineInstr *MI, const bool *UsedRegs) { 293 unsigned UsedRegMask = 0; 294 #define HANDLEREG(N) if (UsedRegs[PPC::V##N]) UsedRegMask |= 1 << (31-N) 295 HANDLEREG( 0); HANDLEREG( 1); HANDLEREG( 2); HANDLEREG( 3); 296 HANDLEREG( 4); HANDLEREG( 5); HANDLEREG( 6); HANDLEREG( 7); 297 HANDLEREG( 8); HANDLEREG( 9); HANDLEREG(10); HANDLEREG(11); 298 HANDLEREG(12); HANDLEREG(13); HANDLEREG(14); HANDLEREG(15); 299 HANDLEREG(16); HANDLEREG(17); HANDLEREG(18); HANDLEREG(19); 300 HANDLEREG(20); HANDLEREG(21); HANDLEREG(22); HANDLEREG(23); 301 HANDLEREG(24); HANDLEREG(25); HANDLEREG(26); HANDLEREG(27); 302 HANDLEREG(28); HANDLEREG(29); HANDLEREG(30); HANDLEREG(31); 303 #undef HANDLEREG 304 unsigned SrcReg = MI->getOperand(1).getReg(); 305 unsigned DstReg = MI->getOperand(0).getReg(); 306 // If no registers are used, turn this into a copy. 307 if (UsedRegMask == 0) { 308 if (SrcReg != DstReg) 309 BuildMI(*MI->getParent(), MI, PPC::OR4, 2, DstReg) 310 .addReg(SrcReg).addReg(SrcReg); 311 } else if ((UsedRegMask & 0xFFFF) == UsedRegMask) { 312 BuildMI(*MI->getParent(), MI, PPC::ORI, 2, DstReg) 313 .addReg(SrcReg).addImm(UsedRegMask); 314 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { 315 BuildMI(*MI->getParent(), MI, PPC::ORIS, 2, DstReg) 316 .addReg(SrcReg).addImm(UsedRegMask >> 16); 317 } else { 318 BuildMI(*MI->getParent(), MI, PPC::ORIS, 2, DstReg) 319 .addReg(SrcReg).addImm(UsedRegMask >> 16); 320 BuildMI(*MI->getParent(), MI, PPC::ORI, 2, DstReg) 321 .addReg(DstReg).addImm(UsedRegMask & 0xFFFF); 322 } 323 324 // Remove the old UPDATE_VRSAVE instruction. 325 MI->getParent()->erase(MI); 326 } 327 328 329 void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const { 330 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB 331 MachineBasicBlock::iterator MBBI = MBB.begin(); 332 MachineFrameInfo *MFI = MF.getFrameInfo(); 333 334 // Scan the first few instructions of the prolog, looking for an UPDATE_VRSAVE 335 // instruction. If we find it, process it. 336 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { 337 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) { 338 HandleVRSaveUpdate(MBBI, MF.getUsedPhysregs()); 339 break; 340 } 341 } 342 343 // Move MBBI back to the beginning of the function. 344 MBBI = MBB.begin(); 345 346 // Get the number of bytes to allocate from the FrameInfo 347 unsigned NumBytes = MFI->getStackSize(); 348 349 // Get the alignments provided by the target, and the maximum alignment 350 // (if any) of the fixed frame objects. 351 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 352 unsigned MaxAlign = MFI->getMaxAlignment(); 353 354 // If we have calls, we cannot use the red zone to store callee save registers 355 // and we must set up a stack frame, so calculate the necessary size here. 356 if (MFI->hasCalls()) { 357 // We reserve argument space for call sites in the function immediately on 358 // entry to the current function. This eliminates the need for add/sub 359 // brackets around call sites. 360 NumBytes += MFI->getMaxCallFrameSize(); 361 } 362 363 // If we are a leaf function, and use up to 224 bytes of stack space, 364 // and don't have a frame pointer, then we do not need to adjust the stack 365 // pointer (we fit in the Red Zone). 366 if ((NumBytes == 0) || (NumBytes <= 224 && !hasFP(MF) && !MFI->hasCalls() && 367 MaxAlign <= TargetAlign)) { 368 MFI->setStackSize(0); 369 return; 370 } 371 372 // Add the size of R1 to NumBytes size for the store of R1 to the bottom 373 // of the stack and round the size to a multiple of the alignment. 374 unsigned Align = std::max(TargetAlign, MaxAlign); 375 unsigned GPRSize = 4; 376 unsigned Size = hasFP(MF) ? GPRSize + GPRSize : GPRSize; 377 NumBytes = (NumBytes+Size+Align-1)/Align*Align; 378 379 // Update frame info to pretend that this is part of the stack... 380 MFI->setStackSize(NumBytes); 381 382 // Adjust stack pointer: r1 -= numbytes. 383 if (NumBytes <= 32768) { 384 BuildMI(MBB, MBBI, PPC::STWU, 3) 385 .addReg(PPC::R1).addSImm(-NumBytes).addReg(PPC::R1); 386 } else { 387 int NegNumbytes = -NumBytes; 388 BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addSImm(NegNumbytes >> 16); 389 BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0) 390 .addReg(PPC::R0).addImm(NegNumbytes & 0xFFFF); 391 BuildMI(MBB, MBBI, PPC::STWUX, 3) 392 .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0); 393 } 394 395 // If there is a preferred stack alignment, align R1 now 396 // FIXME: If this ever matters, this could be made more efficient by folding 397 // this into the code above, so that we don't issue two store+update 398 // instructions. 399 if (MaxAlign > TargetAlign) { 400 assert(isPowerOf2_32(MaxAlign) && MaxAlign < 32767 && "Invalid alignment!"); 401 BuildMI(MBB, MBBI, PPC::RLWINM, 4, PPC::R0) 402 .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31); 403 BuildMI(MBB, MBBI, PPC::SUBFIC, 2,PPC::R0).addReg(PPC::R0).addImm(MaxAlign); 404 BuildMI(MBB, MBBI, PPC::STWUX, 3) 405 .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0); 406 } 407 408 // If there is a frame pointer, copy R1 (SP) into R31 (FP) 409 if (hasFP(MF)) { 410 BuildMI(MBB, MBBI, PPC::STW, 3) 411 .addReg(PPC::R31).addSImm(GPRSize).addReg(PPC::R1); 412 BuildMI(MBB, MBBI, PPC::OR4, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1); 413 } 414 } 415 416 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF, 417 MachineBasicBlock &MBB) const { 418 MachineBasicBlock::iterator MBBI = prior(MBB.end()); 419 assert(MBBI->getOpcode() == PPC::BLR && 420 "Can only insert epilog into returning blocks"); 421 422 // Get the number of bytes allocated from the FrameInfo. 423 unsigned NumBytes = MF.getFrameInfo()->getStackSize(); 424 unsigned GPRSize = 4; 425 426 if (NumBytes != 0) { 427 // If this function has a frame pointer, load the saved stack pointer from 428 // its stack slot. 429 if (hasFP(MF)) { 430 BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R31) 431 .addSImm(GPRSize).addReg(PPC::R31); 432 } 433 434 // The loaded (or persistent) stack pointer value is offseted by the 'stwu' 435 // on entry to the function. Add this offset back now. 436 if (NumBytes < 32768) { 437 BuildMI(MBB, MBBI, PPC::ADDI, 2, PPC::R1) 438 .addReg(PPC::R1).addSImm(NumBytes); 439 } else { 440 BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addSImm(NumBytes >> 16); 441 BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0) 442 .addReg(PPC::R0).addImm(NumBytes & 0xFFFF); 443 BuildMI(MBB, MBBI, PPC::ADD4, 2, PPC::R1) 444 .addReg(PPC::R0).addReg(PPC::R1); 445 } 446 } 447 } 448 449 #include "PPCGenRegisterInfo.inc" 450 451