1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the TargetRegisterInfo 11 // class. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #define DEBUG_TYPE "reginfo" 16 #include "PPC.h" 17 #include "PPCInstrBuilder.h" 18 #include "PPCMachineFunctionInfo.h" 19 #include "PPCRegisterInfo.h" 20 #include "PPCFrameInfo.h" 21 #include "PPCSubtarget.h" 22 #include "llvm/CallingConv.h" 23 #include "llvm/Constants.h" 24 #include "llvm/Function.h" 25 #include "llvm/Type.h" 26 #include "llvm/CodeGen/ValueTypes.h" 27 #include "llvm/CodeGen/MachineInstrBuilder.h" 28 #include "llvm/CodeGen/MachineModuleInfo.h" 29 #include "llvm/CodeGen/MachineFunction.h" 30 #include "llvm/CodeGen/MachineFrameInfo.h" 31 #include "llvm/CodeGen/MachineLocation.h" 32 #include "llvm/CodeGen/MachineRegisterInfo.h" 33 #include "llvm/CodeGen/RegisterScavenging.h" 34 #include "llvm/Target/TargetFrameInfo.h" 35 #include "llvm/Target/TargetInstrInfo.h" 36 #include "llvm/Target/TargetMachine.h" 37 #include "llvm/Target/TargetOptions.h" 38 #include "llvm/Support/CommandLine.h" 39 #include "llvm/Support/Debug.h" 40 #include "llvm/Support/ErrorHandling.h" 41 #include "llvm/Support/MathExtras.h" 42 #include "llvm/Support/raw_ostream.h" 43 #include "llvm/ADT/BitVector.h" 44 #include "llvm/ADT/STLExtras.h" 45 #include <cstdlib> 46 using namespace llvm; 47 48 // FIXME This disables some code that aligns the stack to a boundary 49 // bigger than the default (16 bytes on Darwin) when there is a stack local 50 // of greater alignment. This does not currently work, because the delta 51 // between old and new stack pointers is added to offsets that reference 52 // incoming parameters after the prolog is generated, and the code that 53 // does that doesn't handle a variable delta. You don't want to do that 54 // anyway; a better approach is to reserve another register that retains 55 // to the incoming stack pointer, and reference parameters relative to that. 56 #define ALIGN_STACK 0 57 58 // FIXME (64-bit): Eventually enable by default. 59 cl::opt<bool> EnablePPC32RS("enable-ppc32-regscavenger", 60 cl::init(false), 61 cl::desc("Enable PPC32 register scavenger"), 62 cl::Hidden); 63 cl::opt<bool> EnablePPC64RS("enable-ppc64-regscavenger", 64 cl::init(false), 65 cl::desc("Enable PPC64 register scavenger"), 66 cl::Hidden); 67 #define EnableRegisterScavenging \ 68 ((EnablePPC32RS && !Subtarget.isPPC64()) || \ 69 (EnablePPC64RS && Subtarget.isPPC64())) 70 71 // FIXME (64-bit): Should be inlined. 72 bool 73 PPCRegisterInfo::requiresRegisterScavenging(const MachineFunction &) const { 74 return EnableRegisterScavenging; 75 } 76 77 /// getRegisterNumbering - Given the enum value for some register, e.g. 78 /// PPC::F14, return the number that it corresponds to (e.g. 14). 79 unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) { 80 using namespace PPC; 81 switch (RegEnum) { 82 case 0: return 0; 83 case R0 : case X0 : case F0 : case V0 : case CR0: case CR0LT: return 0; 84 case R1 : case X1 : case F1 : case V1 : case CR1: case CR0GT: return 1; 85 case R2 : case X2 : case F2 : case V2 : case CR2: case CR0EQ: return 2; 86 case R3 : case X3 : case F3 : case V3 : case CR3: case CR0UN: return 3; 87 case R4 : case X4 : case F4 : case V4 : case CR4: case CR1LT: return 4; 88 case R5 : case X5 : case F5 : case V5 : case CR5: case CR1GT: return 5; 89 case R6 : case X6 : case F6 : case V6 : case CR6: case CR1EQ: return 6; 90 case R7 : case X7 : case F7 : case V7 : case CR7: case CR1UN: return 7; 91 case R8 : case X8 : case F8 : case V8 : case CR2LT: return 8; 92 case R9 : case X9 : case F9 : case V9 : case CR2GT: return 9; 93 case R10: case X10: case F10: case V10: case CR2EQ: return 10; 94 case R11: case X11: case F11: case V11: case CR2UN: return 11; 95 case R12: case X12: case F12: case V12: case CR3LT: return 12; 96 case R13: case X13: case F13: case V13: case CR3GT: return 13; 97 case R14: case X14: case F14: case V14: case CR3EQ: return 14; 98 case R15: case X15: case F15: case V15: case CR3UN: return 15; 99 case R16: case X16: case F16: case V16: case CR4LT: return 16; 100 case R17: case X17: case F17: case V17: case CR4GT: return 17; 101 case R18: case X18: case F18: case V18: case CR4EQ: return 18; 102 case R19: case X19: case F19: case V19: case CR4UN: return 19; 103 case R20: case X20: case F20: case V20: case CR5LT: return 20; 104 case R21: case X21: case F21: case V21: case CR5GT: return 21; 105 case R22: case X22: case F22: case V22: case CR5EQ: return 22; 106 case R23: case X23: case F23: case V23: case CR5UN: return 23; 107 case R24: case X24: case F24: case V24: case CR6LT: return 24; 108 case R25: case X25: case F25: case V25: case CR6GT: return 25; 109 case R26: case X26: case F26: case V26: case CR6EQ: return 26; 110 case R27: case X27: case F27: case V27: case CR6UN: return 27; 111 case R28: case X28: case F28: case V28: case CR7LT: return 28; 112 case R29: case X29: case F29: case V29: case CR7GT: return 29; 113 case R30: case X30: case F30: case V30: case CR7EQ: return 30; 114 case R31: case X31: case F31: case V31: case CR7UN: return 31; 115 default: 116 llvm_unreachable("Unhandled reg in PPCRegisterInfo::getRegisterNumbering!"); 117 } 118 } 119 120 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST, 121 const TargetInstrInfo &tii) 122 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP), 123 Subtarget(ST), TII(tii) { 124 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 125 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 126 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 127 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 128 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 129 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 130 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 131 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 132 133 // 64-bit 134 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8; 135 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8; 136 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8; 137 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX; 138 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32; 139 } 140 141 /// getPointerRegClass - Return the register class to use to hold pointers. 142 /// This is used for addressing modes. 143 const TargetRegisterClass * 144 PPCRegisterInfo::getPointerRegClass(unsigned Kind) const { 145 if (Subtarget.isPPC64()) 146 return &PPC::G8RCRegClass; 147 return &PPC::GPRCRegClass; 148 } 149 150 const unsigned* 151 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 152 // 32-bit Darwin calling convention. 153 static const unsigned Darwin32_CalleeSavedRegs[] = { 154 PPC::R13, PPC::R14, PPC::R15, 155 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 156 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 157 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 158 PPC::R28, PPC::R29, PPC::R30, PPC::R31, 159 160 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 161 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 162 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 163 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 164 PPC::F30, PPC::F31, 165 166 PPC::CR2, PPC::CR3, PPC::CR4, 167 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 168 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 169 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 170 171 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 172 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 173 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 174 175 PPC::LR, 0 176 }; 177 178 // 32-bit SVR4 calling convention. 179 static const unsigned SVR4_CalleeSavedRegs[] = { 180 PPC::R14, PPC::R15, 181 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 182 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 183 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 184 PPC::R28, PPC::R29, PPC::R30, PPC::R31, 185 186 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 187 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 188 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 189 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 190 PPC::F30, PPC::F31, 191 192 PPC::CR2, PPC::CR3, PPC::CR4, 193 194 PPC::VRSAVE, 195 196 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 197 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 198 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 199 200 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 201 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 202 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 203 204 0 205 }; 206 // 64-bit Darwin calling convention. 207 static const unsigned Darwin64_CalleeSavedRegs[] = { 208 PPC::X14, PPC::X15, 209 PPC::X16, PPC::X17, PPC::X18, PPC::X19, 210 PPC::X20, PPC::X21, PPC::X22, PPC::X23, 211 PPC::X24, PPC::X25, PPC::X26, PPC::X27, 212 PPC::X28, PPC::X29, PPC::X30, PPC::X31, 213 214 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 215 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 216 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 217 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 218 PPC::F30, PPC::F31, 219 220 PPC::CR2, PPC::CR3, PPC::CR4, 221 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 222 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 223 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 224 225 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 226 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 227 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 228 229 PPC::LR8, 0 230 }; 231 232 // 64-bit SVR4 calling convention. 233 static const unsigned SVR4_64_CalleeSavedRegs[] = { 234 PPC::X14, PPC::X15, 235 PPC::X16, PPC::X17, PPC::X18, PPC::X19, 236 PPC::X20, PPC::X21, PPC::X22, PPC::X23, 237 PPC::X24, PPC::X25, PPC::X26, PPC::X27, 238 PPC::X28, PPC::X29, PPC::X30, PPC::X31, 239 240 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 241 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 242 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 243 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 244 PPC::F30, PPC::F31, 245 246 PPC::CR2, PPC::CR3, PPC::CR4, 247 248 PPC::VRSAVE, 249 250 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 251 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 252 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 253 254 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 255 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 256 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 257 258 0 259 }; 260 261 if (Subtarget.isDarwinABI()) 262 return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegs : 263 Darwin32_CalleeSavedRegs; 264 265 return Subtarget.isPPC64() ? SVR4_64_CalleeSavedRegs : SVR4_CalleeSavedRegs; 266 } 267 268 const TargetRegisterClass* const* 269 PPCRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const { 270 // 32-bit Darwin calling convention. 271 static const TargetRegisterClass * const Darwin32_CalleeSavedRegClasses[] = { 272 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 273 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 274 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 275 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 276 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 277 278 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 279 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 280 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 281 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 282 &PPC::F8RCRegClass,&PPC::F8RCRegClass, 283 284 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, 285 286 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 287 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 288 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 289 290 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 291 &PPC::CRBITRCRegClass, 292 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 293 &PPC::CRBITRCRegClass, 294 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 295 &PPC::CRBITRCRegClass, 296 297 &PPC::GPRCRegClass, 0 298 }; 299 300 // 32-bit SVR4 calling convention. 301 static const TargetRegisterClass * const SVR4_CalleeSavedRegClasses[] = { 302 &PPC::GPRCRegClass,&PPC::GPRCRegClass, 303 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 304 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 305 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 306 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 307 308 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 309 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 310 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 311 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 312 &PPC::F8RCRegClass,&PPC::F8RCRegClass, 313 314 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, 315 316 &PPC::VRSAVERCRegClass, 317 318 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 319 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 320 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 321 322 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 323 &PPC::CRBITRCRegClass, 324 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 325 &PPC::CRBITRCRegClass, 326 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 327 &PPC::CRBITRCRegClass, 328 329 0 330 }; 331 332 // 64-bit Darwin calling convention. 333 static const TargetRegisterClass * const Darwin64_CalleeSavedRegClasses[] = { 334 &PPC::G8RCRegClass,&PPC::G8RCRegClass, 335 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 336 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 337 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 338 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 339 340 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 341 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 342 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 343 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 344 &PPC::F8RCRegClass,&PPC::F8RCRegClass, 345 346 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, 347 348 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 349 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 350 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 351 352 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 353 &PPC::CRBITRCRegClass, 354 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 355 &PPC::CRBITRCRegClass, 356 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 357 &PPC::CRBITRCRegClass, 358 359 &PPC::G8RCRegClass, 0 360 }; 361 362 // 64-bit SVR4 calling convention. 363 static const TargetRegisterClass * const SVR4_64_CalleeSavedRegClasses[] = { 364 &PPC::G8RCRegClass,&PPC::G8RCRegClass, 365 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 366 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 367 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 368 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 369 370 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 371 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 372 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 373 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 374 &PPC::F8RCRegClass,&PPC::F8RCRegClass, 375 376 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, 377 378 &PPC::VRSAVERCRegClass, 379 380 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 381 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 382 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 383 384 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 385 &PPC::CRBITRCRegClass, 386 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 387 &PPC::CRBITRCRegClass, 388 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass, 389 &PPC::CRBITRCRegClass, 390 391 0 392 }; 393 394 if (Subtarget.isDarwinABI()) 395 return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegClasses : 396 Darwin32_CalleeSavedRegClasses; 397 398 return Subtarget.isPPC64() ? SVR4_64_CalleeSavedRegClasses 399 : SVR4_CalleeSavedRegClasses; 400 } 401 402 // needsFP - Return true if the specified function should have a dedicated frame 403 // pointer register. This is true if the function has variable sized allocas or 404 // if frame pointer elimination is disabled. 405 // 406 static bool needsFP(const MachineFunction &MF) { 407 const MachineFrameInfo *MFI = MF.getFrameInfo(); 408 return NoFramePointerElim || MFI->hasVarSizedObjects() || 409 (PerformTailCallOpt && MF.getInfo<PPCFunctionInfo>()->hasFastCall()); 410 } 411 412 static bool spillsCR(const MachineFunction &MF) { 413 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 414 return FuncInfo->isCRSpilled(); 415 } 416 417 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 418 BitVector Reserved(getNumRegs()); 419 Reserved.set(PPC::R0); 420 Reserved.set(PPC::R1); 421 Reserved.set(PPC::LR); 422 Reserved.set(PPC::LR8); 423 Reserved.set(PPC::RM); 424 425 // The SVR4 ABI reserves r2 and r13 426 if (Subtarget.isSVR4ABI()) { 427 Reserved.set(PPC::R2); // System-reserved register 428 Reserved.set(PPC::R13); // Small Data Area pointer register 429 } 430 431 // On PPC64, r13 is the thread pointer. Never allocate this register. 432 // Note that this is over conservative, as it also prevents allocation of R31 433 // when the FP is not needed. 434 if (Subtarget.isPPC64()) { 435 Reserved.set(PPC::R13); 436 Reserved.set(PPC::R31); 437 438 if (!EnableRegisterScavenging) 439 Reserved.set(PPC::R0); // FIXME (64-bit): Remove 440 441 Reserved.set(PPC::X0); 442 Reserved.set(PPC::X1); 443 Reserved.set(PPC::X13); 444 Reserved.set(PPC::X31); 445 446 // The 64-bit SVR4 ABI reserves r2 for the TOC pointer. 447 if (Subtarget.isSVR4ABI()) { 448 Reserved.set(PPC::X2); 449 } 450 } 451 452 if (needsFP(MF)) 453 Reserved.set(PPC::R31); 454 455 return Reserved; 456 } 457 458 //===----------------------------------------------------------------------===// 459 // Stack Frame Processing methods 460 //===----------------------------------------------------------------------===// 461 462 // hasFP - Return true if the specified function actually has a dedicated frame 463 // pointer register. This is true if the function needs a frame pointer and has 464 // a non-zero stack size. 465 bool PPCRegisterInfo::hasFP(const MachineFunction &MF) const { 466 const MachineFrameInfo *MFI = MF.getFrameInfo(); 467 return MFI->getStackSize() && needsFP(MF); 468 } 469 470 /// MustSaveLR - Return true if this function requires that we save the LR 471 /// register onto the stack in the prolog and restore it in the epilog of the 472 /// function. 473 static bool MustSaveLR(const MachineFunction &MF, unsigned LR) { 474 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>(); 475 476 // We need a save/restore of LR if there is any def of LR (which is 477 // defined by calls, including the PIC setup sequence), or if there is 478 // some use of the LR stack slot (e.g. for builtin_return_address). 479 // (LR comes in 32 and 64 bit versions.) 480 MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR); 481 return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired(); 482 } 483 484 485 486 void PPCRegisterInfo:: 487 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 488 MachineBasicBlock::iterator I) const { 489 if (PerformTailCallOpt && I->getOpcode() == PPC::ADJCALLSTACKUP) { 490 // Add (actually subtract) back the amount the callee popped on return. 491 if (int CalleeAmt = I->getOperand(1).getImm()) { 492 bool is64Bit = Subtarget.isPPC64(); 493 CalleeAmt *= -1; 494 unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1; 495 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0; 496 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI; 497 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4; 498 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS; 499 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI; 500 MachineInstr *MI = I; 501 DebugLoc dl = MI->getDebugLoc(); 502 503 if (isInt16(CalleeAmt)) { 504 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg).addReg(StackReg). 505 addImm(CalleeAmt); 506 } else { 507 MachineBasicBlock::iterator MBBI = I; 508 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) 509 .addImm(CalleeAmt >> 16); 510 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) 511 .addReg(TmpReg, RegState::Kill) 512 .addImm(CalleeAmt & 0xFFFF); 513 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr)) 514 .addReg(StackReg) 515 .addReg(StackReg) 516 .addReg(TmpReg); 517 } 518 } 519 } 520 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions. 521 MBB.erase(I); 522 } 523 524 /// findScratchRegister - Find a 'free' PPC register. Try for a call-clobbered 525 /// register first and then a spilled callee-saved register if that fails. 526 static 527 unsigned findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS, 528 const TargetRegisterClass *RC, int SPAdj) { 529 assert(RS && "Register scavenging must be on"); 530 unsigned Reg = RS->FindUnusedReg(RC); 531 // FIXME: move ARM callee-saved reg scan to target independent code, then 532 // search for already spilled CS register here. 533 if (Reg == 0) 534 Reg = RS->scavengeRegister(RC, II, SPAdj); 535 return Reg; 536 } 537 538 /// lowerDynamicAlloc - Generate the code for allocating an object in the 539 /// current frame. The sequence of code with be in the general form 540 /// 541 /// addi R0, SP, \#frameSize ; get the address of the previous frame 542 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size 543 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation 544 /// 545 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II, 546 int SPAdj, RegScavenger *RS) const { 547 // Get the instruction. 548 MachineInstr &MI = *II; 549 // Get the instruction's basic block. 550 MachineBasicBlock &MBB = *MI.getParent(); 551 // Get the basic block's function. 552 MachineFunction &MF = *MBB.getParent(); 553 // Get the frame info. 554 MachineFrameInfo *MFI = MF.getFrameInfo(); 555 // Determine whether 64-bit pointers are used. 556 bool LP64 = Subtarget.isPPC64(); 557 DebugLoc dl = MI.getDebugLoc(); 558 559 // Get the maximum call stack size. 560 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 561 // Get the total frame size. 562 unsigned FrameSize = MFI->getStackSize(); 563 564 // Get stack alignments. 565 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 566 unsigned MaxAlign = MFI->getMaxAlignment(); 567 assert(MaxAlign <= TargetAlign && 568 "Dynamic alloca with large aligns not supported"); 569 570 // Determine the previous frame's address. If FrameSize can't be 571 // represented as 16 bits or we need special alignment, then we load the 572 // previous frame's address from 0(SP). Why not do an addis of the hi? 573 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. 574 // Constructing the constant and adding would take 3 instructions. 575 // Fortunately, a frame greater than 32K is rare. 576 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 577 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 578 const TargetRegisterClass *RC = LP64 ? G8RC : GPRC; 579 580 // FIXME (64-bit): Use "findScratchRegister" 581 unsigned Reg; 582 if (EnableRegisterScavenging) 583 Reg = findScratchRegister(II, RS, RC, SPAdj); 584 else 585 Reg = PPC::R0; 586 587 if (MaxAlign < TargetAlign && isInt16(FrameSize)) { 588 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) 589 .addReg(PPC::R31) 590 .addImm(FrameSize); 591 } else if (LP64) { 592 if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part. 593 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg) 594 .addImm(0) 595 .addReg(PPC::X1); 596 else 597 BuildMI(MBB, II, dl, TII.get(PPC::LD), PPC::X0) 598 .addImm(0) 599 .addReg(PPC::X1); 600 } else { 601 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) 602 .addImm(0) 603 .addReg(PPC::R1); 604 } 605 606 // Grow the stack and update the stack pointer link, then determine the 607 // address of new allocated space. 608 if (LP64) { 609 if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part. 610 BuildMI(MBB, II, dl, TII.get(PPC::STDUX)) 611 .addReg(Reg, RegState::Kill) 612 .addReg(PPC::X1) 613 .addReg(MI.getOperand(1).getReg()); 614 else 615 BuildMI(MBB, II, dl, TII.get(PPC::STDUX)) 616 .addReg(PPC::X0, RegState::Kill) 617 .addReg(PPC::X1) 618 .addReg(MI.getOperand(1).getReg()); 619 620 if (!MI.getOperand(1).isKill()) 621 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 622 .addReg(PPC::X1) 623 .addImm(maxCallFrameSize); 624 else 625 // Implicitly kill the register. 626 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 627 .addReg(PPC::X1) 628 .addImm(maxCallFrameSize) 629 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill); 630 } else { 631 BuildMI(MBB, II, dl, TII.get(PPC::STWUX)) 632 .addReg(Reg, RegState::Kill) 633 .addReg(PPC::R1) 634 .addReg(MI.getOperand(1).getReg()); 635 636 if (!MI.getOperand(1).isKill()) 637 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 638 .addReg(PPC::R1) 639 .addImm(maxCallFrameSize); 640 else 641 // Implicitly kill the register. 642 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 643 .addReg(PPC::R1) 644 .addImm(maxCallFrameSize) 645 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill); 646 } 647 648 // Discard the DYNALLOC instruction. 649 MBB.erase(II); 650 } 651 652 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of 653 /// reserving a whole register (R0), we scrounge for one here. This generates 654 /// code like this: 655 /// 656 /// mfcr rA ; Move the conditional register into GPR rA. 657 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot. 658 /// stw rA, FI ; Store rA to the frame. 659 /// 660 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, 661 unsigned FrameIndex, int SPAdj, 662 RegScavenger *RS) const { 663 // Get the instruction. 664 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>, <FI> 665 // Get the instruction's basic block. 666 MachineBasicBlock &MBB = *MI.getParent(); 667 DebugLoc dl = MI.getDebugLoc(); 668 669 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 670 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 671 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC; 672 unsigned Reg = findScratchRegister(II, RS, RC, SPAdj); 673 674 // We need to store the CR in the low 4-bits of the saved value. First, issue 675 // an MFCR to save all of the CRBits. Add an implicit kill of the CR. 676 if (!MI.getOperand(0).isKill()) 677 BuildMI(MBB, II, dl, TII.get(PPC::MFCR), Reg); 678 else 679 // Implicitly kill the CR register. 680 BuildMI(MBB, II, dl, TII.get(PPC::MFCR), Reg) 681 .addReg(MI.getOperand(0).getReg(), RegState::ImplicitKill); 682 683 // If the saved register wasn't CR0, shift the bits left so that they are in 684 // CR0's slot. 685 unsigned SrcReg = MI.getOperand(0).getReg(); 686 if (SrcReg != PPC::CR0) 687 // rlwinm rA, rA, ShiftBits, 0, 31. 688 BuildMI(MBB, II, dl, TII.get(PPC::RLWINM), Reg) 689 .addReg(Reg, RegState::Kill) 690 .addImm(PPCRegisterInfo::getRegisterNumbering(SrcReg) * 4) 691 .addImm(0) 692 .addImm(31); 693 694 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::STW)) 695 .addReg(Reg, getKillRegState(MI.getOperand(1).getImm())), 696 FrameIndex); 697 698 // Discard the pseudo instruction. 699 MBB.erase(II); 700 } 701 702 unsigned 703 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 704 int SPAdj, int *Value, 705 RegScavenger *RS) const { 706 assert(SPAdj == 0 && "Unexpected"); 707 708 // Get the instruction. 709 MachineInstr &MI = *II; 710 // Get the instruction's basic block. 711 MachineBasicBlock &MBB = *MI.getParent(); 712 // Get the basic block's function. 713 MachineFunction &MF = *MBB.getParent(); 714 // Get the frame info. 715 MachineFrameInfo *MFI = MF.getFrameInfo(); 716 DebugLoc dl = MI.getDebugLoc(); 717 718 // Find out which operand is the frame index. 719 unsigned FIOperandNo = 0; 720 while (!MI.getOperand(FIOperandNo).isFI()) { 721 ++FIOperandNo; 722 assert(FIOperandNo != MI.getNumOperands() && 723 "Instr doesn't have FrameIndex operand!"); 724 } 725 // Take into account whether it's an add or mem instruction 726 unsigned OffsetOperandNo = (FIOperandNo == 2) ? 1 : 2; 727 if (MI.getOpcode() == TargetInstrInfo::INLINEASM) 728 OffsetOperandNo = FIOperandNo-1; 729 730 // Get the frame index. 731 int FrameIndex = MI.getOperand(FIOperandNo).getIndex(); 732 733 // Get the frame pointer save index. Users of this index are primarily 734 // DYNALLOC instructions. 735 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 736 int FPSI = FI->getFramePointerSaveIndex(); 737 // Get the instruction opcode. 738 unsigned OpC = MI.getOpcode(); 739 740 // Special case for dynamic alloca. 741 if (FPSI && FrameIndex == FPSI && 742 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { 743 lowerDynamicAlloc(II, SPAdj, RS); 744 return 0; 745 } 746 747 // Special case for pseudo-op SPILL_CR. 748 if (EnableRegisterScavenging) // FIXME (64-bit): Enable by default. 749 if (OpC == PPC::SPILL_CR) { 750 lowerCRSpilling(II, FrameIndex, SPAdj, RS); 751 return 0; 752 } 753 754 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 755 MI.getOperand(FIOperandNo).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1, 756 false); 757 758 // Figure out if the offset in the instruction is shifted right two bits. This 759 // is true for instructions like "STD", which the machine implicitly adds two 760 // low zeros to. 761 bool isIXAddr = false; 762 switch (OpC) { 763 case PPC::LWA: 764 case PPC::LD: 765 case PPC::STD: 766 case PPC::STD_32: 767 isIXAddr = true; 768 break; 769 } 770 771 // Now add the frame object offset to the offset from r1. 772 int Offset = MFI->getObjectOffset(FrameIndex); 773 if (!isIXAddr) 774 Offset += MI.getOperand(OffsetOperandNo).getImm(); 775 else 776 Offset += MI.getOperand(OffsetOperandNo).getImm() << 2; 777 778 // If we're not using a Frame Pointer that has been set to the value of the 779 // SP before having the stack size subtracted from it, then add the stack size 780 // to Offset to get the correct offset. 781 Offset += MFI->getStackSize(); 782 783 // If we can, encode the offset directly into the instruction. If this is a 784 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If 785 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits 786 // clear can be encoded. This is extremely uncommon, because normally you 787 // only "std" to a stack slot that is at least 4-byte aligned, but it can 788 // happen in invalid code. 789 if (isInt16(Offset) && (!isIXAddr || (Offset & 3) == 0)) { 790 if (isIXAddr) 791 Offset >>= 2; // The actual encoded value has the low two bits zero. 792 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 793 return 0; 794 } 795 796 // The offset doesn't fit into a single register, scavenge one to build the 797 // offset in. 798 // FIXME: figure out what SPAdj is doing here. 799 800 // FIXME (64-bit): Use "findScratchRegister". 801 unsigned SReg; 802 if (EnableRegisterScavenging) 803 SReg = findScratchRegister(II, RS, &PPC::GPRCRegClass, SPAdj); 804 else 805 SReg = PPC::R0; 806 807 // Insert a set of rA with the full offset value before the ld, st, or add 808 BuildMI(MBB, II, dl, TII.get(PPC::LIS), SReg) 809 .addImm(Offset >> 16); 810 BuildMI(MBB, II, dl, TII.get(PPC::ORI), SReg) 811 .addReg(SReg, RegState::Kill) 812 .addImm(Offset); 813 814 // Convert into indexed form of the instruction: 815 // 816 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 817 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 818 unsigned OperandBase; 819 820 if (OpC != TargetInstrInfo::INLINEASM) { 821 assert(ImmToIdxMap.count(OpC) && 822 "No indexed form of load or store available!"); 823 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; 824 MI.setDesc(TII.get(NewOpcode)); 825 OperandBase = 1; 826 } else { 827 OperandBase = OffsetOperandNo; 828 } 829 830 unsigned StackReg = MI.getOperand(FIOperandNo).getReg(); 831 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false); 832 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false); 833 return 0; 834 } 835 836 /// VRRegNo - Map from a numbered VR register to its enum value. 837 /// 838 static const unsigned short VRRegNo[] = { 839 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 , 840 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, 841 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, 842 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31 843 }; 844 845 /// RemoveVRSaveCode - We have found that this function does not need any code 846 /// to manipulate the VRSAVE register, even though it uses vector registers. 847 /// This can happen when the only registers used are known to be live in or out 848 /// of the function. Remove all of the VRSAVE related code from the function. 849 static void RemoveVRSaveCode(MachineInstr *MI) { 850 MachineBasicBlock *Entry = MI->getParent(); 851 MachineFunction *MF = Entry->getParent(); 852 853 // We know that the MTVRSAVE instruction immediately follows MI. Remove it. 854 MachineBasicBlock::iterator MBBI = MI; 855 ++MBBI; 856 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE); 857 MBBI->eraseFromParent(); 858 859 bool RemovedAllMTVRSAVEs = true; 860 // See if we can find and remove the MTVRSAVE instruction from all of the 861 // epilog blocks. 862 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) { 863 // If last instruction is a return instruction, add an epilogue 864 if (!I->empty() && I->back().getDesc().isReturn()) { 865 bool FoundIt = false; 866 for (MBBI = I->end(); MBBI != I->begin(); ) { 867 --MBBI; 868 if (MBBI->getOpcode() == PPC::MTVRSAVE) { 869 MBBI->eraseFromParent(); // remove it. 870 FoundIt = true; 871 break; 872 } 873 } 874 RemovedAllMTVRSAVEs &= FoundIt; 875 } 876 } 877 878 // If we found and removed all MTVRSAVE instructions, remove the read of 879 // VRSAVE as well. 880 if (RemovedAllMTVRSAVEs) { 881 MBBI = MI; 882 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?"); 883 --MBBI; 884 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?"); 885 MBBI->eraseFromParent(); 886 } 887 888 // Finally, nuke the UPDATE_VRSAVE. 889 MI->eraseFromParent(); 890 } 891 892 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the 893 // instruction selector. Based on the vector registers that have been used, 894 // transform this into the appropriate ORI instruction. 895 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) { 896 MachineFunction *MF = MI->getParent()->getParent(); 897 DebugLoc dl = MI->getDebugLoc(); 898 899 unsigned UsedRegMask = 0; 900 for (unsigned i = 0; i != 32; ++i) 901 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i])) 902 UsedRegMask |= 1 << (31-i); 903 904 // Live in and live out values already must be in the mask, so don't bother 905 // marking them. 906 for (MachineRegisterInfo::livein_iterator 907 I = MF->getRegInfo().livein_begin(), 908 E = MF->getRegInfo().livein_end(); I != E; ++I) { 909 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first); 910 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg. 911 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 912 } 913 for (MachineRegisterInfo::liveout_iterator 914 I = MF->getRegInfo().liveout_begin(), 915 E = MF->getRegInfo().liveout_end(); I != E; ++I) { 916 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I); 917 if (VRRegNo[RegNo] == *I) // If this really is a vector reg. 918 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 919 } 920 921 // If no registers are used, turn this into a copy. 922 if (UsedRegMask == 0) { 923 // Remove all VRSAVE code. 924 RemoveVRSaveCode(MI); 925 return; 926 } 927 928 unsigned SrcReg = MI->getOperand(1).getReg(); 929 unsigned DstReg = MI->getOperand(0).getReg(); 930 931 if ((UsedRegMask & 0xFFFF) == UsedRegMask) { 932 if (DstReg != SrcReg) 933 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 934 .addReg(SrcReg) 935 .addImm(UsedRegMask); 936 else 937 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 938 .addReg(SrcReg, RegState::Kill) 939 .addImm(UsedRegMask); 940 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { 941 if (DstReg != SrcReg) 942 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 943 .addReg(SrcReg) 944 .addImm(UsedRegMask >> 16); 945 else 946 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 947 .addReg(SrcReg, RegState::Kill) 948 .addImm(UsedRegMask >> 16); 949 } else { 950 if (DstReg != SrcReg) 951 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 952 .addReg(SrcReg) 953 .addImm(UsedRegMask >> 16); 954 else 955 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 956 .addReg(SrcReg, RegState::Kill) 957 .addImm(UsedRegMask >> 16); 958 959 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 960 .addReg(DstReg, RegState::Kill) 961 .addImm(UsedRegMask & 0xFFFF); 962 } 963 964 // Remove the old UPDATE_VRSAVE instruction. 965 MI->eraseFromParent(); 966 } 967 968 /// determineFrameLayout - Determine the size of the frame and maximum call 969 /// frame size. 970 void PPCRegisterInfo::determineFrameLayout(MachineFunction &MF) const { 971 MachineFrameInfo *MFI = MF.getFrameInfo(); 972 973 // Get the number of bytes to allocate from the FrameInfo 974 unsigned FrameSize = MFI->getStackSize(); 975 976 // Get the alignments provided by the target, and the maximum alignment 977 // (if any) of the fixed frame objects. 978 unsigned MaxAlign = MFI->getMaxAlignment(); 979 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 980 unsigned AlignMask = TargetAlign - 1; // 981 982 // If we are a leaf function, and use up to 224 bytes of stack space, 983 // don't have a frame pointer, calls, or dynamic alloca then we do not need 984 // to adjust the stack pointer (we fit in the Red Zone). 985 bool DisableRedZone = MF.getFunction()->hasFnAttr(Attribute::NoRedZone); 986 // FIXME SVR4 The 32-bit SVR4 ABI has no red zone. 987 if (!DisableRedZone && 988 FrameSize <= 224 && // Fits in red zone. 989 !MFI->hasVarSizedObjects() && // No dynamic alloca. 990 !MFI->hasCalls() && // No calls. 991 (!ALIGN_STACK || MaxAlign <= TargetAlign)) { // No special alignment. 992 // No need for frame 993 MFI->setStackSize(0); 994 return; 995 } 996 997 // Get the maximum call frame size of all the calls. 998 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 999 1000 // Maximum call frame needs to be at least big enough for linkage and 8 args. 1001 unsigned minCallFrameSize = 1002 PPCFrameInfo::getMinCallFrameSize(Subtarget.isPPC64(), 1003 Subtarget.isDarwinABI()); 1004 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize); 1005 1006 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so 1007 // that allocations will be aligned. 1008 if (MFI->hasVarSizedObjects()) 1009 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask; 1010 1011 // Update maximum call frame size. 1012 MFI->setMaxCallFrameSize(maxCallFrameSize); 1013 1014 // Include call frame size in total. 1015 FrameSize += maxCallFrameSize; 1016 1017 // Make sure the frame is aligned. 1018 FrameSize = (FrameSize + AlignMask) & ~AlignMask; 1019 1020 // Update frame info. 1021 MFI->setStackSize(FrameSize); 1022 } 1023 1024 void 1025 PPCRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 1026 RegScavenger *RS) const { 1027 // Save and clear the LR state. 1028 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1029 unsigned LR = getRARegister(); 1030 FI->setMustSaveLR(MustSaveLR(MF, LR)); 1031 MF.getRegInfo().setPhysRegUnused(LR); 1032 1033 // Save R31 if necessary 1034 int FPSI = FI->getFramePointerSaveIndex(); 1035 bool isPPC64 = Subtarget.isPPC64(); 1036 bool isSVR4ABI = Subtarget.isSVR4ABI(); 1037 bool isDarwinABI = Subtarget.isDarwinABI(); 1038 MachineFrameInfo *MFI = MF.getFrameInfo(); 1039 1040 // If the frame pointer save index hasn't been defined yet. 1041 if (!FPSI && needsFP(MF) && isSVR4ABI) { 1042 // Find out what the fix offset of the frame pointer save area. 1043 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(isPPC64, 1044 isDarwinABI); 1045 // Allocate the frame index for frame pointer save area. 1046 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, 1047 true, false); 1048 // Save the result. 1049 FI->setFramePointerSaveIndex(FPSI); 1050 } 1051 1052 // Reserve stack space to move the linkage area to in case of a tail call. 1053 int TCSPDelta = 0; 1054 if (PerformTailCallOpt && (TCSPDelta = FI->getTailCallSPDelta()) < 0) { 1055 MF.getFrameInfo()->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, 1056 true, false); 1057 } 1058 1059 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or 1060 // a large stack, which will require scavenging a register to materialize a 1061 // large offset. 1062 // FIXME: this doesn't actually check stack size, so is a bit pessimistic 1063 // FIXME: doesn't detect whether or not we need to spill vXX, which requires 1064 // r0 for now. 1065 1066 if (EnableRegisterScavenging) // FIXME (64-bit): Enable. 1067 if (needsFP(MF) || spillsCR(MF)) { 1068 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 1069 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 1070 const TargetRegisterClass *RC = isPPC64 ? G8RC : GPRC; 1071 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 1072 RC->getAlignment(), 1073 false)); 1074 } 1075 } 1076 1077 void 1078 PPCRegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) 1079 const { 1080 // Early exit if not using the SVR4 ABI. 1081 if (!Subtarget.isSVR4ABI()) { 1082 return; 1083 } 1084 1085 // Get callee saved register information. 1086 MachineFrameInfo *FFI = MF.getFrameInfo(); 1087 const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo(); 1088 1089 // Early exit if no callee saved registers are modified! 1090 if (CSI.empty() && !needsFP(MF)) { 1091 return; 1092 } 1093 1094 unsigned MinGPR = PPC::R31; 1095 unsigned MinG8R = PPC::X31; 1096 unsigned MinFPR = PPC::F31; 1097 unsigned MinVR = PPC::V31; 1098 1099 bool HasGPSaveArea = false; 1100 bool HasG8SaveArea = false; 1101 bool HasFPSaveArea = false; 1102 bool HasCRSaveArea = false; 1103 bool HasVRSAVESaveArea = false; 1104 bool HasVRSaveArea = false; 1105 1106 SmallVector<CalleeSavedInfo, 18> GPRegs; 1107 SmallVector<CalleeSavedInfo, 18> G8Regs; 1108 SmallVector<CalleeSavedInfo, 18> FPRegs; 1109 SmallVector<CalleeSavedInfo, 18> VRegs; 1110 1111 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1112 unsigned Reg = CSI[i].getReg(); 1113 const TargetRegisterClass *RC = CSI[i].getRegClass(); 1114 1115 if (RC == PPC::GPRCRegisterClass) { 1116 HasGPSaveArea = true; 1117 1118 GPRegs.push_back(CSI[i]); 1119 1120 if (Reg < MinGPR) { 1121 MinGPR = Reg; 1122 } 1123 } else if (RC == PPC::G8RCRegisterClass) { 1124 HasG8SaveArea = true; 1125 1126 G8Regs.push_back(CSI[i]); 1127 1128 if (Reg < MinG8R) { 1129 MinG8R = Reg; 1130 } 1131 } else if (RC == PPC::F8RCRegisterClass) { 1132 HasFPSaveArea = true; 1133 1134 FPRegs.push_back(CSI[i]); 1135 1136 if (Reg < MinFPR) { 1137 MinFPR = Reg; 1138 } 1139 // FIXME SVR4: Disable CR save area for now. 1140 } else if ( RC == PPC::CRBITRCRegisterClass 1141 || RC == PPC::CRRCRegisterClass) { 1142 // HasCRSaveArea = true; 1143 } else if (RC == PPC::VRSAVERCRegisterClass) { 1144 HasVRSAVESaveArea = true; 1145 } else if (RC == PPC::VRRCRegisterClass) { 1146 HasVRSaveArea = true; 1147 1148 VRegs.push_back(CSI[i]); 1149 1150 if (Reg < MinVR) { 1151 MinVR = Reg; 1152 } 1153 } else { 1154 llvm_unreachable("Unknown RegisterClass!"); 1155 } 1156 } 1157 1158 PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>(); 1159 1160 int64_t LowerBound = 0; 1161 1162 // Take into account stack space reserved for tail calls. 1163 int TCSPDelta = 0; 1164 if (PerformTailCallOpt && (TCSPDelta = PFI->getTailCallSPDelta()) < 0) { 1165 LowerBound = TCSPDelta; 1166 } 1167 1168 // The Floating-point register save area is right below the back chain word 1169 // of the previous stack frame. 1170 if (HasFPSaveArea) { 1171 for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) { 1172 int FI = FPRegs[i].getFrameIdx(); 1173 1174 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1175 } 1176 1177 LowerBound -= (31 - getRegisterNumbering(MinFPR) + 1) * 8; 1178 } 1179 1180 // Check whether the frame pointer register is allocated. If so, make sure it 1181 // is spilled to the correct offset. 1182 if (needsFP(MF)) { 1183 HasGPSaveArea = true; 1184 1185 int FI = PFI->getFramePointerSaveIndex(); 1186 assert(FI && "No Frame Pointer Save Slot!"); 1187 1188 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1189 } 1190 1191 // General register save area starts right below the Floating-point 1192 // register save area. 1193 if (HasGPSaveArea || HasG8SaveArea) { 1194 // Move general register save area spill slots down, taking into account 1195 // the size of the Floating-point register save area. 1196 for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) { 1197 int FI = GPRegs[i].getFrameIdx(); 1198 1199 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1200 } 1201 1202 // Move general register save area spill slots down, taking into account 1203 // the size of the Floating-point register save area. 1204 for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) { 1205 int FI = G8Regs[i].getFrameIdx(); 1206 1207 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1208 } 1209 1210 unsigned MinReg = std::min<unsigned>(getRegisterNumbering(MinGPR), 1211 getRegisterNumbering(MinG8R)); 1212 1213 if (Subtarget.isPPC64()) { 1214 LowerBound -= (31 - MinReg + 1) * 8; 1215 } else { 1216 LowerBound -= (31 - MinReg + 1) * 4; 1217 } 1218 } 1219 1220 // The CR save area is below the general register save area. 1221 if (HasCRSaveArea) { 1222 // FIXME SVR4: Is it actually possible to have multiple elements in CSI 1223 // which have the CR/CRBIT register class? 1224 // Adjust the frame index of the CR spill slot. 1225 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1226 const TargetRegisterClass *RC = CSI[i].getRegClass(); 1227 1228 if (RC == PPC::CRBITRCRegisterClass || RC == PPC::CRRCRegisterClass) { 1229 int FI = CSI[i].getFrameIdx(); 1230 1231 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1232 } 1233 } 1234 1235 LowerBound -= 4; // The CR save area is always 4 bytes long. 1236 } 1237 1238 if (HasVRSAVESaveArea) { 1239 // FIXME SVR4: Is it actually possible to have multiple elements in CSI 1240 // which have the VRSAVE register class? 1241 // Adjust the frame index of the VRSAVE spill slot. 1242 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1243 const TargetRegisterClass *RC = CSI[i].getRegClass(); 1244 1245 if (RC == PPC::VRSAVERCRegisterClass) { 1246 int FI = CSI[i].getFrameIdx(); 1247 1248 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1249 } 1250 } 1251 1252 LowerBound -= 4; // The VRSAVE save area is always 4 bytes long. 1253 } 1254 1255 if (HasVRSaveArea) { 1256 // Insert alignment padding, we need 16-byte alignment. 1257 LowerBound = (LowerBound - 15) & ~(15); 1258 1259 for (unsigned i = 0, e = VRegs.size(); i != e; ++i) { 1260 int FI = VRegs[i].getFrameIdx(); 1261 1262 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1263 } 1264 } 1265 } 1266 1267 void 1268 PPCRegisterInfo::emitPrologue(MachineFunction &MF) const { 1269 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB 1270 MachineBasicBlock::iterator MBBI = MBB.begin(); 1271 MachineFrameInfo *MFI = MF.getFrameInfo(); 1272 MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); 1273 DebugLoc dl = DebugLoc::getUnknownLoc(); 1274 bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) || 1275 !MF.getFunction()->doesNotThrow() || 1276 UnwindTablesMandatory; 1277 1278 // Prepare for frame info. 1279 unsigned FrameLabelId = 0; 1280 1281 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it, 1282 // process it. 1283 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { 1284 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) { 1285 HandleVRSaveUpdate(MBBI, TII); 1286 break; 1287 } 1288 } 1289 1290 // Move MBBI back to the beginning of the function. 1291 MBBI = MBB.begin(); 1292 1293 // Work out frame sizes. 1294 determineFrameLayout(MF); 1295 unsigned FrameSize = MFI->getStackSize(); 1296 1297 int NegFrameSize = -FrameSize; 1298 1299 // Get processor type. 1300 bool isPPC64 = Subtarget.isPPC64(); 1301 // Get operating system 1302 bool isDarwinABI = Subtarget.isDarwinABI(); 1303 // Check if the link register (LR) must be saved. 1304 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1305 bool MustSaveLR = FI->mustSaveLR(); 1306 // Do we have a frame pointer for this function? 1307 bool HasFP = hasFP(MF) && FrameSize; 1308 1309 int LROffset = PPCFrameInfo::getReturnSaveOffset(isPPC64, isDarwinABI); 1310 1311 int FPOffset = 0; 1312 if (HasFP) { 1313 if (Subtarget.isSVR4ABI()) { 1314 MachineFrameInfo *FFI = MF.getFrameInfo(); 1315 int FPIndex = FI->getFramePointerSaveIndex(); 1316 assert(FPIndex && "No Frame Pointer Save Slot!"); 1317 FPOffset = FFI->getObjectOffset(FPIndex); 1318 } else { 1319 FPOffset = PPCFrameInfo::getFramePointerSaveOffset(isPPC64, isDarwinABI); 1320 } 1321 } 1322 1323 if (isPPC64) { 1324 if (MustSaveLR) 1325 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR8), PPC::X0); 1326 1327 if (HasFP) 1328 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD)) 1329 .addReg(PPC::X31) 1330 .addImm(FPOffset/4) 1331 .addReg(PPC::X1); 1332 1333 if (MustSaveLR) 1334 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD)) 1335 .addReg(PPC::X0) 1336 .addImm(LROffset / 4) 1337 .addReg(PPC::X1); 1338 } else { 1339 if (MustSaveLR) 1340 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR), PPC::R0); 1341 1342 if (HasFP) 1343 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW)) 1344 .addReg(PPC::R31) 1345 .addImm(FPOffset) 1346 .addReg(PPC::R1); 1347 1348 if (MustSaveLR) 1349 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW)) 1350 .addReg(PPC::R0) 1351 .addImm(LROffset) 1352 .addReg(PPC::R1); 1353 } 1354 1355 // Skip if a leaf routine. 1356 if (!FrameSize) return; 1357 1358 // Get stack alignments. 1359 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 1360 unsigned MaxAlign = MFI->getMaxAlignment(); 1361 1362 // Adjust stack pointer: r1 += NegFrameSize. 1363 // If there is a preferred stack alignment, align R1 now 1364 if (!isPPC64) { 1365 // PPC32. 1366 if (ALIGN_STACK && MaxAlign > TargetAlign) { 1367 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!"); 1368 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!"); 1369 1370 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), PPC::R0) 1371 .addReg(PPC::R1) 1372 .addImm(0) 1373 .addImm(32 - Log2_32(MaxAlign)) 1374 .addImm(31); 1375 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC) ,PPC::R0) 1376 .addReg(PPC::R0, RegState::Kill) 1377 .addImm(NegFrameSize); 1378 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX)) 1379 .addReg(PPC::R1) 1380 .addReg(PPC::R1) 1381 .addReg(PPC::R0); 1382 } else if (isInt16(NegFrameSize)) { 1383 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWU), PPC::R1) 1384 .addReg(PPC::R1) 1385 .addImm(NegFrameSize) 1386 .addReg(PPC::R1); 1387 } else { 1388 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0) 1389 .addImm(NegFrameSize >> 16); 1390 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0) 1391 .addReg(PPC::R0, RegState::Kill) 1392 .addImm(NegFrameSize & 0xFFFF); 1393 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX)) 1394 .addReg(PPC::R1) 1395 .addReg(PPC::R1) 1396 .addReg(PPC::R0); 1397 } 1398 } else { // PPC64. 1399 if (ALIGN_STACK && MaxAlign > TargetAlign) { 1400 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!"); 1401 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!"); 1402 1403 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), PPC::X0) 1404 .addReg(PPC::X1) 1405 .addImm(0) 1406 .addImm(64 - Log2_32(MaxAlign)); 1407 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC8), PPC::X0) 1408 .addReg(PPC::X0) 1409 .addImm(NegFrameSize); 1410 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX)) 1411 .addReg(PPC::X1) 1412 .addReg(PPC::X1) 1413 .addReg(PPC::X0); 1414 } else if (isInt16(NegFrameSize)) { 1415 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDU), PPC::X1) 1416 .addReg(PPC::X1) 1417 .addImm(NegFrameSize / 4) 1418 .addReg(PPC::X1); 1419 } else { 1420 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0) 1421 .addImm(NegFrameSize >> 16); 1422 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0) 1423 .addReg(PPC::X0, RegState::Kill) 1424 .addImm(NegFrameSize & 0xFFFF); 1425 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX)) 1426 .addReg(PPC::X1) 1427 .addReg(PPC::X1) 1428 .addReg(PPC::X0); 1429 } 1430 } 1431 1432 std::vector<MachineMove> &Moves = MMI->getFrameMoves(); 1433 1434 // Add the "machine moves" for the instructions we generated above, but in 1435 // reverse order. 1436 if (needsFrameMoves) { 1437 // Mark effective beginning of when frame pointer becomes valid. 1438 FrameLabelId = MMI->NextLabelID(); 1439 BuildMI(MBB, MBBI, dl, TII.get(PPC::DBG_LABEL)).addImm(FrameLabelId); 1440 1441 // Show update of SP. 1442 if (NegFrameSize) { 1443 MachineLocation SPDst(MachineLocation::VirtualFP); 1444 MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize); 1445 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc)); 1446 } else { 1447 MachineLocation SP(isPPC64 ? PPC::X31 : PPC::R31); 1448 Moves.push_back(MachineMove(FrameLabelId, SP, SP)); 1449 } 1450 1451 if (HasFP) { 1452 MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset); 1453 MachineLocation FPSrc(isPPC64 ? PPC::X31 : PPC::R31); 1454 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc)); 1455 } 1456 1457 if (MustSaveLR) { 1458 MachineLocation LRDst(MachineLocation::VirtualFP, LROffset); 1459 MachineLocation LRSrc(isPPC64 ? PPC::LR8 : PPC::LR); 1460 Moves.push_back(MachineMove(FrameLabelId, LRDst, LRSrc)); 1461 } 1462 } 1463 1464 unsigned ReadyLabelId = 0; 1465 1466 // If there is a frame pointer, copy R1 into R31 1467 if (HasFP) { 1468 if (!isPPC64) { 1469 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR), PPC::R31) 1470 .addReg(PPC::R1) 1471 .addReg(PPC::R1); 1472 } else { 1473 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR8), PPC::X31) 1474 .addReg(PPC::X1) 1475 .addReg(PPC::X1); 1476 } 1477 1478 if (needsFrameMoves) { 1479 ReadyLabelId = MMI->NextLabelID(); 1480 1481 // Mark effective beginning of when frame pointer is ready. 1482 BuildMI(MBB, MBBI, dl, TII.get(PPC::DBG_LABEL)).addImm(ReadyLabelId); 1483 1484 MachineLocation FPDst(HasFP ? (isPPC64 ? PPC::X31 : PPC::R31) : 1485 (isPPC64 ? PPC::X1 : PPC::R1)); 1486 MachineLocation FPSrc(MachineLocation::VirtualFP); 1487 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc)); 1488 } 1489 } 1490 1491 if (needsFrameMoves) { 1492 unsigned LabelId = HasFP ? ReadyLabelId : FrameLabelId; 1493 1494 // Add callee saved registers to move list. 1495 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 1496 for (unsigned I = 0, E = CSI.size(); I != E; ++I) { 1497 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx()); 1498 unsigned Reg = CSI[I].getReg(); 1499 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue; 1500 MachineLocation CSDst(MachineLocation::VirtualFP, Offset); 1501 MachineLocation CSSrc(Reg); 1502 Moves.push_back(MachineMove(LabelId, CSDst, CSSrc)); 1503 } 1504 } 1505 } 1506 1507 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF, 1508 MachineBasicBlock &MBB) const { 1509 MachineBasicBlock::iterator MBBI = prior(MBB.end()); 1510 unsigned RetOpcode = MBBI->getOpcode(); 1511 DebugLoc dl = DebugLoc::getUnknownLoc(); 1512 1513 assert( (RetOpcode == PPC::BLR || 1514 RetOpcode == PPC::TCRETURNri || 1515 RetOpcode == PPC::TCRETURNdi || 1516 RetOpcode == PPC::TCRETURNai || 1517 RetOpcode == PPC::TCRETURNri8 || 1518 RetOpcode == PPC::TCRETURNdi8 || 1519 RetOpcode == PPC::TCRETURNai8) && 1520 "Can only insert epilog into returning blocks"); 1521 1522 // Get alignment info so we know how to restore r1 1523 const MachineFrameInfo *MFI = MF.getFrameInfo(); 1524 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 1525 unsigned MaxAlign = MFI->getMaxAlignment(); 1526 1527 // Get the number of bytes allocated from the FrameInfo. 1528 int FrameSize = MFI->getStackSize(); 1529 1530 // Get processor type. 1531 bool isPPC64 = Subtarget.isPPC64(); 1532 // Get operating system 1533 bool isDarwinABI = Subtarget.isDarwinABI(); 1534 // Check if the link register (LR) has been saved. 1535 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1536 bool MustSaveLR = FI->mustSaveLR(); 1537 // Do we have a frame pointer for this function? 1538 bool HasFP = hasFP(MF) && FrameSize; 1539 1540 int LROffset = PPCFrameInfo::getReturnSaveOffset(isPPC64, isDarwinABI); 1541 1542 int FPOffset = 0; 1543 if (HasFP) { 1544 if (Subtarget.isSVR4ABI()) { 1545 MachineFrameInfo *FFI = MF.getFrameInfo(); 1546 int FPIndex = FI->getFramePointerSaveIndex(); 1547 assert(FPIndex && "No Frame Pointer Save Slot!"); 1548 FPOffset = FFI->getObjectOffset(FPIndex); 1549 } else { 1550 FPOffset = PPCFrameInfo::getFramePointerSaveOffset(isPPC64, isDarwinABI); 1551 } 1552 } 1553 1554 bool UsesTCRet = RetOpcode == PPC::TCRETURNri || 1555 RetOpcode == PPC::TCRETURNdi || 1556 RetOpcode == PPC::TCRETURNai || 1557 RetOpcode == PPC::TCRETURNri8 || 1558 RetOpcode == PPC::TCRETURNdi8 || 1559 RetOpcode == PPC::TCRETURNai8; 1560 1561 if (UsesTCRet) { 1562 int MaxTCRetDelta = FI->getTailCallSPDelta(); 1563 MachineOperand &StackAdjust = MBBI->getOperand(1); 1564 assert(StackAdjust.isImm() && "Expecting immediate value."); 1565 // Adjust stack pointer. 1566 int StackAdj = StackAdjust.getImm(); 1567 int Delta = StackAdj - MaxTCRetDelta; 1568 assert((Delta >= 0) && "Delta must be positive"); 1569 if (MaxTCRetDelta>0) 1570 FrameSize += (StackAdj +Delta); 1571 else 1572 FrameSize += StackAdj; 1573 } 1574 1575 if (FrameSize) { 1576 // The loaded (or persistent) stack pointer value is offset by the 'stwu' 1577 // on entry to the function. Add this offset back now. 1578 if (!isPPC64) { 1579 // If this function contained a fastcc call and PerformTailCallOpt is 1580 // enabled (=> hasFastCall()==true) the fastcc call might contain a tail 1581 // call which invalidates the stack pointer value in SP(0). So we use the 1582 // value of R31 in this case. 1583 if (FI->hasFastCall() && isInt16(FrameSize)) { 1584 assert(hasFP(MF) && "Expecting a valid the frame pointer."); 1585 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1) 1586 .addReg(PPC::R31).addImm(FrameSize); 1587 } else if(FI->hasFastCall()) { 1588 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0) 1589 .addImm(FrameSize >> 16); 1590 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0) 1591 .addReg(PPC::R0, RegState::Kill) 1592 .addImm(FrameSize & 0xFFFF); 1593 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD4)) 1594 .addReg(PPC::R1) 1595 .addReg(PPC::R31) 1596 .addReg(PPC::R0); 1597 } else if (isInt16(FrameSize) && 1598 (!ALIGN_STACK || TargetAlign >= MaxAlign) && 1599 !MFI->hasVarSizedObjects()) { 1600 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1) 1601 .addReg(PPC::R1).addImm(FrameSize); 1602 } else { 1603 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ),PPC::R1) 1604 .addImm(0).addReg(PPC::R1); 1605 } 1606 } else { 1607 if (FI->hasFastCall() && isInt16(FrameSize)) { 1608 assert(hasFP(MF) && "Expecting a valid the frame pointer."); 1609 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1) 1610 .addReg(PPC::X31).addImm(FrameSize); 1611 } else if(FI->hasFastCall()) { 1612 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0) 1613 .addImm(FrameSize >> 16); 1614 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0) 1615 .addReg(PPC::X0, RegState::Kill) 1616 .addImm(FrameSize & 0xFFFF); 1617 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD8)) 1618 .addReg(PPC::X1) 1619 .addReg(PPC::X31) 1620 .addReg(PPC::X0); 1621 } else if (isInt16(FrameSize) && TargetAlign >= MaxAlign && 1622 !MFI->hasVarSizedObjects()) { 1623 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1) 1624 .addReg(PPC::X1).addImm(FrameSize); 1625 } else { 1626 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X1) 1627 .addImm(0).addReg(PPC::X1); 1628 } 1629 } 1630 } 1631 1632 if (isPPC64) { 1633 if (MustSaveLR) 1634 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X0) 1635 .addImm(LROffset/4).addReg(PPC::X1); 1636 1637 if (HasFP) 1638 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X31) 1639 .addImm(FPOffset/4).addReg(PPC::X1); 1640 1641 if (MustSaveLR) 1642 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR8)).addReg(PPC::X0); 1643 } else { 1644 if (MustSaveLR) 1645 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R0) 1646 .addImm(LROffset).addReg(PPC::R1); 1647 1648 if (HasFP) 1649 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R31) 1650 .addImm(FPOffset).addReg(PPC::R1); 1651 1652 if (MustSaveLR) 1653 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR)).addReg(PPC::R0); 1654 } 1655 1656 // Callee pop calling convention. Pop parameter/linkage area. Used for tail 1657 // call optimization 1658 if (PerformTailCallOpt && RetOpcode == PPC::BLR && 1659 MF.getFunction()->getCallingConv() == CallingConv::Fast) { 1660 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1661 unsigned CallerAllocatedAmt = FI->getMinReservedArea(); 1662 unsigned StackReg = isPPC64 ? PPC::X1 : PPC::R1; 1663 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31; 1664 unsigned TmpReg = isPPC64 ? PPC::X0 : PPC::R0; 1665 unsigned ADDIInstr = isPPC64 ? PPC::ADDI8 : PPC::ADDI; 1666 unsigned ADDInstr = isPPC64 ? PPC::ADD8 : PPC::ADD4; 1667 unsigned LISInstr = isPPC64 ? PPC::LIS8 : PPC::LIS; 1668 unsigned ORIInstr = isPPC64 ? PPC::ORI8 : PPC::ORI; 1669 1670 if (CallerAllocatedAmt && isInt16(CallerAllocatedAmt)) { 1671 BuildMI(MBB, MBBI, dl, TII.get(ADDIInstr), StackReg) 1672 .addReg(StackReg).addImm(CallerAllocatedAmt); 1673 } else { 1674 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) 1675 .addImm(CallerAllocatedAmt >> 16); 1676 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) 1677 .addReg(TmpReg, RegState::Kill) 1678 .addImm(CallerAllocatedAmt & 0xFFFF); 1679 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr)) 1680 .addReg(StackReg) 1681 .addReg(FPReg) 1682 .addReg(TmpReg); 1683 } 1684 } else if (RetOpcode == PPC::TCRETURNdi) { 1685 MBBI = prior(MBB.end()); 1686 MachineOperand &JumpTarget = MBBI->getOperand(0); 1687 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)). 1688 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); 1689 } else if (RetOpcode == PPC::TCRETURNri) { 1690 MBBI = prior(MBB.end()); 1691 assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); 1692 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR)); 1693 } else if (RetOpcode == PPC::TCRETURNai) { 1694 MBBI = prior(MBB.end()); 1695 MachineOperand &JumpTarget = MBBI->getOperand(0); 1696 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm()); 1697 } else if (RetOpcode == PPC::TCRETURNdi8) { 1698 MBBI = prior(MBB.end()); 1699 MachineOperand &JumpTarget = MBBI->getOperand(0); 1700 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)). 1701 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); 1702 } else if (RetOpcode == PPC::TCRETURNri8) { 1703 MBBI = prior(MBB.end()); 1704 assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); 1705 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8)); 1706 } else if (RetOpcode == PPC::TCRETURNai8) { 1707 MBBI = prior(MBB.end()); 1708 MachineOperand &JumpTarget = MBBI->getOperand(0); 1709 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm()); 1710 } 1711 } 1712 1713 unsigned PPCRegisterInfo::getRARegister() const { 1714 return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8; 1715 } 1716 1717 unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 1718 if (!Subtarget.isPPC64()) 1719 return hasFP(MF) ? PPC::R31 : PPC::R1; 1720 else 1721 return hasFP(MF) ? PPC::X31 : PPC::X1; 1722 } 1723 1724 void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) 1725 const { 1726 // Initial state of the frame pointer is R1. 1727 MachineLocation Dst(MachineLocation::VirtualFP); 1728 MachineLocation Src(PPC::R1, 0); 1729 Moves.push_back(MachineMove(0, Dst, Src)); 1730 } 1731 1732 unsigned PPCRegisterInfo::getEHExceptionRegister() const { 1733 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3; 1734 } 1735 1736 unsigned PPCRegisterInfo::getEHHandlerRegister() const { 1737 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4; 1738 } 1739 1740 int PPCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { 1741 // FIXME: Most probably dwarf numbers differs for Linux and Darwin 1742 return PPCGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); 1743 } 1744 1745 #include "PPCGenRegisterInfo.inc" 1746 1747