1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the TargetRegisterInfo 11 // class. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #define DEBUG_TYPE "reginfo" 16 #include "PPC.h" 17 #include "PPCInstrBuilder.h" 18 #include "PPCMachineFunctionInfo.h" 19 #include "PPCRegisterInfo.h" 20 #include "PPCFrameInfo.h" 21 #include "PPCSubtarget.h" 22 #include "llvm/CallingConv.h" 23 #include "llvm/Constants.h" 24 #include "llvm/Function.h" 25 #include "llvm/Type.h" 26 #include "llvm/CodeGen/ValueTypes.h" 27 #include "llvm/CodeGen/MachineInstrBuilder.h" 28 #include "llvm/CodeGen/MachineModuleInfo.h" 29 #include "llvm/CodeGen/MachineFunction.h" 30 #include "llvm/CodeGen/MachineFrameInfo.h" 31 #include "llvm/CodeGen/MachineLocation.h" 32 #include "llvm/CodeGen/MachineRegisterInfo.h" 33 #include "llvm/CodeGen/RegisterScavenging.h" 34 #include "llvm/Target/TargetFrameInfo.h" 35 #include "llvm/Target/TargetInstrInfo.h" 36 #include "llvm/Target/TargetMachine.h" 37 #include "llvm/Target/TargetOptions.h" 38 #include "llvm/Support/CommandLine.h" 39 #include "llvm/Support/Debug.h" 40 #include "llvm/Support/ErrorHandling.h" 41 #include "llvm/Support/MathExtras.h" 42 #include "llvm/Support/raw_ostream.h" 43 #include "llvm/ADT/BitVector.h" 44 #include "llvm/ADT/STLExtras.h" 45 #include <cstdlib> 46 47 // FIXME (64-bit): Eventually enable by default. 48 namespace llvm { 49 cl::opt<bool> EnablePPC32RS("enable-ppc32-regscavenger", 50 cl::init(false), 51 cl::desc("Enable PPC32 register scavenger"), 52 cl::Hidden); 53 cl::opt<bool> EnablePPC64RS("enable-ppc64-regscavenger", 54 cl::init(false), 55 cl::desc("Enable PPC64 register scavenger"), 56 cl::Hidden); 57 } 58 59 using namespace llvm; 60 61 // FIXME (64-bit): Should be inlined. 62 bool 63 PPCRegisterInfo::requiresRegisterScavenging(const MachineFunction &) const { 64 return ((EnablePPC32RS && !Subtarget.isPPC64()) || 65 (EnablePPC64RS && Subtarget.isPPC64())); 66 } 67 68 /// getRegisterNumbering - Given the enum value for some register, e.g. 69 /// PPC::F14, return the number that it corresponds to (e.g. 14). 70 unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) { 71 using namespace PPC; 72 switch (RegEnum) { 73 case 0: return 0; 74 case R0 : case X0 : case F0 : case V0 : case CR0: case CR0LT: return 0; 75 case R1 : case X1 : case F1 : case V1 : case CR1: case CR0GT: return 1; 76 case R2 : case X2 : case F2 : case V2 : case CR2: case CR0EQ: return 2; 77 case R3 : case X3 : case F3 : case V3 : case CR3: case CR0UN: return 3; 78 case R4 : case X4 : case F4 : case V4 : case CR4: case CR1LT: return 4; 79 case R5 : case X5 : case F5 : case V5 : case CR5: case CR1GT: return 5; 80 case R6 : case X6 : case F6 : case V6 : case CR6: case CR1EQ: return 6; 81 case R7 : case X7 : case F7 : case V7 : case CR7: case CR1UN: return 7; 82 case R8 : case X8 : case F8 : case V8 : case CR2LT: return 8; 83 case R9 : case X9 : case F9 : case V9 : case CR2GT: return 9; 84 case R10: case X10: case F10: case V10: case CR2EQ: return 10; 85 case R11: case X11: case F11: case V11: case CR2UN: return 11; 86 case R12: case X12: case F12: case V12: case CR3LT: return 12; 87 case R13: case X13: case F13: case V13: case CR3GT: return 13; 88 case R14: case X14: case F14: case V14: case CR3EQ: return 14; 89 case R15: case X15: case F15: case V15: case CR3UN: return 15; 90 case R16: case X16: case F16: case V16: case CR4LT: return 16; 91 case R17: case X17: case F17: case V17: case CR4GT: return 17; 92 case R18: case X18: case F18: case V18: case CR4EQ: return 18; 93 case R19: case X19: case F19: case V19: case CR4UN: return 19; 94 case R20: case X20: case F20: case V20: case CR5LT: return 20; 95 case R21: case X21: case F21: case V21: case CR5GT: return 21; 96 case R22: case X22: case F22: case V22: case CR5EQ: return 22; 97 case R23: case X23: case F23: case V23: case CR5UN: return 23; 98 case R24: case X24: case F24: case V24: case CR6LT: return 24; 99 case R25: case X25: case F25: case V25: case CR6GT: return 25; 100 case R26: case X26: case F26: case V26: case CR6EQ: return 26; 101 case R27: case X27: case F27: case V27: case CR6UN: return 27; 102 case R28: case X28: case F28: case V28: case CR7LT: return 28; 103 case R29: case X29: case F29: case V29: case CR7GT: return 29; 104 case R30: case X30: case F30: case V30: case CR7EQ: return 30; 105 case R31: case X31: case F31: case V31: case CR7UN: return 31; 106 default: 107 llvm_unreachable("Unhandled reg in PPCRegisterInfo::getRegisterNumbering!"); 108 } 109 } 110 111 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST, 112 const TargetInstrInfo &tii) 113 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP), 114 Subtarget(ST), TII(tii) { 115 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 116 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 117 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 118 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 119 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 120 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 121 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 122 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 123 124 // 64-bit 125 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8; 126 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8; 127 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8; 128 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX; 129 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32; 130 } 131 132 /// getPointerRegClass - Return the register class to use to hold pointers. 133 /// This is used for addressing modes. 134 const TargetRegisterClass * 135 PPCRegisterInfo::getPointerRegClass(unsigned Kind) const { 136 if (Subtarget.isPPC64()) 137 return &PPC::G8RCRegClass; 138 return &PPC::GPRCRegClass; 139 } 140 141 const unsigned* 142 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 143 // 32-bit Darwin calling convention. 144 static const unsigned Darwin32_CalleeSavedRegs[] = { 145 PPC::R13, PPC::R14, PPC::R15, 146 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 147 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 148 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 149 PPC::R28, PPC::R29, PPC::R30, PPC::R31, 150 151 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 152 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 153 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 154 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 155 PPC::F30, PPC::F31, 156 157 PPC::CR2, PPC::CR3, PPC::CR4, 158 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 159 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 160 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 161 162 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 163 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 164 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 165 166 PPC::LR, 0 167 }; 168 169 // 32-bit SVR4 calling convention. 170 static const unsigned SVR4_CalleeSavedRegs[] = { 171 PPC::R14, PPC::R15, 172 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 173 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 174 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 175 PPC::R28, PPC::R29, PPC::R30, PPC::R31, 176 177 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 178 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 179 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 180 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 181 PPC::F30, PPC::F31, 182 183 PPC::CR2, PPC::CR3, PPC::CR4, 184 185 PPC::VRSAVE, 186 187 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 188 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 189 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 190 191 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 192 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 193 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 194 195 0 196 }; 197 // 64-bit Darwin calling convention. 198 static const unsigned Darwin64_CalleeSavedRegs[] = { 199 PPC::X14, PPC::X15, 200 PPC::X16, PPC::X17, PPC::X18, PPC::X19, 201 PPC::X20, PPC::X21, PPC::X22, PPC::X23, 202 PPC::X24, PPC::X25, PPC::X26, PPC::X27, 203 PPC::X28, PPC::X29, PPC::X30, PPC::X31, 204 205 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 206 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 207 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 208 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 209 PPC::F30, PPC::F31, 210 211 PPC::CR2, PPC::CR3, PPC::CR4, 212 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 213 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 214 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 215 216 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 217 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 218 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 219 220 PPC::LR8, 0 221 }; 222 223 // 64-bit SVR4 calling convention. 224 static const unsigned SVR4_64_CalleeSavedRegs[] = { 225 PPC::X14, PPC::X15, 226 PPC::X16, PPC::X17, PPC::X18, PPC::X19, 227 PPC::X20, PPC::X21, PPC::X22, PPC::X23, 228 PPC::X24, PPC::X25, PPC::X26, PPC::X27, 229 PPC::X28, PPC::X29, PPC::X30, PPC::X31, 230 231 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 232 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 233 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 234 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 235 PPC::F30, PPC::F31, 236 237 PPC::CR2, PPC::CR3, PPC::CR4, 238 239 PPC::VRSAVE, 240 241 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 242 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 243 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 244 245 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 246 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 247 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 248 249 0 250 }; 251 252 if (Subtarget.isDarwinABI()) 253 return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegs : 254 Darwin32_CalleeSavedRegs; 255 256 return Subtarget.isPPC64() ? SVR4_64_CalleeSavedRegs : SVR4_CalleeSavedRegs; 257 } 258 259 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 260 BitVector Reserved(getNumRegs()); 261 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo(); 262 263 Reserved.set(PPC::R0); 264 Reserved.set(PPC::R1); 265 Reserved.set(PPC::LR); 266 Reserved.set(PPC::LR8); 267 Reserved.set(PPC::RM); 268 269 // The SVR4 ABI reserves r2 and r13 270 if (Subtarget.isSVR4ABI()) { 271 Reserved.set(PPC::R2); // System-reserved register 272 Reserved.set(PPC::R13); // Small Data Area pointer register 273 } 274 // Reserve R2 on Darwin to hack around the problem of save/restore of CR 275 // when the stack frame is too big to address directly; we need two regs. 276 // This is a hack. 277 if (Subtarget.isDarwinABI()) { 278 Reserved.set(PPC::R2); 279 } 280 281 // On PPC64, r13 is the thread pointer. Never allocate this register. 282 // Note that this is over conservative, as it also prevents allocation of R31 283 // when the FP is not needed. 284 if (Subtarget.isPPC64()) { 285 Reserved.set(PPC::R13); 286 Reserved.set(PPC::R31); 287 288 if (!requiresRegisterScavenging(MF)) 289 Reserved.set(PPC::R0); // FIXME (64-bit): Remove 290 291 Reserved.set(PPC::X0); 292 Reserved.set(PPC::X1); 293 Reserved.set(PPC::X13); 294 Reserved.set(PPC::X31); 295 296 // The 64-bit SVR4 ABI reserves r2 for the TOC pointer. 297 if (Subtarget.isSVR4ABI()) { 298 Reserved.set(PPC::X2); 299 } 300 // Reserve R2 on Darwin to hack around the problem of save/restore of CR 301 // when the stack frame is too big to address directly; we need two regs. 302 // This is a hack. 303 if (Subtarget.isDarwinABI()) { 304 Reserved.set(PPC::X2); 305 } 306 } 307 308 if (TFI->hasFP(MF)) 309 Reserved.set(PPC::R31); 310 311 return Reserved; 312 } 313 314 //===----------------------------------------------------------------------===// 315 // Stack Frame Processing methods 316 //===----------------------------------------------------------------------===// 317 318 void PPCRegisterInfo:: 319 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 320 MachineBasicBlock::iterator I) const { 321 if (GuaranteedTailCallOpt && I->getOpcode() == PPC::ADJCALLSTACKUP) { 322 // Add (actually subtract) back the amount the callee popped on return. 323 if (int CalleeAmt = I->getOperand(1).getImm()) { 324 bool is64Bit = Subtarget.isPPC64(); 325 CalleeAmt *= -1; 326 unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1; 327 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0; 328 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI; 329 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4; 330 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS; 331 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI; 332 MachineInstr *MI = I; 333 DebugLoc dl = MI->getDebugLoc(); 334 335 if (isInt<16>(CalleeAmt)) { 336 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg).addReg(StackReg). 337 addImm(CalleeAmt); 338 } else { 339 MachineBasicBlock::iterator MBBI = I; 340 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) 341 .addImm(CalleeAmt >> 16); 342 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) 343 .addReg(TmpReg, RegState::Kill) 344 .addImm(CalleeAmt & 0xFFFF); 345 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr)) 346 .addReg(StackReg) 347 .addReg(StackReg) 348 .addReg(TmpReg); 349 } 350 } 351 } 352 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions. 353 MBB.erase(I); 354 } 355 356 /// findScratchRegister - Find a 'free' PPC register. Try for a call-clobbered 357 /// register first and then a spilled callee-saved register if that fails. 358 static 359 unsigned findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS, 360 const TargetRegisterClass *RC, int SPAdj) { 361 assert(RS && "Register scavenging must be on"); 362 unsigned Reg = RS->FindUnusedReg(RC); 363 // FIXME: move ARM callee-saved reg scan to target independent code, then 364 // search for already spilled CS register here. 365 if (Reg == 0) 366 Reg = RS->scavengeRegister(RC, II, SPAdj); 367 return Reg; 368 } 369 370 /// lowerDynamicAlloc - Generate the code for allocating an object in the 371 /// current frame. The sequence of code with be in the general form 372 /// 373 /// addi R0, SP, \#frameSize ; get the address of the previous frame 374 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size 375 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation 376 /// 377 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II, 378 int SPAdj, RegScavenger *RS) const { 379 // Get the instruction. 380 MachineInstr &MI = *II; 381 // Get the instruction's basic block. 382 MachineBasicBlock &MBB = *MI.getParent(); 383 // Get the basic block's function. 384 MachineFunction &MF = *MBB.getParent(); 385 // Get the frame info. 386 MachineFrameInfo *MFI = MF.getFrameInfo(); 387 // Determine whether 64-bit pointers are used. 388 bool LP64 = Subtarget.isPPC64(); 389 DebugLoc dl = MI.getDebugLoc(); 390 391 // Get the maximum call stack size. 392 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 393 // Get the total frame size. 394 unsigned FrameSize = MFI->getStackSize(); 395 396 // Get stack alignments. 397 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 398 unsigned MaxAlign = MFI->getMaxAlignment(); 399 if (MaxAlign > TargetAlign) 400 report_fatal_error("Dynamic alloca with large aligns not supported"); 401 402 // Determine the previous frame's address. If FrameSize can't be 403 // represented as 16 bits or we need special alignment, then we load the 404 // previous frame's address from 0(SP). Why not do an addis of the hi? 405 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. 406 // Constructing the constant and adding would take 3 instructions. 407 // Fortunately, a frame greater than 32K is rare. 408 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 409 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 410 const TargetRegisterClass *RC = LP64 ? G8RC : GPRC; 411 412 // FIXME (64-bit): Use "findScratchRegister" 413 unsigned Reg; 414 if (requiresRegisterScavenging(MF)) 415 Reg = findScratchRegister(II, RS, RC, SPAdj); 416 else 417 Reg = PPC::R0; 418 419 if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) { 420 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) 421 .addReg(PPC::R31) 422 .addImm(FrameSize); 423 } else if (LP64) { 424 if (requiresRegisterScavenging(MF)) // FIXME (64-bit): Use "true" part. 425 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg) 426 .addImm(0) 427 .addReg(PPC::X1); 428 else 429 BuildMI(MBB, II, dl, TII.get(PPC::LD), PPC::X0) 430 .addImm(0) 431 .addReg(PPC::X1); 432 } else { 433 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) 434 .addImm(0) 435 .addReg(PPC::R1); 436 } 437 438 // Grow the stack and update the stack pointer link, then determine the 439 // address of new allocated space. 440 if (LP64) { 441 if (requiresRegisterScavenging(MF)) // FIXME (64-bit): Use "true" part. 442 BuildMI(MBB, II, dl, TII.get(PPC::STDUX)) 443 .addReg(Reg, RegState::Kill) 444 .addReg(PPC::X1) 445 .addReg(MI.getOperand(1).getReg()); 446 else 447 BuildMI(MBB, II, dl, TII.get(PPC::STDUX)) 448 .addReg(PPC::X0, RegState::Kill) 449 .addReg(PPC::X1) 450 .addReg(MI.getOperand(1).getReg()); 451 452 if (!MI.getOperand(1).isKill()) 453 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 454 .addReg(PPC::X1) 455 .addImm(maxCallFrameSize); 456 else 457 // Implicitly kill the register. 458 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 459 .addReg(PPC::X1) 460 .addImm(maxCallFrameSize) 461 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill); 462 } else { 463 BuildMI(MBB, II, dl, TII.get(PPC::STWUX)) 464 .addReg(Reg, RegState::Kill) 465 .addReg(PPC::R1) 466 .addReg(MI.getOperand(1).getReg()); 467 468 if (!MI.getOperand(1).isKill()) 469 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 470 .addReg(PPC::R1) 471 .addImm(maxCallFrameSize); 472 else 473 // Implicitly kill the register. 474 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 475 .addReg(PPC::R1) 476 .addImm(maxCallFrameSize) 477 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill); 478 } 479 480 // Discard the DYNALLOC instruction. 481 MBB.erase(II); 482 } 483 484 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of 485 /// reserving a whole register (R0), we scrounge for one here. This generates 486 /// code like this: 487 /// 488 /// mfcr rA ; Move the conditional register into GPR rA. 489 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot. 490 /// stw rA, FI ; Store rA to the frame. 491 /// 492 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, 493 unsigned FrameIndex, int SPAdj, 494 RegScavenger *RS) const { 495 // Get the instruction. 496 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>, <FI> 497 // Get the instruction's basic block. 498 MachineBasicBlock &MBB = *MI.getParent(); 499 DebugLoc dl = MI.getDebugLoc(); 500 501 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 502 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 503 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC; 504 unsigned Reg = findScratchRegister(II, RS, RC, SPAdj); 505 unsigned SrcReg = MI.getOperand(0).getReg(); 506 507 // We need to store the CR in the low 4-bits of the saved value. First, issue 508 // an MFCRpsued to save all of the CRBits and, if needed, kill the SrcReg. 509 BuildMI(MBB, II, dl, TII.get(PPC::MFCRpseud), Reg) 510 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 511 512 // If the saved register wasn't CR0, shift the bits left so that they are in 513 // CR0's slot. 514 if (SrcReg != PPC::CR0) 515 // rlwinm rA, rA, ShiftBits, 0, 31. 516 BuildMI(MBB, II, dl, TII.get(PPC::RLWINM), Reg) 517 .addReg(Reg, RegState::Kill) 518 .addImm(PPCRegisterInfo::getRegisterNumbering(SrcReg) * 4) 519 .addImm(0) 520 .addImm(31); 521 522 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::STW)) 523 .addReg(Reg, getKillRegState(MI.getOperand(1).getImm())), 524 FrameIndex); 525 526 // Discard the pseudo instruction. 527 MBB.erase(II); 528 } 529 530 void 531 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 532 int SPAdj, RegScavenger *RS) const { 533 assert(SPAdj == 0 && "Unexpected"); 534 535 // Get the instruction. 536 MachineInstr &MI = *II; 537 // Get the instruction's basic block. 538 MachineBasicBlock &MBB = *MI.getParent(); 539 // Get the basic block's function. 540 MachineFunction &MF = *MBB.getParent(); 541 // Get the frame info. 542 MachineFrameInfo *MFI = MF.getFrameInfo(); 543 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo(); 544 DebugLoc dl = MI.getDebugLoc(); 545 546 // Find out which operand is the frame index. 547 unsigned FIOperandNo = 0; 548 while (!MI.getOperand(FIOperandNo).isFI()) { 549 ++FIOperandNo; 550 assert(FIOperandNo != MI.getNumOperands() && 551 "Instr doesn't have FrameIndex operand!"); 552 } 553 // Take into account whether it's an add or mem instruction 554 unsigned OffsetOperandNo = (FIOperandNo == 2) ? 1 : 2; 555 if (MI.isInlineAsm()) 556 OffsetOperandNo = FIOperandNo-1; 557 558 // Get the frame index. 559 int FrameIndex = MI.getOperand(FIOperandNo).getIndex(); 560 561 // Get the frame pointer save index. Users of this index are primarily 562 // DYNALLOC instructions. 563 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 564 int FPSI = FI->getFramePointerSaveIndex(); 565 // Get the instruction opcode. 566 unsigned OpC = MI.getOpcode(); 567 568 // Special case for dynamic alloca. 569 if (FPSI && FrameIndex == FPSI && 570 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { 571 lowerDynamicAlloc(II, SPAdj, RS); 572 return; 573 } 574 575 // Special case for pseudo-op SPILL_CR. 576 if (requiresRegisterScavenging(MF)) // FIXME (64-bit): Enable by default. 577 if (OpC == PPC::SPILL_CR) { 578 lowerCRSpilling(II, FrameIndex, SPAdj, RS); 579 return; 580 } 581 582 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 583 MI.getOperand(FIOperandNo).ChangeToRegister(TFI->hasFP(MF) ? 584 PPC::R31 : PPC::R1, 585 false); 586 587 // Figure out if the offset in the instruction is shifted right two bits. This 588 // is true for instructions like "STD", which the machine implicitly adds two 589 // low zeros to. 590 bool isIXAddr = false; 591 switch (OpC) { 592 case PPC::LWA: 593 case PPC::LD: 594 case PPC::STD: 595 case PPC::STD_32: 596 isIXAddr = true; 597 break; 598 } 599 600 // Now add the frame object offset to the offset from r1. 601 int Offset = MFI->getObjectOffset(FrameIndex); 602 if (!isIXAddr) 603 Offset += MI.getOperand(OffsetOperandNo).getImm(); 604 else 605 Offset += MI.getOperand(OffsetOperandNo).getImm() << 2; 606 607 // If we're not using a Frame Pointer that has been set to the value of the 608 // SP before having the stack size subtracted from it, then add the stack size 609 // to Offset to get the correct offset. 610 // Naked functions have stack size 0, although getStackSize may not reflect that 611 // because we didn't call all the pieces that compute it for naked functions. 612 if (!MF.getFunction()->hasFnAttr(Attribute::Naked)) 613 Offset += MFI->getStackSize(); 614 615 // If we can, encode the offset directly into the instruction. If this is a 616 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If 617 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits 618 // clear can be encoded. This is extremely uncommon, because normally you 619 // only "std" to a stack slot that is at least 4-byte aligned, but it can 620 // happen in invalid code. 621 if (isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0)) { 622 if (isIXAddr) 623 Offset >>= 2; // The actual encoded value has the low two bits zero. 624 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 625 return; 626 } 627 628 // The offset doesn't fit into a single register, scavenge one to build the 629 // offset in. 630 // FIXME: figure out what SPAdj is doing here. 631 632 // FIXME (64-bit): Use "findScratchRegister". 633 unsigned SReg; 634 if (requiresRegisterScavenging(MF)) 635 SReg = findScratchRegister(II, RS, &PPC::GPRCRegClass, SPAdj); 636 else 637 SReg = PPC::R0; 638 639 // Insert a set of rA with the full offset value before the ld, st, or add 640 BuildMI(MBB, II, dl, TII.get(PPC::LIS), SReg) 641 .addImm(Offset >> 16); 642 BuildMI(MBB, II, dl, TII.get(PPC::ORI), SReg) 643 .addReg(SReg, RegState::Kill) 644 .addImm(Offset); 645 646 // Convert into indexed form of the instruction: 647 // 648 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 649 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 650 unsigned OperandBase; 651 652 if (OpC != TargetOpcode::INLINEASM) { 653 assert(ImmToIdxMap.count(OpC) && 654 "No indexed form of load or store available!"); 655 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; 656 MI.setDesc(TII.get(NewOpcode)); 657 OperandBase = 1; 658 } else { 659 OperandBase = OffsetOperandNo; 660 } 661 662 unsigned StackReg = MI.getOperand(FIOperandNo).getReg(); 663 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false); 664 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false); 665 } 666 667 unsigned PPCRegisterInfo::getRARegister() const { 668 return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8; 669 } 670 671 unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 672 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo(); 673 674 if (!Subtarget.isPPC64()) 675 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1; 676 else 677 return TFI->hasFP(MF) ? PPC::X31 : PPC::X1; 678 } 679 680 unsigned PPCRegisterInfo::getEHExceptionRegister() const { 681 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3; 682 } 683 684 unsigned PPCRegisterInfo::getEHHandlerRegister() const { 685 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4; 686 } 687 688 int PPCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { 689 // FIXME: Most probably dwarf numbers differs for Linux and Darwin 690 return PPCGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); 691 } 692 693 #include "PPCGenRegisterInfo.inc" 694