1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file was developed by the LLVM research group and is distributed under 6 // the University of Illinois Open Source License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the MRegisterInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #define DEBUG_TYPE "reginfo" 15 #include "PPC.h" 16 #include "PPCInstrBuilder.h" 17 #include "PPCRegisterInfo.h" 18 #include "PPCSubtarget.h" 19 #include "llvm/Constants.h" 20 #include "llvm/Type.h" 21 #include "llvm/CodeGen/ValueTypes.h" 22 #include "llvm/CodeGen/MachineInstrBuilder.h" 23 #include "llvm/CodeGen/MachineDebugInfo.h" 24 #include "llvm/CodeGen/MachineFunction.h" 25 #include "llvm/CodeGen/MachineFrameInfo.h" 26 #include "llvm/CodeGen/MachineLocation.h" 27 #include "llvm/CodeGen/SelectionDAGNodes.h" 28 #include "llvm/Target/TargetFrameInfo.h" 29 #include "llvm/Target/TargetInstrInfo.h" 30 #include "llvm/Target/TargetMachine.h" 31 #include "llvm/Target/TargetOptions.h" 32 #include "llvm/Support/CommandLine.h" 33 #include "llvm/Support/Debug.h" 34 #include "llvm/Support/MathExtras.h" 35 #include "llvm/ADT/STLExtras.h" 36 #include <cstdlib> 37 #include <iostream> 38 using namespace llvm; 39 40 /// getRegisterNumbering - Given the enum value for some register, e.g. 41 /// PPC::F14, return the number that it corresponds to (e.g. 14). 42 unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) { 43 using namespace PPC; 44 switch (RegEnum) { 45 case R0 : case X0 : case F0 : case V0 : case CR0: return 0; 46 case R1 : case X1 : case F1 : case V1 : case CR1: return 1; 47 case R2 : case X2 : case F2 : case V2 : case CR2: return 2; 48 case R3 : case X3 : case F3 : case V3 : case CR3: return 3; 49 case R4 : case X4 : case F4 : case V4 : case CR4: return 4; 50 case R5 : case X5 : case F5 : case V5 : case CR5: return 5; 51 case R6 : case X6 : case F6 : case V6 : case CR6: return 6; 52 case R7 : case X7 : case F7 : case V7 : case CR7: return 7; 53 case R8 : case X8 : case F8 : case V8 : return 8; 54 case R9 : case X9 : case F9 : case V9 : return 9; 55 case R10: case X10: case F10: case V10: return 10; 56 case R11: case X11: case F11: case V11: return 11; 57 case R12: case X12: case F12: case V12: return 12; 58 case R13: case X13: case F13: case V13: return 13; 59 case R14: case X14: case F14: case V14: return 14; 60 case R15: case X15: case F15: case V15: return 15; 61 case R16: case X16: case F16: case V16: return 16; 62 case R17: case X17: case F17: case V17: return 17; 63 case R18: case X18: case F18: case V18: return 18; 64 case R19: case X19: case F19: case V19: return 19; 65 case R20: case X20: case F20: case V20: return 20; 66 case R21: case X21: case F21: case V21: return 21; 67 case R22: case X22: case F22: case V22: return 22; 68 case R23: case X23: case F23: case V23: return 23; 69 case R24: case X24: case F24: case V24: return 24; 70 case R25: case X25: case F25: case V25: return 25; 71 case R26: case X26: case F26: case V26: return 26; 72 case R27: case X27: case F27: case V27: return 27; 73 case R28: case X28: case F28: case V28: return 28; 74 case R29: case X29: case F29: case V29: return 29; 75 case R30: case X30: case F30: case V30: return 30; 76 case R31: case X31: case F31: case V31: return 31; 77 default: 78 std::cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n"; 79 abort(); 80 } 81 } 82 83 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST) 84 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP), 85 Subtarget(ST) { 86 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 87 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 88 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 89 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 90 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 91 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 92 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 93 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 94 } 95 96 void 97 PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 98 MachineBasicBlock::iterator MI, 99 unsigned SrcReg, int FrameIdx, 100 const TargetRegisterClass *RC) const { 101 if (SrcReg == PPC::LR) { 102 // FIXME: this spills LR immediately to memory in one step. To do this, we 103 // use R11, which we know cannot be used in the prolog/epilog. This is a 104 // hack. 105 BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11); 106 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx); 107 } else if (RC == PPC::CRRCRegisterClass) { 108 // FIXME: We use R0 here, because it isn't available for RA. 109 // We need to store the CR in the low 4-bits of the saved value. First, 110 // issue a MFCR to save all of the CRBits. 111 BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R0); 112 113 // If the saved register wasn't CR0, shift the bits left so that they are in 114 // CR0's slot. 115 if (SrcReg != PPC::CR0) { 116 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4; 117 // rlwinm r0, r0, ShiftBits, 0, 31. 118 BuildMI(MBB, MI, PPC::RLWINM, 4, PPC::R0) 119 .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31); 120 } 121 122 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R0), FrameIdx); 123 } else if (RC == PPC::GPRCRegisterClass) { 124 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(SrcReg),FrameIdx); 125 } else if (RC == PPC::G8RCRegisterClass) { 126 addFrameReference(BuildMI(MBB, MI, PPC::STD, 3).addReg(SrcReg),FrameIdx); 127 } else if (RC == PPC::F8RCRegisterClass) { 128 addFrameReference(BuildMI(MBB, MI, PPC::STFD, 3).addReg(SrcReg),FrameIdx); 129 } else if (RC == PPC::F4RCRegisterClass) { 130 addFrameReference(BuildMI(MBB, MI, PPC::STFS, 3).addReg(SrcReg),FrameIdx); 131 } else if (RC == PPC::VRRCRegisterClass) { 132 // We don't have indexed addressing for vector loads. Emit: 133 // R11 = ADDI FI# 134 // Dest = LVX R0, R11 135 // 136 // FIXME: We use R0 here, because it isn't available for RA. 137 addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0); 138 BuildMI(MBB, MI, PPC::STVX, 3) 139 .addReg(SrcReg).addReg(PPC::R0).addReg(PPC::R0); 140 } else { 141 assert(0 && "Unknown regclass!"); 142 abort(); 143 } 144 } 145 146 void 147 PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 148 MachineBasicBlock::iterator MI, 149 unsigned DestReg, int FrameIdx, 150 const TargetRegisterClass *RC) const { 151 if (DestReg == PPC::LR) { 152 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx); 153 BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11); 154 } else if (RC == PPC::CRRCRegisterClass) { 155 // FIXME: We use R0 here, because it isn't available for RA. 156 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R0), FrameIdx); 157 158 // If the reloaded register isn't CR0, shift the bits right so that they are 159 // in the right CR's slot. 160 if (DestReg != PPC::CR0) { 161 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4; 162 // rlwinm r11, r11, 32-ShiftBits, 0, 31. 163 BuildMI(MBB, MI, PPC::RLWINM, 4, PPC::R0) 164 .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31); 165 } 166 167 BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R0); 168 } else if (RC == PPC::GPRCRegisterClass) { 169 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, DestReg), FrameIdx); 170 } else if (RC == PPC::G8RCRegisterClass) { 171 addFrameReference(BuildMI(MBB, MI, PPC::LD, 2, DestReg), FrameIdx); 172 } else if (RC == PPC::F8RCRegisterClass) { 173 addFrameReference(BuildMI(MBB, MI, PPC::LFD, 2, DestReg), FrameIdx); 174 } else if (RC == PPC::F4RCRegisterClass) { 175 addFrameReference(BuildMI(MBB, MI, PPC::LFS, 2, DestReg), FrameIdx); 176 } else if (RC == PPC::VRRCRegisterClass) { 177 // We don't have indexed addressing for vector loads. Emit: 178 // R11 = ADDI FI# 179 // Dest = LVX R0, R11 180 // 181 // FIXME: We use R0 here, because it isn't available for RA. 182 addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0); 183 BuildMI(MBB, MI, PPC::LVX, 2, DestReg).addReg(PPC::R0).addReg(PPC::R0); 184 } else { 185 assert(0 && "Unknown regclass!"); 186 abort(); 187 } 188 } 189 190 void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, 191 MachineBasicBlock::iterator MI, 192 unsigned DestReg, unsigned SrcReg, 193 const TargetRegisterClass *RC) const { 194 if (RC == PPC::GPRCRegisterClass) { 195 BuildMI(MBB, MI, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg); 196 } else if (RC == PPC::G8RCRegisterClass) { 197 BuildMI(MBB, MI, PPC::OR8, 2, DestReg).addReg(SrcReg).addReg(SrcReg); 198 } else if (RC == PPC::F4RCRegisterClass) { 199 BuildMI(MBB, MI, PPC::FMRS, 1, DestReg).addReg(SrcReg); 200 } else if (RC == PPC::F8RCRegisterClass) { 201 BuildMI(MBB, MI, PPC::FMRD, 1, DestReg).addReg(SrcReg); 202 } else if (RC == PPC::CRRCRegisterClass) { 203 BuildMI(MBB, MI, PPC::MCRF, 1, DestReg).addReg(SrcReg); 204 } else if (RC == PPC::VRRCRegisterClass) { 205 BuildMI(MBB, MI, PPC::VOR, 2, DestReg).addReg(SrcReg).addReg(SrcReg); 206 } else { 207 std::cerr << "Attempt to copy register that is not GPR or FPR"; 208 abort(); 209 } 210 } 211 212 const unsigned* PPCRegisterInfo::getCalleeSaveRegs() const { 213 // 32-bit Darwin calling convention. 214 static const unsigned Darwin32_CalleeSaveRegs[] = { 215 PPC::R1 , PPC::R13, PPC::R14, PPC::R15, 216 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 217 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 218 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 219 PPC::R28, PPC::R29, PPC::R30, PPC::R31, 220 221 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 222 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 223 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 224 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 225 PPC::F30, PPC::F31, 226 227 PPC::CR2, PPC::CR3, PPC::CR4, 228 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 229 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 230 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 231 232 PPC::LR, 0 233 }; 234 // 64-bit Darwin calling convention. 235 static const unsigned Darwin64_CalleeSaveRegs[] = { 236 PPC::X1 , PPC::X13, PPC::X14, PPC::X15, 237 PPC::X16, PPC::X17, PPC::X18, PPC::X19, 238 PPC::X20, PPC::X21, PPC::X22, PPC::X23, 239 PPC::X24, PPC::X25, PPC::X26, PPC::X27, 240 PPC::X28, PPC::X29, PPC::X30, PPC::X31, 241 242 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 243 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 244 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 245 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 246 PPC::F30, PPC::F31, 247 248 PPC::CR2, PPC::CR3, PPC::CR4, 249 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 250 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 251 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 252 253 PPC::LR, 0 254 }; 255 256 return Subtarget.isPPC64() ? Darwin64_CalleeSaveRegs : 257 Darwin32_CalleeSaveRegs; 258 } 259 260 const TargetRegisterClass* const* 261 PPCRegisterInfo::getCalleeSaveRegClasses() const { 262 // 32-bit Darwin calling convention. 263 static const TargetRegisterClass * const Darwin32_CalleeSaveRegClasses[] = { 264 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 265 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 266 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 267 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 268 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 269 270 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 271 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 272 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 273 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 274 &PPC::F8RCRegClass,&PPC::F8RCRegClass, 275 276 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, 277 278 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 279 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 280 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 281 282 &PPC::GPRCRegClass, 0 283 }; 284 285 // 64-bit Darwin calling convention. 286 static const TargetRegisterClass * const Darwin64_CalleeSaveRegClasses[] = { 287 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 288 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 289 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 290 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 291 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 292 293 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 294 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 295 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 296 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 297 &PPC::F8RCRegClass,&PPC::F8RCRegClass, 298 299 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, 300 301 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 302 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 303 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 304 305 &PPC::GPRCRegClass, 0 306 }; 307 308 return Subtarget.isPPC64() ? Darwin64_CalleeSaveRegClasses : 309 Darwin32_CalleeSaveRegClasses; 310 } 311 312 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into 313 /// copy instructions, turning them into load/store instructions. 314 MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI, 315 unsigned OpNum, 316 int FrameIndex) const { 317 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because 318 // it takes more than one instruction to store it. 319 unsigned Opc = MI->getOpcode(); 320 321 if ((Opc == PPC::OR && 322 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { 323 if (OpNum == 0) { // move -> store 324 unsigned InReg = MI->getOperand(1).getReg(); 325 return addFrameReference(BuildMI(PPC::STW, 326 3).addReg(InReg), FrameIndex); 327 } else { // move -> load 328 unsigned OutReg = MI->getOperand(0).getReg(); 329 return addFrameReference(BuildMI(PPC::LWZ, 2, OutReg), FrameIndex); 330 } 331 } else if ((Opc == PPC::OR8 && 332 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { 333 if (OpNum == 0) { // move -> store 334 unsigned InReg = MI->getOperand(1).getReg(); 335 return addFrameReference(BuildMI(PPC::STD, 336 3).addReg(InReg), FrameIndex); 337 } else { // move -> load 338 unsigned OutReg = MI->getOperand(0).getReg(); 339 return addFrameReference(BuildMI(PPC::LD, 2, OutReg), FrameIndex); 340 } 341 } else if (Opc == PPC::FMRD) { 342 if (OpNum == 0) { // move -> store 343 unsigned InReg = MI->getOperand(1).getReg(); 344 return addFrameReference(BuildMI(PPC::STFD, 345 3).addReg(InReg), FrameIndex); 346 } else { // move -> load 347 unsigned OutReg = MI->getOperand(0).getReg(); 348 return addFrameReference(BuildMI(PPC::LFD, 2, OutReg), FrameIndex); 349 } 350 } else if (Opc == PPC::FMRS) { 351 if (OpNum == 0) { // move -> store 352 unsigned InReg = MI->getOperand(1).getReg(); 353 return addFrameReference(BuildMI(PPC::STFS, 354 3).addReg(InReg), FrameIndex); 355 } else { // move -> load 356 unsigned OutReg = MI->getOperand(0).getReg(); 357 return addFrameReference(BuildMI(PPC::LFS, 2, OutReg), FrameIndex); 358 } 359 } 360 return 0; 361 } 362 363 //===----------------------------------------------------------------------===// 364 // Stack Frame Processing methods 365 //===----------------------------------------------------------------------===// 366 367 // hasFP - Return true if the specified function should have a dedicated frame 368 // pointer register. This is true if the function has variable sized allocas or 369 // if frame pointer elimination is disabled. 370 // 371 static bool hasFP(const MachineFunction &MF) { 372 const MachineFrameInfo *MFI = MF.getFrameInfo(); 373 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 374 375 // If frame pointers are forced, or if there are variable sized stack objects, 376 // use a frame pointer. 377 // 378 return NoFramePointerElim || MFI->hasVarSizedObjects(); 379 } 380 381 void PPCRegisterInfo:: 382 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 383 MachineBasicBlock::iterator I) const { 384 if (hasFP(MF)) { 385 // If we have a frame pointer, convert as follows: 386 // ADJCALLSTACKDOWN -> addi, r1, r1, -amount 387 // ADJCALLSTACKUP -> addi, r1, r1, amount 388 MachineInstr *Old = I; 389 unsigned Amount = Old->getOperand(0).getImmedValue(); 390 if (Amount != 0) { 391 // We need to keep the stack aligned properly. To do this, we round the 392 // amount of space needed for the outgoing arguments up to the next 393 // alignment boundary. 394 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 395 Amount = (Amount+Align-1)/Align*Align; 396 397 // Replace the pseudo instruction with a new instruction... 398 if (Old->getOpcode() == PPC::ADJCALLSTACKDOWN) { 399 BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addImm(-Amount); 400 } else { 401 assert(Old->getOpcode() == PPC::ADJCALLSTACKUP); 402 BuildMI(MBB, I, PPC::ADDI, 2, PPC::R1).addReg(PPC::R1).addImm(Amount); 403 } 404 } 405 } 406 MBB.erase(I); 407 } 408 409 void 410 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { 411 unsigned i = 0; 412 MachineInstr &MI = *II; 413 MachineBasicBlock &MBB = *MI.getParent(); 414 MachineFunction &MF = *MBB.getParent(); 415 416 while (!MI.getOperand(i).isFrameIndex()) { 417 ++i; 418 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 419 } 420 421 int FrameIndex = MI.getOperand(i).getFrameIndex(); 422 423 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 424 MI.getOperand(i).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1); 425 426 // Take into account whether it's an add or mem instruction 427 unsigned OffIdx = (i == 2) ? 1 : 2; 428 429 // Figure out if the offset in the instruction is shifted right two bits. This 430 // is true for instructions like "STD", which the machine implicitly adds two 431 // low zeros to. 432 bool isIXAddr = false; 433 switch (MI.getOpcode()) { 434 case PPC::LWA: 435 case PPC::LD: 436 case PPC::STD: 437 case PPC::STD_32: 438 isIXAddr = true; 439 break; 440 } 441 442 443 // Now add the frame object offset to the offset from r1. 444 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex); 445 446 if (!isIXAddr) 447 Offset += MI.getOperand(OffIdx).getImmedValue(); 448 else 449 Offset += MI.getOperand(OffIdx).getImmedValue() << 2; 450 451 // If we're not using a Frame Pointer that has been set to the value of the 452 // SP before having the stack size subtracted from it, then add the stack size 453 // to Offset to get the correct offset. 454 Offset += MF.getFrameInfo()->getStackSize(); 455 456 if (Offset > 32767 || Offset < -32768) { 457 // Insert a set of r0 with the full offset value before the ld, st, or add 458 MachineBasicBlock *MBB = MI.getParent(); 459 BuildMI(*MBB, II, PPC::LIS, 1, PPC::R0).addImm(Offset >> 16); 460 BuildMI(*MBB, II, PPC::ORI, 2, PPC::R0).addReg(PPC::R0).addImm(Offset); 461 462 // convert into indexed form of the instruction 463 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 464 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 465 assert(ImmToIdxMap.count(MI.getOpcode()) && 466 "No indexed form of load or store available!"); 467 unsigned NewOpcode = ImmToIdxMap.find(MI.getOpcode())->second; 468 MI.setOpcode(NewOpcode); 469 MI.getOperand(1).ChangeToRegister(MI.getOperand(i).getReg()); 470 MI.getOperand(2).ChangeToRegister(PPC::R0); 471 } else { 472 if (isIXAddr) { 473 assert((Offset & 3) == 0 && "Invalid frame offset!"); 474 Offset >>= 2; // The actual encoded value has the low two bits zero. 475 } 476 MI.getOperand(OffIdx).ChangeToImmediate(Offset); 477 } 478 } 479 480 /// VRRegNo - Map from a numbered VR register to its enum value. 481 /// 482 static const unsigned short VRRegNo[] = { 483 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 , 484 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, 485 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, 486 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31 487 }; 488 489 /// RemoveVRSaveCode - We have found that this function does not need any code 490 /// to manipulate the VRSAVE register, even though it uses vector registers. 491 /// This can happen when the only registers used are known to be live in or out 492 /// of the function. Remove all of the VRSAVE related code from the function. 493 static void RemoveVRSaveCode(MachineInstr *MI) { 494 MachineBasicBlock *Entry = MI->getParent(); 495 MachineFunction *MF = Entry->getParent(); 496 497 // We know that the MTVRSAVE instruction immediately follows MI. Remove it. 498 MachineBasicBlock::iterator MBBI = MI; 499 ++MBBI; 500 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE); 501 MBBI->eraseFromParent(); 502 503 bool RemovedAllMTVRSAVEs = true; 504 // See if we can find and remove the MTVRSAVE instruction from all of the 505 // epilog blocks. 506 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); 507 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) { 508 // If last instruction is a return instruction, add an epilogue 509 if (!I->empty() && TII.isReturn(I->back().getOpcode())) { 510 bool FoundIt = false; 511 for (MBBI = I->end(); MBBI != I->begin(); ) { 512 --MBBI; 513 if (MBBI->getOpcode() == PPC::MTVRSAVE) { 514 MBBI->eraseFromParent(); // remove it. 515 FoundIt = true; 516 break; 517 } 518 } 519 RemovedAllMTVRSAVEs &= FoundIt; 520 } 521 } 522 523 // If we found and removed all MTVRSAVE instructions, remove the read of 524 // VRSAVE as well. 525 if (RemovedAllMTVRSAVEs) { 526 MBBI = MI; 527 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?"); 528 --MBBI; 529 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?"); 530 MBBI->eraseFromParent(); 531 } 532 533 // Finally, nuke the UPDATE_VRSAVE. 534 MI->eraseFromParent(); 535 } 536 537 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the 538 // instruction selector. Based on the vector registers that have been used, 539 // transform this into the appropriate ORI instruction. 540 static void HandleVRSaveUpdate(MachineInstr *MI, const bool *UsedRegs) { 541 unsigned UsedRegMask = 0; 542 for (unsigned i = 0; i != 32; ++i) 543 if (UsedRegs[VRRegNo[i]]) 544 UsedRegMask |= 1 << (31-i); 545 546 // Live in and live out values already must be in the mask, so don't bother 547 // marking them. 548 MachineFunction *MF = MI->getParent()->getParent(); 549 for (MachineFunction::livein_iterator I = 550 MF->livein_begin(), E = MF->livein_end(); I != E; ++I) { 551 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first); 552 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg. 553 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 554 } 555 for (MachineFunction::liveout_iterator I = 556 MF->liveout_begin(), E = MF->liveout_end(); I != E; ++I) { 557 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I); 558 if (VRRegNo[RegNo] == *I) // If this really is a vector reg. 559 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 560 } 561 562 unsigned SrcReg = MI->getOperand(1).getReg(); 563 unsigned DstReg = MI->getOperand(0).getReg(); 564 // If no registers are used, turn this into a copy. 565 if (UsedRegMask == 0) { 566 // Remove all VRSAVE code. 567 RemoveVRSaveCode(MI); 568 return; 569 } else if ((UsedRegMask & 0xFFFF) == UsedRegMask) { 570 BuildMI(*MI->getParent(), MI, PPC::ORI, 2, DstReg) 571 .addReg(SrcReg).addImm(UsedRegMask); 572 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { 573 BuildMI(*MI->getParent(), MI, PPC::ORIS, 2, DstReg) 574 .addReg(SrcReg).addImm(UsedRegMask >> 16); 575 } else { 576 BuildMI(*MI->getParent(), MI, PPC::ORIS, 2, DstReg) 577 .addReg(SrcReg).addImm(UsedRegMask >> 16); 578 BuildMI(*MI->getParent(), MI, PPC::ORI, 2, DstReg) 579 .addReg(DstReg).addImm(UsedRegMask & 0xFFFF); 580 } 581 582 // Remove the old UPDATE_VRSAVE instruction. 583 MI->eraseFromParent(); 584 } 585 586 587 void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const { 588 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB 589 MachineBasicBlock::iterator MBBI = MBB.begin(); 590 MachineFrameInfo *MFI = MF.getFrameInfo(); 591 MachineDebugInfo *DebugInfo = MFI->getMachineDebugInfo(); 592 593 // Do we have a frame pointer for this function? 594 bool HasFP = hasFP(MF); 595 596 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it, 597 // process it. 598 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { 599 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) { 600 HandleVRSaveUpdate(MBBI, MF.getUsedPhysregs()); 601 break; 602 } 603 } 604 605 // Move MBBI back to the beginning of the function. 606 MBBI = MBB.begin(); 607 608 // Get the number of bytes to allocate from the FrameInfo 609 unsigned NumBytes = MFI->getStackSize(); 610 611 // Get the alignments provided by the target, and the maximum alignment 612 // (if any) of the fixed frame objects. 613 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 614 unsigned MaxAlign = MFI->getMaxAlignment(); 615 616 // If we have calls, we cannot use the red zone to store callee save registers 617 // and we must set up a stack frame, so calculate the necessary size here. 618 if (MFI->hasCalls()) { 619 // We reserve argument space for call sites in the function immediately on 620 // entry to the current function. This eliminates the need for add/sub 621 // brackets around call sites. 622 NumBytes += MFI->getMaxCallFrameSize(); 623 } 624 625 // If we are a leaf function, and use up to 224 bytes of stack space, 626 // and don't have a frame pointer, then we do not need to adjust the stack 627 // pointer (we fit in the Red Zone). 628 if ((NumBytes == 0) || (NumBytes <= 224 && !HasFP && !MFI->hasCalls() && 629 MaxAlign <= TargetAlign)) { 630 MFI->setStackSize(0); 631 return; 632 } 633 634 // Add the size of R1 to NumBytes size for the store of R1 to the bottom 635 // of the stack and round the size to a multiple of the alignment. 636 unsigned Align = std::max(TargetAlign, MaxAlign); 637 unsigned GPRSize = 4; 638 unsigned Size = HasFP ? GPRSize + GPRSize : GPRSize; 639 NumBytes = (NumBytes+Size+Align-1)/Align*Align; 640 641 // Update frame info to pretend that this is part of the stack... 642 MFI->setStackSize(NumBytes); 643 int NegNumbytes = -NumBytes; 644 645 // Adjust stack pointer: r1 -= numbytes. 646 // If there is a preferred stack alignment, align R1 now 647 if (MaxAlign > TargetAlign) { 648 assert(isPowerOf2_32(MaxAlign) && MaxAlign < 32767 && "Invalid alignment!"); 649 assert(isInt16(0-NumBytes) && "Unhandled stack size and alignment!"); 650 BuildMI(MBB, MBBI, PPC::RLWINM, 4, PPC::R0) 651 .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31); 652 BuildMI(MBB, MBBI, PPC::SUBFIC,2,PPC::R0).addReg(PPC::R0) 653 .addImm(0-NumBytes); 654 BuildMI(MBB, MBBI, PPC::STWUX, 3) 655 .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0); 656 } else if (NumBytes <= 32768) { 657 BuildMI(MBB, MBBI, PPC::STWU, 3).addReg(PPC::R1).addImm(NegNumbytes) 658 .addReg(PPC::R1); 659 } else { 660 BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addImm(NegNumbytes >> 16); 661 BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0).addReg(PPC::R0) 662 .addImm(NegNumbytes & 0xFFFF); 663 BuildMI(MBB, MBBI, PPC::STWUX, 3).addReg(PPC::R1).addReg(PPC::R1) 664 .addReg(PPC::R0); 665 } 666 667 if (DebugInfo && DebugInfo->hasInfo()) { 668 std::vector<MachineMove *> &Moves = DebugInfo->getFrameMoves(); 669 unsigned LabelID = DebugInfo->NextLabelID(); 670 671 // Show update of SP. 672 MachineLocation Dst(MachineLocation::VirtualFP); 673 MachineLocation Src(MachineLocation::VirtualFP, NegNumbytes); 674 Moves.push_back(new MachineMove(LabelID, Dst, Src)); 675 676 BuildMI(MBB, MBBI, PPC::DWARF_LABEL, 1).addImm(LabelID); 677 } 678 679 // If there is a frame pointer, copy R1 (SP) into R31 (FP) 680 if (HasFP) { 681 BuildMI(MBB, MBBI, PPC::STW, 3) 682 .addReg(PPC::R31).addImm(GPRSize).addReg(PPC::R1); 683 BuildMI(MBB, MBBI, PPC::OR, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1); 684 } 685 } 686 687 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF, 688 MachineBasicBlock &MBB) const { 689 MachineBasicBlock::iterator MBBI = prior(MBB.end()); 690 assert(MBBI->getOpcode() == PPC::BLR && 691 "Can only insert epilog into returning blocks"); 692 693 // Get alignment info so we know how to restore r1 694 const MachineFrameInfo *MFI = MF.getFrameInfo(); 695 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 696 697 // Get the number of bytes allocated from the FrameInfo. 698 unsigned NumBytes = MFI->getStackSize(); 699 unsigned GPRSize = 4; 700 701 if (NumBytes != 0) { 702 // If this function has a frame pointer, load the saved stack pointer from 703 // its stack slot. 704 if (hasFP(MF)) { 705 BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R31) 706 .addImm(GPRSize).addReg(PPC::R31); 707 } 708 709 // The loaded (or persistent) stack pointer value is offseted by the 'stwu' 710 // on entry to the function. Add this offset back now. 711 if (NumBytes < 32768 && TargetAlign >= MFI->getMaxAlignment()) { 712 BuildMI(MBB, MBBI, PPC::ADDI, 2, PPC::R1) 713 .addReg(PPC::R1).addImm(NumBytes); 714 } else { 715 BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R1).addImm(0).addReg(PPC::R1); 716 } 717 } 718 } 719 720 unsigned PPCRegisterInfo::getRARegister() const { 721 return PPC::LR; 722 } 723 724 unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const { 725 return hasFP(MF) ? PPC::R31 : PPC::R1; 726 } 727 728 void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove *> &Moves) 729 const { 730 // Initial state is the frame pointer is R1. 731 MachineLocation Dst(MachineLocation::VirtualFP); 732 MachineLocation Src(PPC::R1, 0); 733 Moves.push_back(new MachineMove(0, Dst, Src)); 734 } 735 736 #include "PPCGenRegisterInfo.inc" 737 738