1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file was developed by the LLVM research group and is distributed under 6 // the University of Illinois Open Source License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the MRegisterInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #define DEBUG_TYPE "reginfo" 15 #include "PPC.h" 16 #include "PPCInstrBuilder.h" 17 #include "PPCRegisterInfo.h" 18 #include "llvm/Constants.h" 19 #include "llvm/Type.h" 20 #include "llvm/CodeGen/ValueTypes.h" 21 #include "llvm/CodeGen/MachineInstrBuilder.h" 22 #include "llvm/CodeGen/MachineFunction.h" 23 #include "llvm/CodeGen/MachineFrameInfo.h" 24 #include "llvm/Target/TargetFrameInfo.h" 25 #include "llvm/Target/TargetMachine.h" 26 #include "llvm/Target/TargetOptions.h" 27 #include "llvm/Support/CommandLine.h" 28 #include "llvm/Support/Debug.h" 29 #include "llvm/ADT/STLExtras.h" 30 #include <cstdlib> 31 #include <iostream> 32 using namespace llvm; 33 34 PPCRegisterInfo::PPCRegisterInfo() 35 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP) { 36 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 37 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 38 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 39 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 40 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 41 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 42 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 43 ImmToIdxMap[PPC::ADDI] = PPC::ADD; 44 } 45 46 void 47 PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 48 MachineBasicBlock::iterator MI, 49 unsigned SrcReg, int FrameIdx, 50 const TargetRegisterClass *RC) const { 51 if (SrcReg == PPC::LR) { 52 BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11); 53 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx); 54 } else if (RC == PPC32::CRRCRegisterClass) { 55 BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R11); 56 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx); 57 } else if (RC == PPC32::GPRCRegisterClass) { 58 addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(SrcReg),FrameIdx); 59 } else if (RC == PPC32::F8RCRegisterClass) { 60 addFrameReference(BuildMI(MBB, MI, PPC::STFD, 3).addReg(SrcReg),FrameIdx); 61 } else if (RC == PPC32::F4RCRegisterClass) { 62 addFrameReference(BuildMI(MBB, MI, PPC::STFS, 3).addReg(SrcReg),FrameIdx); 63 } else { 64 assert(0 && "Unknown regclass!"); 65 abort(); 66 } 67 } 68 69 void 70 PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 71 MachineBasicBlock::iterator MI, 72 unsigned DestReg, int FrameIdx, 73 const TargetRegisterClass *RC) const { 74 if (DestReg == PPC::LR) { 75 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx); 76 BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11); 77 } else if (RC == PPC32::CRRCRegisterClass) { 78 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx); 79 BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R11); 80 } else if (RC == PPC32::GPRCRegisterClass) { 81 addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, DestReg), FrameIdx); 82 } else if (RC == PPC32::F8RCRegisterClass) { 83 addFrameReference(BuildMI(MBB, MI, PPC::LFD, 2, DestReg), FrameIdx); 84 } else if (RC == PPC32::F4RCRegisterClass) { 85 addFrameReference(BuildMI(MBB, MI, PPC::LFS, 2, DestReg), FrameIdx); 86 } else { 87 assert(0 && "Unknown regclass!"); 88 abort(); 89 } 90 } 91 92 void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, 93 MachineBasicBlock::iterator MI, 94 unsigned DestReg, unsigned SrcReg, 95 const TargetRegisterClass *RC) const { 96 MachineInstr *I; 97 98 if (RC == PPC32::GPRCRegisterClass) { 99 BuildMI(MBB, MI, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg); 100 } else if (RC == PPC32::F4RCRegisterClass) { 101 BuildMI(MBB, MI, PPC::FMRS, 1, DestReg).addReg(SrcReg); 102 } else if (RC == PPC32::F8RCRegisterClass) { 103 BuildMI(MBB, MI, PPC::FMRD, 1, DestReg).addReg(SrcReg); 104 } else if (RC == PPC32::CRRCRegisterClass) { 105 BuildMI(MBB, MI, PPC::MCRF, 1, DestReg).addReg(SrcReg); 106 } else { 107 std::cerr << "Attempt to copy register that is not GPR or FPR"; 108 abort(); 109 } 110 } 111 112 unsigned PPCRegisterInfo::isLoadFromStackSlot(MachineInstr *MI, 113 int &FrameIndex) const { 114 switch (MI->getOpcode()) { 115 default: break; 116 case PPC::LWZ: 117 case PPC::LFS: 118 case PPC::LFD: 119 if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImmedValue() && 120 MI->getOperand(2).isFrameIndex()) { 121 FrameIndex = MI->getOperand(2).getFrameIndex(); 122 return MI->getOperand(0).getReg(); 123 } 124 break; 125 } 126 return 0; 127 } 128 129 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into 130 /// copy instructions, turning them into load/store instructions. 131 MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI, 132 unsigned OpNum, 133 int FrameIndex) const { 134 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because 135 // it takes more than one instruction to store it. 136 unsigned Opc = MI->getOpcode(); 137 138 if ((Opc == PPC::OR && 139 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { 140 if (OpNum == 0) { // move -> store 141 unsigned InReg = MI->getOperand(1).getReg(); 142 return addFrameReference(BuildMI(PPC::STW, 143 3).addReg(InReg), FrameIndex); 144 } else { // move -> load 145 unsigned OutReg = MI->getOperand(0).getReg(); 146 return addFrameReference(BuildMI(PPC::LWZ, 2, OutReg), FrameIndex); 147 } 148 149 } else if (Opc == PPC::FMRD) { 150 if (OpNum == 0) { // move -> store 151 unsigned InReg = MI->getOperand(1).getReg(); 152 return addFrameReference(BuildMI(PPC::STFD, 153 3).addReg(InReg), FrameIndex); 154 } else { // move -> load 155 unsigned OutReg = MI->getOperand(0).getReg(); 156 return addFrameReference(BuildMI(PPC::LFD, 2, OutReg), FrameIndex); 157 } 158 } else if (Opc == PPC::FMRS) { 159 if (OpNum == 0) { // move -> store 160 unsigned InReg = MI->getOperand(1).getReg(); 161 return addFrameReference(BuildMI(PPC::STFS, 162 3).addReg(InReg), FrameIndex); 163 } else { // move -> load 164 unsigned OutReg = MI->getOperand(0).getReg(); 165 return addFrameReference(BuildMI(PPC::LFS, 2, OutReg), FrameIndex); 166 } 167 } 168 return 0; 169 } 170 171 //===----------------------------------------------------------------------===// 172 // Stack Frame Processing methods 173 //===----------------------------------------------------------------------===// 174 175 // hasFP - Return true if the specified function should have a dedicated frame 176 // pointer register. This is true if the function has variable sized allocas or 177 // if frame pointer elimination is disabled. 178 // 179 static bool hasFP(MachineFunction &MF) { 180 return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects(); 181 } 182 183 void PPCRegisterInfo:: 184 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 185 MachineBasicBlock::iterator I) const { 186 if (hasFP(MF)) { 187 // If we have a frame pointer, convert as follows: 188 // ADJCALLSTACKDOWN -> addi, r1, r1, -amount 189 // ADJCALLSTACKUP -> addi, r1, r1, amount 190 MachineInstr *Old = I; 191 unsigned Amount = Old->getOperand(0).getImmedValue(); 192 if (Amount != 0) { 193 // We need to keep the stack aligned properly. To do this, we round the 194 // amount of space needed for the outgoing arguments up to the next 195 // alignment boundary. 196 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 197 Amount = (Amount+Align-1)/Align*Align; 198 199 // Replace the pseudo instruction with a new instruction... 200 if (Old->getOpcode() == PPC::ADJCALLSTACKDOWN) { 201 MBB.insert(I, BuildMI(PPC::ADDI, 2, PPC::R1).addReg(PPC::R1) 202 .addSImm(-Amount)); 203 } else { 204 assert(Old->getOpcode() == PPC::ADJCALLSTACKUP); 205 MBB.insert(I, BuildMI(PPC::ADDI, 2, PPC::R1).addReg(PPC::R1) 206 .addSImm(Amount)); 207 } 208 } 209 } 210 MBB.erase(I); 211 } 212 213 void 214 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { 215 unsigned i = 0; 216 MachineInstr &MI = *II; 217 MachineBasicBlock &MBB = *MI.getParent(); 218 MachineFunction &MF = *MBB.getParent(); 219 220 while (!MI.getOperand(i).isFrameIndex()) { 221 ++i; 222 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 223 } 224 225 int FrameIndex = MI.getOperand(i).getFrameIndex(); 226 227 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 228 MI.SetMachineOperandReg(i, hasFP(MF) ? PPC::R31 : PPC::R1); 229 230 // Take into account whether it's an add or mem instruction 231 unsigned OffIdx = (i == 2) ? 1 : 2; 232 233 // Now add the frame object offset to the offset from r1. 234 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + 235 MI.getOperand(OffIdx).getImmedValue(); 236 237 // If we're not using a Frame Pointer that has been set to the value of the 238 // SP before having the stack size subtracted from it, then add the stack size 239 // to Offset to get the correct offset. 240 Offset += MF.getFrameInfo()->getStackSize(); 241 242 if (Offset > 32767 || Offset < -32768) { 243 // Insert a set of r0 with the full offset value before the ld, st, or add 244 MachineBasicBlock *MBB = MI.getParent(); 245 MBB->insert(II, BuildMI(PPC::LIS, 1, PPC::R0).addSImm(Offset >> 16)); 246 MBB->insert(II, BuildMI(PPC::ORI, 2, PPC::R0).addReg(PPC::R0) 247 .addImm(Offset)); 248 // convert into indexed form of the instruction 249 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 250 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 251 assert(ImmToIdxMap.count(MI.getOpcode()) && 252 "No indexed form of load or store available!"); 253 unsigned NewOpcode = ImmToIdxMap.find(MI.getOpcode())->second; 254 MI.setOpcode(NewOpcode); 255 MI.SetMachineOperandReg(1, MI.getOperand(i).getReg()); 256 MI.SetMachineOperandReg(2, PPC::R0); 257 } else { 258 MI.SetMachineOperandConst(OffIdx, MachineOperand::MO_SignExtendedImmed, 259 Offset); 260 } 261 } 262 263 264 void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const { 265 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB 266 MachineBasicBlock::iterator MBBI = MBB.begin(); 267 MachineFrameInfo *MFI = MF.getFrameInfo(); 268 MachineInstr *MI; 269 270 // Get the number of bytes to allocate from the FrameInfo 271 unsigned NumBytes = MFI->getStackSize(); 272 273 // If we have calls, we cannot use the red zone to store callee save registers 274 // and we must set up a stack frame, so calculate the necessary size here. 275 if (MFI->hasCalls()) { 276 // We reserve argument space for call sites in the function immediately on 277 // entry to the current function. This eliminates the need for add/sub 278 // brackets around call sites. 279 NumBytes += MFI->getMaxCallFrameSize(); 280 } 281 282 // If we are a leaf function, and use up to 224 bytes of stack space, 283 // and don't have a frame pointer, then we do not need to adjust the stack 284 // pointer (we fit in the Red Zone). 285 if ((NumBytes == 0) || (NumBytes <= 224 && !hasFP(MF) && !MFI->hasCalls())) { 286 MFI->setStackSize(0); 287 return; 288 } 289 290 // Add the size of R1 to NumBytes size for the store of R1 to the bottom 291 // of the stack and round the size to a multiple of the alignment. 292 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 293 unsigned GPRSize = 4; 294 unsigned Size = hasFP(MF) ? GPRSize + GPRSize : GPRSize; 295 NumBytes = (NumBytes+Size+Align-1)/Align*Align; 296 297 // Update frame info to pretend that this is part of the stack... 298 MFI->setStackSize(NumBytes); 299 300 // Adjust stack pointer: r1 -= numbytes. 301 if (NumBytes <= 32768) { 302 MI=BuildMI(PPC::STWU,3).addReg(PPC::R1).addSImm(-NumBytes).addReg(PPC::R1); 303 MBB.insert(MBBI, MI); 304 } else { 305 int NegNumbytes = -NumBytes; 306 MI = BuildMI(PPC::LIS, 1, PPC::R0).addSImm(NegNumbytes >> 16); 307 MBB.insert(MBBI, MI); 308 MI = BuildMI(PPC::ORI, 2, PPC::R0).addReg(PPC::R0) 309 .addImm(NegNumbytes & 0xFFFF); 310 MBB.insert(MBBI, MI); 311 MI = BuildMI(PPC::STWUX, 3).addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0); 312 MBB.insert(MBBI, MI); 313 } 314 315 if (hasFP(MF)) { 316 MI = BuildMI(PPC::STW, 3).addReg(PPC::R31).addSImm(GPRSize).addReg(PPC::R1); 317 MBB.insert(MBBI, MI); 318 MI = BuildMI(PPC::OR, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1); 319 MBB.insert(MBBI, MI); 320 } 321 } 322 323 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF, 324 MachineBasicBlock &MBB) const { 325 const MachineFrameInfo *MFI = MF.getFrameInfo(); 326 MachineBasicBlock::iterator MBBI = prior(MBB.end()); 327 MachineInstr *MI; 328 assert(MBBI->getOpcode() == PPC::BLR && 329 "Can only insert epilog into returning blocks"); 330 331 // Get the number of bytes allocated from the FrameInfo... 332 unsigned NumBytes = MFI->getStackSize(); 333 unsigned GPRSize = 4; 334 335 if (NumBytes != 0) { 336 if (hasFP(MF)) { 337 MI = BuildMI(PPC::LWZ, 2, PPC::R31).addSImm(GPRSize).addReg(PPC::R31); 338 MBB.insert(MBBI, MI); 339 } 340 MI = BuildMI(PPC::LWZ, 2, PPC::R1).addSImm(0).addReg(PPC::R1); 341 MBB.insert(MBBI, MI); 342 } 343 } 344 345 #include "PPCGenRegisterInfo.inc" 346 347