1 //===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the TargetRegisterInfo 11 // class. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #define DEBUG_TYPE "reginfo" 16 #include "PPCRegisterInfo.h" 17 #include "PPC.h" 18 #include "PPCFrameLowering.h" 19 #include "PPCInstrBuilder.h" 20 #include "PPCMachineFunctionInfo.h" 21 #include "PPCSubtarget.h" 22 #include "llvm/ADT/BitVector.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/CodeGen/MachineFrameInfo.h" 25 #include "llvm/CodeGen/MachineFunction.h" 26 #include "llvm/CodeGen/MachineInstrBuilder.h" 27 #include "llvm/CodeGen/MachineModuleInfo.h" 28 #include "llvm/CodeGen/MachineRegisterInfo.h" 29 #include "llvm/CodeGen/RegisterScavenging.h" 30 #include "llvm/CodeGen/ValueTypes.h" 31 #include "llvm/IR/CallingConv.h" 32 #include "llvm/IR/Constants.h" 33 #include "llvm/IR/Function.h" 34 #include "llvm/IR/Type.h" 35 #include "llvm/Support/CommandLine.h" 36 #include "llvm/Support/Debug.h" 37 #include "llvm/Support/ErrorHandling.h" 38 #include "llvm/Support/MathExtras.h" 39 #include "llvm/Support/raw_ostream.h" 40 #include "llvm/Target/TargetFrameLowering.h" 41 #include "llvm/Target/TargetInstrInfo.h" 42 #include "llvm/Target/TargetMachine.h" 43 #include "llvm/Target/TargetOptions.h" 44 #include <cstdlib> 45 46 #define GET_REGINFO_TARGET_DESC 47 #include "PPCGenRegisterInfo.inc" 48 49 using namespace llvm; 50 51 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST, 52 const TargetInstrInfo &tii) 53 : PPCGenRegisterInfo(ST.isPPC64() ? PPC::LR8 : PPC::LR, 54 ST.isPPC64() ? 0 : 1, 55 ST.isPPC64() ? 0 : 1), 56 Subtarget(ST), TII(tii) { 57 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 58 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 59 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 60 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 61 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 62 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 63 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 64 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 65 66 // 64-bit 67 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8; 68 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8; 69 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8; 70 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX; 71 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32; 72 } 73 74 /// getPointerRegClass - Return the register class to use to hold pointers. 75 /// This is used for addressing modes. 76 const TargetRegisterClass * 77 PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) 78 const { 79 if (Kind == 1) { 80 if (Subtarget.isPPC64()) 81 return &PPC::G8RC_NOX0RegClass; 82 return &PPC::GPRC_NOR0RegClass; 83 } 84 85 if (Subtarget.isPPC64()) 86 return &PPC::G8RCRegClass; 87 return &PPC::GPRCRegClass; 88 } 89 90 const uint16_t* 91 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 92 if (Subtarget.isDarwinABI()) 93 return Subtarget.isPPC64() ? CSR_Darwin64_SaveList : 94 CSR_Darwin32_SaveList; 95 96 return Subtarget.isPPC64() ? CSR_SVR464_SaveList : CSR_SVR432_SaveList; 97 } 98 99 const uint32_t* 100 PPCRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const { 101 if (Subtarget.isDarwinABI()) 102 return Subtarget.isPPC64() ? CSR_Darwin64_RegMask : 103 CSR_Darwin32_RegMask; 104 105 return Subtarget.isPPC64() ? CSR_SVR464_RegMask : CSR_SVR432_RegMask; 106 } 107 108 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 109 BitVector Reserved(getNumRegs()); 110 const PPCFrameLowering *PPCFI = 111 static_cast<const PPCFrameLowering*>(MF.getTarget().getFrameLowering()); 112 113 // The ZERO register is not really a register, but the representation of r0 114 // when used in instructions that treat r0 as the constant 0. 115 Reserved.set(PPC::ZERO); 116 117 Reserved.set(PPC::R0); 118 Reserved.set(PPC::R1); 119 Reserved.set(PPC::LR); 120 Reserved.set(PPC::LR8); 121 Reserved.set(PPC::RM); 122 123 // The SVR4 ABI reserves r2 and r13 124 if (Subtarget.isSVR4ABI()) { 125 Reserved.set(PPC::R2); // System-reserved register 126 Reserved.set(PPC::R13); // Small Data Area pointer register 127 } 128 129 // On PPC64, r13 is the thread pointer. Never allocate this register. 130 if (Subtarget.isPPC64()) { 131 Reserved.set(PPC::R13); 132 133 Reserved.set(PPC::X0); 134 Reserved.set(PPC::X1); 135 Reserved.set(PPC::X13); 136 137 if (PPCFI->needsFP(MF)) 138 Reserved.set(PPC::X31); 139 140 // The 64-bit SVR4 ABI reserves r2 for the TOC pointer. 141 if (Subtarget.isSVR4ABI()) { 142 Reserved.set(PPC::X2); 143 } 144 } 145 146 if (PPCFI->needsFP(MF)) 147 Reserved.set(PPC::R31); 148 149 return Reserved; 150 } 151 152 unsigned 153 PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 154 MachineFunction &MF) const { 155 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 156 const unsigned DefaultSafety = 1; 157 158 switch (RC->getID()) { 159 default: 160 return 0; 161 case PPC::G8RC_NOX0RegClassID: 162 case PPC::GPRC_NOR0RegClassID: 163 case PPC::G8RCRegClassID: 164 case PPC::GPRCRegClassID: { 165 unsigned FP = TFI->hasFP(MF) ? 1 : 0; 166 return 32 - FP - DefaultSafety; 167 } 168 case PPC::F8RCRegClassID: 169 case PPC::F4RCRegClassID: 170 case PPC::VRRCRegClassID: 171 return 32 - DefaultSafety; 172 case PPC::CRRCRegClassID: 173 return 8 - DefaultSafety; 174 } 175 } 176 177 //===----------------------------------------------------------------------===// 178 // Stack Frame Processing methods 179 //===----------------------------------------------------------------------===// 180 181 /// lowerDynamicAlloc - Generate the code for allocating an object in the 182 /// current frame. The sequence of code with be in the general form 183 /// 184 /// addi R0, SP, \#frameSize ; get the address of the previous frame 185 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size 186 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation 187 /// 188 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II, 189 int SPAdj, RegScavenger *RS) const { 190 // Get the instruction. 191 MachineInstr &MI = *II; 192 // Get the instruction's basic block. 193 MachineBasicBlock &MBB = *MI.getParent(); 194 // Get the basic block's function. 195 MachineFunction &MF = *MBB.getParent(); 196 // Get the frame info. 197 MachineFrameInfo *MFI = MF.getFrameInfo(); 198 // Determine whether 64-bit pointers are used. 199 bool LP64 = Subtarget.isPPC64(); 200 DebugLoc dl = MI.getDebugLoc(); 201 202 // Get the maximum call stack size. 203 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 204 // Get the total frame size. 205 unsigned FrameSize = MFI->getStackSize(); 206 207 // Get stack alignments. 208 unsigned TargetAlign = MF.getTarget().getFrameLowering()->getStackAlignment(); 209 unsigned MaxAlign = MFI->getMaxAlignment(); 210 if (MaxAlign > TargetAlign) 211 report_fatal_error("Dynamic alloca with large aligns not supported"); 212 213 // Determine the previous frame's address. If FrameSize can't be 214 // represented as 16 bits or we need special alignment, then we load the 215 // previous frame's address from 0(SP). Why not do an addis of the hi? 216 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. 217 // Constructing the constant and adding would take 3 instructions. 218 // Fortunately, a frame greater than 32K is rare. 219 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 220 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 221 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 222 223 if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) { 224 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) 225 .addReg(PPC::R31) 226 .addImm(FrameSize); 227 } else if (LP64) { 228 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg) 229 .addImm(0) 230 .addReg(PPC::X1); 231 } else { 232 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) 233 .addImm(0) 234 .addReg(PPC::R1); 235 } 236 237 // Grow the stack and update the stack pointer link, then determine the 238 // address of new allocated space. 239 if (LP64) { 240 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1) 241 .addReg(Reg, RegState::Kill) 242 .addReg(PPC::X1) 243 .addReg(MI.getOperand(1).getReg()); 244 if (!MI.getOperand(1).isKill()) 245 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 246 .addReg(PPC::X1) 247 .addImm(maxCallFrameSize); 248 else 249 // Implicitly kill the register. 250 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 251 .addReg(PPC::X1) 252 .addImm(maxCallFrameSize) 253 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill); 254 } else { 255 BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1) 256 .addReg(Reg, RegState::Kill) 257 .addReg(PPC::R1) 258 .addReg(MI.getOperand(1).getReg()); 259 260 if (!MI.getOperand(1).isKill()) 261 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 262 .addReg(PPC::R1) 263 .addImm(maxCallFrameSize); 264 else 265 // Implicitly kill the register. 266 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 267 .addReg(PPC::R1) 268 .addImm(maxCallFrameSize) 269 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill); 270 } 271 272 // Discard the DYNALLOC instruction. 273 MBB.erase(II); 274 } 275 276 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of 277 /// reserving a whole register (R0), we scrounge for one here. This generates 278 /// code like this: 279 /// 280 /// mfcr rA ; Move the conditional register into GPR rA. 281 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot. 282 /// stw rA, FI ; Store rA to the frame. 283 /// 284 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, 285 unsigned FrameIndex, int SPAdj, 286 RegScavenger *RS) const { 287 // Get the instruction. 288 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset> 289 // Get the instruction's basic block. 290 MachineBasicBlock &MBB = *MI.getParent(); 291 DebugLoc dl = MI.getDebugLoc(); 292 293 // FIXME: Once LLVM supports creating virtual registers here, or the register 294 // scavenger can return multiple registers, stop using reserved registers 295 // here. 296 (void) SPAdj; 297 (void) RS; 298 299 bool LP64 = Subtarget.isPPC64(); 300 unsigned Reg = LP64 ? PPC::X0 : PPC::R0; 301 unsigned SrcReg = MI.getOperand(0).getReg(); 302 303 // We need to store the CR in the low 4-bits of the saved value. First, issue 304 // an MFCRpsued to save all of the CRBits and, if needed, kill the SrcReg. 305 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFCR8pseud : PPC::MFCRpseud), Reg) 306 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 307 308 // If the saved register wasn't CR0, shift the bits left so that they are in 309 // CR0's slot. 310 if (SrcReg != PPC::CR0) 311 // rlwinm rA, rA, ShiftBits, 0, 31. 312 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 313 .addReg(Reg, RegState::Kill) 314 .addImm(getPPCRegisterNumbering(SrcReg) * 4) 315 .addImm(0) 316 .addImm(31); 317 318 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW)) 319 .addReg(Reg, getKillRegState(MI.getOperand(1).getImm())), 320 FrameIndex); 321 322 // Discard the pseudo instruction. 323 MBB.erase(II); 324 } 325 326 void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II, 327 unsigned FrameIndex, int SPAdj, 328 RegScavenger *RS) const { 329 // Get the instruction. 330 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset> 331 // Get the instruction's basic block. 332 MachineBasicBlock &MBB = *MI.getParent(); 333 DebugLoc dl = MI.getDebugLoc(); 334 335 // FIXME: Once LLVM supports creating virtual registers here, or the register 336 // scavenger can return multiple registers, stop using reserved registers 337 // here. 338 (void) SPAdj; 339 (void) RS; 340 341 bool LP64 = Subtarget.isPPC64(); 342 unsigned Reg = LP64 ? PPC::X0 : PPC::R0; 343 unsigned DestReg = MI.getOperand(0).getReg(); 344 assert(MI.definesRegister(DestReg) && 345 "RESTORE_CR does not define its destination"); 346 347 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), 348 Reg), FrameIndex); 349 350 // If the reloaded register isn't CR0, shift the bits right so that they are 351 // in the right CR's slot. 352 if (DestReg != PPC::CR0) { 353 unsigned ShiftBits = getPPCRegisterNumbering(DestReg)*4; 354 // rlwinm r11, r11, 32-ShiftBits, 0, 31. 355 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 356 .addReg(Reg).addImm(32-ShiftBits).addImm(0) 357 .addImm(31); 358 } 359 360 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTCRF8 : PPC::MTCRF), DestReg) 361 .addReg(Reg); 362 363 // Discard the pseudo instruction. 364 MBB.erase(II); 365 } 366 367 bool 368 PPCRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF, 369 unsigned Reg, int &FrameIdx) const { 370 371 // For the nonvolatile condition registers (CR2, CR3, CR4) in an SVR4 372 // ABI, return true to prevent allocating an additional frame slot. 373 // For 64-bit, the CR save area is at SP+8; the value of FrameIdx = 0 374 // is arbitrary and will be subsequently ignored. For 32-bit, we have 375 // previously created the stack slot if needed, so return its FrameIdx. 376 if (Subtarget.isSVR4ABI() && PPC::CR2 <= Reg && Reg <= PPC::CR4) { 377 if (Subtarget.isPPC64()) 378 FrameIdx = 0; 379 else { 380 const PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 381 FrameIdx = FI->getCRSpillFrameIndex(); 382 } 383 return true; 384 } 385 return false; 386 } 387 388 void 389 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 390 int SPAdj, unsigned FIOperandNum, 391 RegScavenger *RS) const { 392 assert(SPAdj == 0 && "Unexpected"); 393 394 // Get the instruction. 395 MachineInstr &MI = *II; 396 // Get the instruction's basic block. 397 MachineBasicBlock &MBB = *MI.getParent(); 398 // Get the basic block's function. 399 MachineFunction &MF = *MBB.getParent(); 400 // Get the frame info. 401 MachineFrameInfo *MFI = MF.getFrameInfo(); 402 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 403 DebugLoc dl = MI.getDebugLoc(); 404 405 // Take into account whether it's an add or mem instruction 406 unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2; 407 if (MI.isInlineAsm()) 408 OffsetOperandNo = FIOperandNum-1; 409 410 // Get the frame index. 411 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 412 413 // Get the frame pointer save index. Users of this index are primarily 414 // DYNALLOC instructions. 415 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 416 int FPSI = FI->getFramePointerSaveIndex(); 417 // Get the instruction opcode. 418 unsigned OpC = MI.getOpcode(); 419 420 // Special case for dynamic alloca. 421 if (FPSI && FrameIndex == FPSI && 422 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { 423 lowerDynamicAlloc(II, SPAdj, RS); 424 return; 425 } 426 427 // Special case for pseudo-ops SPILL_CR and RESTORE_CR. 428 if (OpC == PPC::SPILL_CR) { 429 lowerCRSpilling(II, FrameIndex, SPAdj, RS); 430 return; 431 } else if (OpC == PPC::RESTORE_CR) { 432 lowerCRRestore(II, FrameIndex, SPAdj, RS); 433 return; 434 } 435 436 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 437 438 bool is64Bit = Subtarget.isPPC64(); 439 MI.getOperand(FIOperandNum).ChangeToRegister(TFI->hasFP(MF) ? 440 (is64Bit ? PPC::X31 : PPC::R31) : 441 (is64Bit ? PPC::X1 : PPC::R1), 442 false); 443 444 // Figure out if the offset in the instruction is shifted right two bits. This 445 // is true for instructions like "STD", which the machine implicitly adds two 446 // low zeros to. 447 bool isIXAddr = false; 448 switch (OpC) { 449 case PPC::LWA: 450 case PPC::LD: 451 case PPC::STD: 452 case PPC::STD_32: 453 isIXAddr = true; 454 break; 455 } 456 457 bool noImmForm = false; 458 switch (OpC) { 459 case PPC::LVEBX: 460 case PPC::LVEHX: 461 case PPC::LVEWX: 462 case PPC::LVX: 463 case PPC::LVXL: 464 case PPC::LVSL: 465 case PPC::LVSR: 466 case PPC::STVEBX: 467 case PPC::STVEHX: 468 case PPC::STVEWX: 469 case PPC::STVX: 470 case PPC::STVXL: 471 noImmForm = true; 472 break; 473 } 474 475 // Now add the frame object offset to the offset from r1. 476 int Offset = MFI->getObjectOffset(FrameIndex); 477 if (!isIXAddr) 478 Offset += MI.getOperand(OffsetOperandNo).getImm(); 479 else 480 Offset += MI.getOperand(OffsetOperandNo).getImm() << 2; 481 482 // If we're not using a Frame Pointer that has been set to the value of the 483 // SP before having the stack size subtracted from it, then add the stack size 484 // to Offset to get the correct offset. 485 // Naked functions have stack size 0, although getStackSize may not reflect that 486 // because we didn't call all the pieces that compute it for naked functions. 487 if (!MF.getFunction()->getAttributes(). 488 hasAttribute(AttributeSet::FunctionIndex, Attribute::Naked)) 489 Offset += MFI->getStackSize(); 490 491 // If we can, encode the offset directly into the instruction. If this is a 492 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If 493 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits 494 // clear can be encoded. This is extremely uncommon, because normally you 495 // only "std" to a stack slot that is at least 4-byte aligned, but it can 496 // happen in invalid code. 497 if (OpC == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm 498 (!noImmForm && 499 isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0))) { 500 if (isIXAddr) 501 Offset >>= 2; // The actual encoded value has the low two bits zero. 502 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 503 return; 504 } 505 506 // The offset doesn't fit into a single register, scavenge one to build the 507 // offset in. 508 509 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 510 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 511 unsigned SReg = MF.getRegInfo().createVirtualRegister(is64Bit ? G8RC : GPRC); 512 513 // Insert a set of rA with the full offset value before the ld, st, or add 514 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SReg) 515 .addImm(Offset >> 16); 516 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg) 517 .addReg(SReg, RegState::Kill) 518 .addImm(Offset); 519 520 // Convert into indexed form of the instruction: 521 // 522 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 523 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 524 unsigned OperandBase; 525 526 if (noImmForm) 527 OperandBase = 1; 528 else if (OpC != TargetOpcode::INLINEASM) { 529 assert(ImmToIdxMap.count(OpC) && 530 "No indexed form of load or store available!"); 531 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; 532 MI.setDesc(TII.get(NewOpcode)); 533 OperandBase = 1; 534 } else { 535 OperandBase = OffsetOperandNo; 536 } 537 538 unsigned StackReg = MI.getOperand(FIOperandNum).getReg(); 539 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false); 540 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true); 541 } 542 543 unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 544 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 545 546 if (!Subtarget.isPPC64()) 547 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1; 548 else 549 return TFI->hasFP(MF) ? PPC::X31 : PPC::X1; 550 } 551 552 unsigned PPCRegisterInfo::getEHExceptionRegister() const { 553 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3; 554 } 555 556 unsigned PPCRegisterInfo::getEHHandlerRegister() const { 557 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4; 558 } 559