1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file was developed by the LLVM research group and is distributed under 6 // the University of Illinois Open Source License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the MRegisterInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #define DEBUG_TYPE "reginfo" 15 #include "PPC.h" 16 #include "PPCInstrBuilder.h" 17 #include "PPCMachineFunctionInfo.h" 18 #include "PPCRegisterInfo.h" 19 #include "PPCFrameInfo.h" 20 #include "PPCSubtarget.h" 21 #include "llvm/Constants.h" 22 #include "llvm/Type.h" 23 #include "llvm/CodeGen/ValueTypes.h" 24 #include "llvm/CodeGen/MachineInstrBuilder.h" 25 #include "llvm/CodeGen/MachineModuleInfo.h" 26 #include "llvm/CodeGen/MachineFunction.h" 27 #include "llvm/CodeGen/MachineFrameInfo.h" 28 #include "llvm/CodeGen/MachineLocation.h" 29 #include "llvm/CodeGen/SelectionDAGNodes.h" 30 #include "llvm/Target/TargetFrameInfo.h" 31 #include "llvm/Target/TargetInstrInfo.h" 32 #include "llvm/Target/TargetMachine.h" 33 #include "llvm/Target/TargetOptions.h" 34 #include "llvm/Support/CommandLine.h" 35 #include "llvm/Support/Debug.h" 36 #include "llvm/Support/MathExtras.h" 37 #include "llvm/ADT/BitVector.h" 38 #include "llvm/ADT/STLExtras.h" 39 #include <cstdlib> 40 using namespace llvm; 41 42 /// getRegisterNumbering - Given the enum value for some register, e.g. 43 /// PPC::F14, return the number that it corresponds to (e.g. 14). 44 unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) { 45 using namespace PPC; 46 switch (RegEnum) { 47 case R0 : case X0 : case F0 : case V0 : case CR0: return 0; 48 case R1 : case X1 : case F1 : case V1 : case CR1: return 1; 49 case R2 : case X2 : case F2 : case V2 : case CR2: return 2; 50 case R3 : case X3 : case F3 : case V3 : case CR3: return 3; 51 case R4 : case X4 : case F4 : case V4 : case CR4: return 4; 52 case R5 : case X5 : case F5 : case V5 : case CR5: return 5; 53 case R6 : case X6 : case F6 : case V6 : case CR6: return 6; 54 case R7 : case X7 : case F7 : case V7 : case CR7: return 7; 55 case R8 : case X8 : case F8 : case V8 : return 8; 56 case R9 : case X9 : case F9 : case V9 : return 9; 57 case R10: case X10: case F10: case V10: return 10; 58 case R11: case X11: case F11: case V11: return 11; 59 case R12: case X12: case F12: case V12: return 12; 60 case R13: case X13: case F13: case V13: return 13; 61 case R14: case X14: case F14: case V14: return 14; 62 case R15: case X15: case F15: case V15: return 15; 63 case R16: case X16: case F16: case V16: return 16; 64 case R17: case X17: case F17: case V17: return 17; 65 case R18: case X18: case F18: case V18: return 18; 66 case R19: case X19: case F19: case V19: return 19; 67 case R20: case X20: case F20: case V20: return 20; 68 case R21: case X21: case F21: case V21: return 21; 69 case R22: case X22: case F22: case V22: return 22; 70 case R23: case X23: case F23: case V23: return 23; 71 case R24: case X24: case F24: case V24: return 24; 72 case R25: case X25: case F25: case V25: return 25; 73 case R26: case X26: case F26: case V26: return 26; 74 case R27: case X27: case F27: case V27: return 27; 75 case R28: case X28: case F28: case V28: return 28; 76 case R29: case X29: case F29: case V29: return 29; 77 case R30: case X30: case F30: case V30: return 30; 78 case R31: case X31: case F31: case V31: return 31; 79 default: 80 cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n"; 81 abort(); 82 } 83 } 84 85 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST, 86 const TargetInstrInfo &tii) 87 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP), 88 Subtarget(ST), TII(tii) { 89 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 90 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 91 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 92 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 93 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 94 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 95 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 96 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 97 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; 98 } 99 100 void 101 PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 102 MachineBasicBlock::iterator MI, 103 unsigned SrcReg, int FrameIdx, 104 const TargetRegisterClass *RC) const { 105 if (RC == PPC::GPRCRegisterClass) { 106 if (SrcReg != PPC::LR) { 107 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW)) 108 .addReg(SrcReg, false, false, true), FrameIdx); 109 } else { 110 // FIXME: this spills LR immediately to memory in one step. To do this, 111 // we use R11, which we know cannot be used in the prolog/epilog. This is 112 // a hack. 113 BuildMI(MBB, MI, TII.get(PPC::MFLR), PPC::R11); 114 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW)) 115 .addReg(PPC::R11, false, false, true), FrameIdx); 116 } 117 } else if (RC == PPC::G8RCRegisterClass) { 118 if (SrcReg != PPC::LR8) { 119 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STD)) 120 .addReg(SrcReg, false, false, true), FrameIdx); 121 } else { 122 // FIXME: this spills LR immediately to memory in one step. To do this, 123 // we use R11, which we know cannot be used in the prolog/epilog. This is 124 // a hack. 125 BuildMI(MBB, MI, TII.get(PPC::MFLR8), PPC::X11); 126 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STD)) 127 .addReg(PPC::X11, false, false, true), FrameIdx); 128 } 129 } else if (RC == PPC::F8RCRegisterClass) { 130 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STFD)) 131 .addReg(SrcReg, false, false, true), FrameIdx); 132 } else if (RC == PPC::F4RCRegisterClass) { 133 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STFS)) 134 .addReg(SrcReg, false, false, true), FrameIdx); 135 } else if (RC == PPC::CRRCRegisterClass) { 136 // FIXME: We use R0 here, because it isn't available for RA. 137 // We need to store the CR in the low 4-bits of the saved value. First, 138 // issue a MFCR to save all of the CRBits. 139 BuildMI(MBB, MI, TII.get(PPC::MFCR), PPC::R0); 140 141 // If the saved register wasn't CR0, shift the bits left so that they are in 142 // CR0's slot. 143 if (SrcReg != PPC::CR0) { 144 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4; 145 // rlwinm r0, r0, ShiftBits, 0, 31. 146 BuildMI(MBB, MI, TII.get(PPC::RLWINM), PPC::R0) 147 .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31); 148 } 149 150 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW)) 151 .addReg(PPC::R0, false, false, true), FrameIdx); 152 } else if (RC == PPC::VRRCRegisterClass) { 153 // We don't have indexed addressing for vector loads. Emit: 154 // R11 = ADDI FI# 155 // Dest = LVX R0, R11 156 // 157 // FIXME: We use R0 here, because it isn't available for RA. 158 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::ADDI), PPC::R0), 159 FrameIdx, 0, 0); 160 BuildMI(MBB, MI, TII.get(PPC::STVX)) 161 .addReg(SrcReg, false, false, true).addReg(PPC::R0).addReg(PPC::R0); 162 } else { 163 assert(0 && "Unknown regclass!"); 164 abort(); 165 } 166 } 167 168 void 169 PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 170 MachineBasicBlock::iterator MI, 171 unsigned DestReg, int FrameIdx, 172 const TargetRegisterClass *RC) const { 173 if (RC == PPC::GPRCRegisterClass) { 174 if (DestReg != PPC::LR) { 175 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LWZ), DestReg), FrameIdx); 176 } else { 177 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LWZ), PPC::R11),FrameIdx); 178 BuildMI(MBB, MI, TII.get(PPC::MTLR)).addReg(PPC::R11); 179 } 180 } else if (RC == PPC::G8RCRegisterClass) { 181 if (DestReg != PPC::LR8) { 182 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LD), DestReg), FrameIdx); 183 } else { 184 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LD), PPC::R11), FrameIdx); 185 BuildMI(MBB, MI, TII.get(PPC::MTLR8)).addReg(PPC::R11); 186 } 187 } else if (RC == PPC::F8RCRegisterClass) { 188 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LFD), DestReg), FrameIdx); 189 } else if (RC == PPC::F4RCRegisterClass) { 190 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LFS), DestReg), FrameIdx); 191 } else if (RC == PPC::CRRCRegisterClass) { 192 // FIXME: We use R0 here, because it isn't available for RA. 193 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LWZ), PPC::R0), FrameIdx); 194 195 // If the reloaded register isn't CR0, shift the bits right so that they are 196 // in the right CR's slot. 197 if (DestReg != PPC::CR0) { 198 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4; 199 // rlwinm r11, r11, 32-ShiftBits, 0, 31. 200 BuildMI(MBB, MI, TII.get(PPC::RLWINM), PPC::R0) 201 .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31); 202 } 203 204 BuildMI(MBB, MI, TII.get(PPC::MTCRF), DestReg).addReg(PPC::R0); 205 } else if (RC == PPC::VRRCRegisterClass) { 206 // We don't have indexed addressing for vector loads. Emit: 207 // R11 = ADDI FI# 208 // Dest = LVX R0, R11 209 // 210 // FIXME: We use R0 here, because it isn't available for RA. 211 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::ADDI), PPC::R0), 212 FrameIdx, 0, 0); 213 BuildMI(MBB, MI, TII.get(PPC::LVX),DestReg).addReg(PPC::R0).addReg(PPC::R0); 214 } else { 215 assert(0 && "Unknown regclass!"); 216 abort(); 217 } 218 } 219 220 void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, 221 MachineBasicBlock::iterator MI, 222 unsigned DestReg, unsigned SrcReg, 223 const TargetRegisterClass *RC) const { 224 if (RC == PPC::GPRCRegisterClass) { 225 BuildMI(MBB, MI, TII.get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg); 226 } else if (RC == PPC::G8RCRegisterClass) { 227 BuildMI(MBB, MI, TII.get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg); 228 } else if (RC == PPC::F4RCRegisterClass) { 229 BuildMI(MBB, MI, TII.get(PPC::FMRS), DestReg).addReg(SrcReg); 230 } else if (RC == PPC::F8RCRegisterClass) { 231 BuildMI(MBB, MI, TII.get(PPC::FMRD), DestReg).addReg(SrcReg); 232 } else if (RC == PPC::CRRCRegisterClass) { 233 BuildMI(MBB, MI, TII.get(PPC::MCRF), DestReg).addReg(SrcReg); 234 } else if (RC == PPC::VRRCRegisterClass) { 235 BuildMI(MBB, MI, TII.get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg); 236 } else { 237 cerr << "Attempt to copy register that is not GPR or FPR"; 238 abort(); 239 } 240 } 241 242 void PPCRegisterInfo::reMaterialize(MachineBasicBlock &MBB, 243 MachineBasicBlock::iterator I, 244 unsigned DestReg, 245 const MachineInstr *Orig) const { 246 MachineInstr *MI = Orig->clone(); 247 MI->getOperand(0).setReg(DestReg); 248 MBB.insert(I, MI); 249 } 250 251 const unsigned* PPCRegisterInfo::getCalleeSavedRegs() const { 252 // 32-bit Darwin calling convention. 253 static const unsigned Darwin32_CalleeSavedRegs[] = { 254 PPC::R13, PPC::R14, PPC::R15, 255 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 256 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 257 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 258 PPC::R28, PPC::R29, PPC::R30, PPC::R31, 259 260 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 261 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 262 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 263 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 264 PPC::F30, PPC::F31, 265 266 PPC::CR2, PPC::CR3, PPC::CR4, 267 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 268 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 269 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 270 271 PPC::LR, 0 272 }; 273 274 static const unsigned ELF32_CalleeSavedRegs[] = { 275 PPC::R13, PPC::R14, PPC::R15, 276 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 277 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 278 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 279 PPC::R28, PPC::R29, PPC::R30, PPC::R31, 280 281 PPC::F11, PPC::F12, PPC::F13, 282 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 283 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 284 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 285 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 286 PPC::F30, PPC::F31, 287 288 PPC::CR2, PPC::CR3, PPC::CR4, 289 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 290 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 291 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 292 293 PPC::LR, 0 294 }; 295 // 64-bit Darwin calling convention. 296 static const unsigned Darwin64_CalleeSavedRegs[] = { 297 PPC::X14, PPC::X15, 298 PPC::X16, PPC::X17, PPC::X18, PPC::X19, 299 PPC::X20, PPC::X21, PPC::X22, PPC::X23, 300 PPC::X24, PPC::X25, PPC::X26, PPC::X27, 301 PPC::X28, PPC::X29, PPC::X30, PPC::X31, 302 303 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 304 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 305 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 306 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 307 PPC::F30, PPC::F31, 308 309 PPC::CR2, PPC::CR3, PPC::CR4, 310 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 311 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 312 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 313 314 PPC::LR8, 0 315 }; 316 317 static const unsigned ELF64_CalleeSavedRegs[] = { 318 PPC::X14, PPC::X15, 319 PPC::X16, PPC::X17, PPC::X18, PPC::X19, 320 PPC::X20, PPC::X21, PPC::X22, PPC::X23, 321 PPC::X24, PPC::X25, PPC::X26, PPC::X27, 322 PPC::X28, PPC::X29, PPC::X30, PPC::X31, 323 324 PPC::F11, PPC::F12, PPC::F13, 325 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 326 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 327 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 328 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 329 PPC::F30, PPC::F31, 330 331 PPC::CR2, PPC::CR3, PPC::CR4, 332 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 333 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 334 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 335 336 PPC::LR8, 0 337 }; 338 339 if (Subtarget.isMachoABI()) 340 return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegs : 341 Darwin32_CalleeSavedRegs; 342 343 // ELF. 344 return Subtarget.isPPC64() ? ELF64_CalleeSavedRegs : ELF32_CalleeSavedRegs; 345 } 346 347 const TargetRegisterClass* const* 348 PPCRegisterInfo::getCalleeSavedRegClasses() const { 349 // 32-bit Darwin calling convention. 350 static const TargetRegisterClass * const Darwin32_CalleeSavedRegClasses[] = { 351 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 352 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 353 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 354 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 355 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 356 357 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 358 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 359 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 360 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 361 &PPC::F8RCRegClass,&PPC::F8RCRegClass, 362 363 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, 364 365 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 366 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 367 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 368 369 &PPC::GPRCRegClass, 0 370 }; 371 372 static const TargetRegisterClass * const ELF32_CalleeSavedRegClasses[] = { 373 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 374 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 375 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 376 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 377 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 378 379 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 380 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 381 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 382 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 383 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 384 &PPC::F8RCRegClass,&PPC::F8RCRegClass, 385 386 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, 387 388 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 389 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 390 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 391 392 &PPC::GPRCRegClass, 0 393 }; 394 395 // 64-bit Darwin calling convention. 396 static const TargetRegisterClass * const Darwin64_CalleeSavedRegClasses[] = { 397 &PPC::G8RCRegClass,&PPC::G8RCRegClass, 398 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 399 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 400 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 401 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 402 403 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 404 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 405 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 406 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 407 &PPC::F8RCRegClass,&PPC::F8RCRegClass, 408 409 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, 410 411 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 412 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 413 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 414 415 &PPC::G8RCRegClass, 0 416 }; 417 418 static const TargetRegisterClass * const ELF64_CalleeSavedRegClasses[] = { 419 &PPC::G8RCRegClass,&PPC::G8RCRegClass, 420 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 421 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 422 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 423 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 424 425 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 426 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 427 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 428 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 429 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 430 &PPC::F8RCRegClass,&PPC::F8RCRegClass, 431 432 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, 433 434 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 435 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 436 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 437 438 &PPC::G8RCRegClass, 0 439 }; 440 441 if (Subtarget.isMachoABI()) 442 return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegClasses : 443 Darwin32_CalleeSavedRegClasses; 444 445 // ELF. 446 return Subtarget.isPPC64() ? ELF64_CalleeSavedRegClasses : 447 ELF32_CalleeSavedRegClasses; 448 } 449 450 // needsFP - Return true if the specified function should have a dedicated frame 451 // pointer register. This is true if the function has variable sized allocas or 452 // if frame pointer elimination is disabled. 453 // 454 static bool needsFP(const MachineFunction &MF) { 455 const MachineFrameInfo *MFI = MF.getFrameInfo(); 456 return NoFramePointerElim || MFI->hasVarSizedObjects(); 457 } 458 459 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 460 BitVector Reserved(getNumRegs()); 461 Reserved.set(PPC::R0); 462 Reserved.set(PPC::R1); 463 Reserved.set(PPC::LR); 464 // In Linux, r2 is reserved for the OS. 465 if (!Subtarget.isDarwin()) 466 Reserved.set(PPC::R2); 467 // On PPC64, r13 is the thread pointer. Never allocate this register. 468 // Note that this is overconservative, as it also prevents allocation of 469 // R31 when the FP is not needed. 470 if (Subtarget.isPPC64()) { 471 Reserved.set(PPC::R13); 472 Reserved.set(PPC::R31); 473 } 474 if (needsFP(MF)) 475 Reserved.set(PPC::R31); 476 return Reserved; 477 } 478 479 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into 480 /// copy instructions, turning them into load/store instructions. 481 MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI, 482 unsigned OpNum, 483 int FrameIndex) const { 484 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because 485 // it takes more than one instruction to store it. 486 unsigned Opc = MI->getOpcode(); 487 488 MachineInstr *NewMI = NULL; 489 if ((Opc == PPC::OR && 490 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { 491 if (OpNum == 0) { // move -> store 492 unsigned InReg = MI->getOperand(1).getReg(); 493 NewMI = addFrameReference(BuildMI(TII.get(PPC::STW)).addReg(InReg), 494 FrameIndex); 495 } else { // move -> load 496 unsigned OutReg = MI->getOperand(0).getReg(); 497 NewMI = addFrameReference(BuildMI(TII.get(PPC::LWZ), OutReg), 498 FrameIndex); 499 } 500 } else if ((Opc == PPC::OR8 && 501 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { 502 if (OpNum == 0) { // move -> store 503 unsigned InReg = MI->getOperand(1).getReg(); 504 NewMI = addFrameReference(BuildMI(TII.get(PPC::STD)).addReg(InReg), 505 FrameIndex); 506 } else { // move -> load 507 unsigned OutReg = MI->getOperand(0).getReg(); 508 NewMI = addFrameReference(BuildMI(TII.get(PPC::LD), OutReg), FrameIndex); 509 } 510 } else if (Opc == PPC::FMRD) { 511 if (OpNum == 0) { // move -> store 512 unsigned InReg = MI->getOperand(1).getReg(); 513 NewMI = addFrameReference(BuildMI(TII.get(PPC::STFD)).addReg(InReg), 514 FrameIndex); 515 } else { // move -> load 516 unsigned OutReg = MI->getOperand(0).getReg(); 517 NewMI = addFrameReference(BuildMI(TII.get(PPC::LFD), OutReg), FrameIndex); 518 } 519 } else if (Opc == PPC::FMRS) { 520 if (OpNum == 0) { // move -> store 521 unsigned InReg = MI->getOperand(1).getReg(); 522 NewMI = addFrameReference(BuildMI(TII.get(PPC::STFS)).addReg(InReg), 523 FrameIndex); 524 } else { // move -> load 525 unsigned OutReg = MI->getOperand(0).getReg(); 526 NewMI = addFrameReference(BuildMI(TII.get(PPC::LFS), OutReg), FrameIndex); 527 } 528 } 529 530 if (NewMI) 531 NewMI->copyKillDeadInfo(MI); 532 return NewMI; 533 } 534 535 //===----------------------------------------------------------------------===// 536 // Stack Frame Processing methods 537 //===----------------------------------------------------------------------===// 538 539 // hasFP - Return true if the specified function actually has a dedicated frame 540 // pointer register. This is true if the function needs a frame pointer and has 541 // a non-zero stack size. 542 bool PPCRegisterInfo::hasFP(const MachineFunction &MF) const { 543 const MachineFrameInfo *MFI = MF.getFrameInfo(); 544 return MFI->getStackSize() && needsFP(MF); 545 } 546 547 /// usesLR - Returns if the link registers (LR) has been used in the function. 548 /// 549 bool PPCRegisterInfo::usesLR(MachineFunction &MF) const { 550 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 551 return FI->usesLR(); 552 } 553 554 void PPCRegisterInfo:: 555 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 556 MachineBasicBlock::iterator I) const { 557 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions. 558 MBB.erase(I); 559 } 560 561 /// LowerDynamicAlloc - Generate the code for allocating an object in the 562 /// current frame. The sequence of code with be in the general form 563 /// 564 /// addi R0, SP, #frameSize ; get the address of the previous frame 565 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size 566 /// addi Rnew, SP, #maxCalFrameSize ; get the top of the allocation 567 /// 568 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const { 569 // Get the instruction. 570 MachineInstr &MI = *II; 571 // Get the instruction's basic block. 572 MachineBasicBlock &MBB = *MI.getParent(); 573 // Get the basic block's function. 574 MachineFunction &MF = *MBB.getParent(); 575 // Get the frame info. 576 MachineFrameInfo *MFI = MF.getFrameInfo(); 577 // Determine whether 64-bit pointers are used. 578 bool LP64 = Subtarget.isPPC64(); 579 580 // Get the maximum call stack size. 581 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 582 // Get the total frame size. 583 unsigned FrameSize = MFI->getStackSize(); 584 585 // Get stack alignments. 586 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 587 unsigned MaxAlign = MFI->getMaxAlignment(); 588 assert(MaxAlign <= TargetAlign && 589 "Dynamic alloca with large aligns not supported"); 590 591 // Determine the previous frame's address. If FrameSize can't be 592 // represented as 16 bits or we need special alignment, then we load the 593 // previous frame's address from 0(SP). Why not do an addis of the hi? 594 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. 595 // Constructing the constant and adding would take 3 instructions. 596 // Fortunately, a frame greater than 32K is rare. 597 if (MaxAlign < TargetAlign && isInt16(FrameSize)) { 598 BuildMI(MBB, II, TII.get(PPC::ADDI), PPC::R0) 599 .addReg(PPC::R31) 600 .addImm(FrameSize); 601 } else if (LP64) { 602 BuildMI(MBB, II, TII.get(PPC::LD), PPC::X0) 603 .addImm(0) 604 .addReg(PPC::X1); 605 } else { 606 BuildMI(MBB, II, TII.get(PPC::LWZ), PPC::R0) 607 .addImm(0) 608 .addReg(PPC::R1); 609 } 610 611 // Grow the stack and update the stack pointer link, then 612 // determine the address of new allocated space. 613 if (LP64) { 614 BuildMI(MBB, II, TII.get(PPC::STDUX)) 615 .addReg(PPC::X0) 616 .addReg(PPC::X1) 617 .addReg(MI.getOperand(1).getReg()); 618 BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 619 .addReg(PPC::X1) 620 .addImm(maxCallFrameSize); 621 } else { 622 BuildMI(MBB, II, TII.get(PPC::STWUX)) 623 .addReg(PPC::R0) 624 .addReg(PPC::R1) 625 .addReg(MI.getOperand(1).getReg()); 626 BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 627 .addReg(PPC::R1) 628 .addImm(maxCallFrameSize); 629 } 630 631 // Discard the DYNALLOC instruction. 632 MBB.erase(II); 633 } 634 635 void PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 636 RegScavenger *RS) const { 637 // Get the instruction. 638 MachineInstr &MI = *II; 639 // Get the instruction's basic block. 640 MachineBasicBlock &MBB = *MI.getParent(); 641 // Get the basic block's function. 642 MachineFunction &MF = *MBB.getParent(); 643 // Get the frame info. 644 MachineFrameInfo *MFI = MF.getFrameInfo(); 645 646 // Find out which operand is the frame index. 647 unsigned i = 0; 648 while (!MI.getOperand(i).isFrameIndex()) { 649 ++i; 650 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 651 } 652 // Take into account whether it's an add or mem instruction 653 unsigned OffIdx = (i == 2) ? 1 : 2; 654 if (MI.getOpcode() == TargetInstrInfo::INLINEASM) 655 OffIdx = i-1; 656 657 // Get the frame index. 658 int FrameIndex = MI.getOperand(i).getFrameIndex(); 659 660 // Get the frame pointer save index. Users of this index are primarily 661 // DYNALLOC instructions. 662 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 663 int FPSI = FI->getFramePointerSaveIndex(); 664 // Get the instruction opcode. 665 unsigned OpC = MI.getOpcode(); 666 667 // Special case for dynamic alloca. 668 if (FPSI && FrameIndex == FPSI && 669 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { 670 lowerDynamicAlloc(II); 671 return; 672 } 673 674 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 675 MI.getOperand(i).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1, false); 676 677 // Figure out if the offset in the instruction is shifted right two bits. This 678 // is true for instructions like "STD", which the machine implicitly adds two 679 // low zeros to. 680 bool isIXAddr = false; 681 switch (OpC) { 682 case PPC::LWA: 683 case PPC::LD: 684 case PPC::STD: 685 case PPC::STD_32: 686 isIXAddr = true; 687 break; 688 } 689 690 // Now add the frame object offset to the offset from r1. 691 int Offset = MFI->getObjectOffset(FrameIndex); 692 693 if (!isIXAddr) 694 Offset += MI.getOperand(OffIdx).getImmedValue(); 695 else 696 Offset += MI.getOperand(OffIdx).getImmedValue() << 2; 697 698 // If we're not using a Frame Pointer that has been set to the value of the 699 // SP before having the stack size subtracted from it, then add the stack size 700 // to Offset to get the correct offset. 701 Offset += MFI->getStackSize(); 702 703 if (!isInt16(Offset)) { 704 // Insert a set of r0 with the full offset value before the ld, st, or add 705 BuildMI(MBB, II, TII.get(PPC::LIS), PPC::R0).addImm(Offset >> 16); 706 BuildMI(MBB, II, TII.get(PPC::ORI), PPC::R0).addReg(PPC::R0).addImm(Offset); 707 708 // convert into indexed form of the instruction 709 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 710 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 711 assert(ImmToIdxMap.count(OpC) && 712 "No indexed form of load or store available!"); 713 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; 714 MI.setInstrDescriptor(TII.get(NewOpcode)); 715 MI.getOperand(1).ChangeToRegister(MI.getOperand(i).getReg(), false); 716 MI.getOperand(2).ChangeToRegister(PPC::R0, false); 717 } else { 718 if (isIXAddr) { 719 assert((Offset & 3) == 0 && "Invalid frame offset!"); 720 Offset >>= 2; // The actual encoded value has the low two bits zero. 721 } 722 MI.getOperand(OffIdx).ChangeToImmediate(Offset); 723 } 724 } 725 726 /// VRRegNo - Map from a numbered VR register to its enum value. 727 /// 728 static const unsigned short VRRegNo[] = { 729 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 , 730 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, 731 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, 732 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31 733 }; 734 735 /// RemoveVRSaveCode - We have found that this function does not need any code 736 /// to manipulate the VRSAVE register, even though it uses vector registers. 737 /// This can happen when the only registers used are known to be live in or out 738 /// of the function. Remove all of the VRSAVE related code from the function. 739 static void RemoveVRSaveCode(MachineInstr *MI) { 740 MachineBasicBlock *Entry = MI->getParent(); 741 MachineFunction *MF = Entry->getParent(); 742 743 // We know that the MTVRSAVE instruction immediately follows MI. Remove it. 744 MachineBasicBlock::iterator MBBI = MI; 745 ++MBBI; 746 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE); 747 MBBI->eraseFromParent(); 748 749 bool RemovedAllMTVRSAVEs = true; 750 // See if we can find and remove the MTVRSAVE instruction from all of the 751 // epilog blocks. 752 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); 753 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) { 754 // If last instruction is a return instruction, add an epilogue 755 if (!I->empty() && TII.isReturn(I->back().getOpcode())) { 756 bool FoundIt = false; 757 for (MBBI = I->end(); MBBI != I->begin(); ) { 758 --MBBI; 759 if (MBBI->getOpcode() == PPC::MTVRSAVE) { 760 MBBI->eraseFromParent(); // remove it. 761 FoundIt = true; 762 break; 763 } 764 } 765 RemovedAllMTVRSAVEs &= FoundIt; 766 } 767 } 768 769 // If we found and removed all MTVRSAVE instructions, remove the read of 770 // VRSAVE as well. 771 if (RemovedAllMTVRSAVEs) { 772 MBBI = MI; 773 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?"); 774 --MBBI; 775 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?"); 776 MBBI->eraseFromParent(); 777 } 778 779 // Finally, nuke the UPDATE_VRSAVE. 780 MI->eraseFromParent(); 781 } 782 783 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the 784 // instruction selector. Based on the vector registers that have been used, 785 // transform this into the appropriate ORI instruction. 786 static void HandleVRSaveUpdate(MachineInstr *MI, const bool *UsedRegs, 787 const TargetInstrInfo &TII) { 788 unsigned UsedRegMask = 0; 789 for (unsigned i = 0; i != 32; ++i) 790 if (UsedRegs[VRRegNo[i]]) 791 UsedRegMask |= 1 << (31-i); 792 793 // Live in and live out values already must be in the mask, so don't bother 794 // marking them. 795 MachineFunction *MF = MI->getParent()->getParent(); 796 for (MachineFunction::livein_iterator I = 797 MF->livein_begin(), E = MF->livein_end(); I != E; ++I) { 798 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first); 799 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg. 800 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 801 } 802 for (MachineFunction::liveout_iterator I = 803 MF->liveout_begin(), E = MF->liveout_end(); I != E; ++I) { 804 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I); 805 if (VRRegNo[RegNo] == *I) // If this really is a vector reg. 806 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 807 } 808 809 unsigned SrcReg = MI->getOperand(1).getReg(); 810 unsigned DstReg = MI->getOperand(0).getReg(); 811 // If no registers are used, turn this into a copy. 812 if (UsedRegMask == 0) { 813 // Remove all VRSAVE code. 814 RemoveVRSaveCode(MI); 815 return; 816 } else if ((UsedRegMask & 0xFFFF) == UsedRegMask) { 817 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg) 818 .addReg(SrcReg).addImm(UsedRegMask); 819 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { 820 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) 821 .addReg(SrcReg).addImm(UsedRegMask >> 16); 822 } else { 823 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) 824 .addReg(SrcReg).addImm(UsedRegMask >> 16); 825 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg) 826 .addReg(DstReg).addImm(UsedRegMask & 0xFFFF); 827 } 828 829 // Remove the old UPDATE_VRSAVE instruction. 830 MI->eraseFromParent(); 831 } 832 833 /// determineFrameLayout - Determine the size of the frame and maximum call 834 /// frame size. 835 void PPCRegisterInfo::determineFrameLayout(MachineFunction &MF) const { 836 MachineFrameInfo *MFI = MF.getFrameInfo(); 837 838 // Get the number of bytes to allocate from the FrameInfo 839 unsigned FrameSize = MFI->getStackSize(); 840 841 // Get the alignments provided by the target, and the maximum alignment 842 // (if any) of the fixed frame objects. 843 unsigned MaxAlign = MFI->getMaxAlignment(); 844 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 845 unsigned AlignMask = TargetAlign - 1; // 846 847 // If we are a leaf function, and use up to 224 bytes of stack space, 848 // don't have a frame pointer, calls, or dynamic alloca then we do not need 849 // to adjust the stack pointer (we fit in the Red Zone). 850 if (FrameSize <= 224 && // Fits in red zone. 851 !MFI->hasVarSizedObjects() && // No dynamic alloca. 852 !MFI->hasCalls() && // No calls. 853 MaxAlign <= TargetAlign) { // No special alignment. 854 // No need for frame 855 MFI->setStackSize(0); 856 return; 857 } 858 859 // Get the maximum call frame size of all the calls. 860 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 861 862 // Maximum call frame needs to be at least big enough for linkage and 8 args. 863 unsigned minCallFrameSize = 864 PPCFrameInfo::getMinCallFrameSize(Subtarget.isPPC64(), 865 Subtarget.isMachoABI()); 866 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize); 867 868 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so 869 // that allocations will be aligned. 870 if (MFI->hasVarSizedObjects()) 871 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask; 872 873 // Update maximum call frame size. 874 MFI->setMaxCallFrameSize(maxCallFrameSize); 875 876 // Include call frame size in total. 877 FrameSize += maxCallFrameSize; 878 879 // Make sure the frame is aligned. 880 FrameSize = (FrameSize + AlignMask) & ~AlignMask; 881 882 // Update frame info. 883 MFI->setStackSize(FrameSize); 884 } 885 886 void PPCRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 887 RegScavenger *RS) 888 const { 889 // Save and clear the LR state. 890 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 891 unsigned LR = getRARegister(); 892 FI->setUsesLR(MF.isPhysRegUsed(LR)); 893 MF.changePhyRegUsed(LR, false); 894 } 895 896 void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const { 897 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB 898 MachineBasicBlock::iterator MBBI = MBB.begin(); 899 MachineFrameInfo *MFI = MF.getFrameInfo(); 900 MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); 901 902 // Prepare for frame info. 903 unsigned FrameLabelId = 0; 904 905 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it, 906 // process it. 907 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { 908 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) { 909 HandleVRSaveUpdate(MBBI, MF.getUsedPhysregs(), TII); 910 break; 911 } 912 } 913 914 // Move MBBI back to the beginning of the function. 915 MBBI = MBB.begin(); 916 917 // Work out frame sizes. 918 determineFrameLayout(MF); 919 unsigned FrameSize = MFI->getStackSize(); 920 921 int NegFrameSize = -FrameSize; 922 923 // Get processor type. 924 bool IsPPC64 = Subtarget.isPPC64(); 925 // Get operating system 926 bool IsMachoABI = Subtarget.isMachoABI(); 927 // Check if the link register (LR) has been used. 928 bool UsesLR = MFI->hasCalls() || usesLR(MF); 929 // Do we have a frame pointer for this function? 930 bool HasFP = hasFP(MF) && FrameSize; 931 932 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI); 933 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI); 934 935 if (IsPPC64) { 936 if (UsesLR) 937 BuildMI(MBB, MBBI, TII.get(PPC::MFLR8), PPC::X0); 938 939 if (HasFP) 940 BuildMI(MBB, MBBI, TII.get(PPC::STD)) 941 .addReg(PPC::X31).addImm(FPOffset/4).addReg(PPC::X1); 942 943 if (UsesLR) 944 BuildMI(MBB, MBBI, TII.get(PPC::STD)) 945 .addReg(PPC::X0).addImm(LROffset/4).addReg(PPC::X1); 946 } else { 947 if (UsesLR) 948 BuildMI(MBB, MBBI, TII.get(PPC::MFLR), PPC::R0); 949 950 if (HasFP) 951 BuildMI(MBB, MBBI, TII.get(PPC::STW)) 952 .addReg(PPC::R31).addImm(FPOffset).addReg(PPC::R1); 953 954 if (UsesLR) 955 BuildMI(MBB, MBBI, TII.get(PPC::STW)) 956 .addReg(PPC::R0).addImm(LROffset).addReg(PPC::R1); 957 } 958 959 // Skip if a leaf routine. 960 if (!FrameSize) return; 961 962 // Get stack alignments. 963 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 964 unsigned MaxAlign = MFI->getMaxAlignment(); 965 966 if (MMI && MMI->needsFrameInfo()) { 967 // Mark effective beginning of when frame pointer becomes valid. 968 FrameLabelId = MMI->NextLabelID(); 969 BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(FrameLabelId); 970 } 971 972 // Adjust stack pointer: r1 += NegFrameSize. 973 // If there is a preferred stack alignment, align R1 now 974 if (!IsPPC64) { 975 // PPC32. 976 if (MaxAlign > TargetAlign) { 977 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!"); 978 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!"); 979 BuildMI(MBB, MBBI, TII.get(PPC::RLWINM), PPC::R0) 980 .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31); 981 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC) ,PPC::R0).addReg(PPC::R0) 982 .addImm(NegFrameSize); 983 BuildMI(MBB, MBBI, TII.get(PPC::STWUX)) 984 .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0); 985 } else if (isInt16(NegFrameSize)) { 986 BuildMI(MBB, MBBI, TII.get(PPC::STWU), 987 PPC::R1).addReg(PPC::R1).addImm(NegFrameSize).addReg(PPC::R1); 988 } else { 989 BuildMI(MBB, MBBI, TII.get(PPC::LIS), PPC::R0).addImm(NegFrameSize >> 16); 990 BuildMI(MBB, MBBI, TII.get(PPC::ORI), PPC::R0).addReg(PPC::R0) 991 .addImm(NegFrameSize & 0xFFFF); 992 BuildMI(MBB, MBBI, TII.get(PPC::STWUX)).addReg(PPC::R1).addReg(PPC::R1) 993 .addReg(PPC::R0); 994 } 995 } else { // PPC64. 996 if (MaxAlign > TargetAlign) { 997 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!"); 998 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!"); 999 BuildMI(MBB, MBBI, TII.get(PPC::RLDICL), PPC::X0) 1000 .addReg(PPC::X1).addImm(0).addImm(64-Log2_32(MaxAlign)); 1001 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC8), PPC::X0).addReg(PPC::X0) 1002 .addImm(NegFrameSize); 1003 BuildMI(MBB, MBBI, TII.get(PPC::STDUX)) 1004 .addReg(PPC::X1).addReg(PPC::X1).addReg(PPC::X0); 1005 } else if (isInt16(NegFrameSize)) { 1006 BuildMI(MBB, MBBI, TII.get(PPC::STDU), PPC::X1) 1007 .addReg(PPC::X1).addImm(NegFrameSize/4).addReg(PPC::X1); 1008 } else { 1009 BuildMI(MBB, MBBI, TII.get(PPC::LIS8), PPC::X0).addImm(NegFrameSize >>16); 1010 BuildMI(MBB, MBBI, TII.get(PPC::ORI8), PPC::X0).addReg(PPC::X0) 1011 .addImm(NegFrameSize & 0xFFFF); 1012 BuildMI(MBB, MBBI, TII.get(PPC::STDUX)).addReg(PPC::X1).addReg(PPC::X1) 1013 .addReg(PPC::X0); 1014 } 1015 } 1016 1017 if (MMI && MMI->needsFrameInfo()) { 1018 std::vector<MachineMove> &Moves = MMI->getFrameMoves(); 1019 1020 if (NegFrameSize) { 1021 // Show update of SP. 1022 MachineLocation SPDst(MachineLocation::VirtualFP); 1023 MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize); 1024 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc)); 1025 } else { 1026 MachineLocation SP(IsPPC64 ? PPC::X31 : PPC::R31); 1027 Moves.push_back(MachineMove(FrameLabelId, SP, SP)); 1028 } 1029 1030 if (HasFP) { 1031 MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset); 1032 MachineLocation FPSrc(IsPPC64 ? PPC::X31 : PPC::R31); 1033 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc)); 1034 } 1035 1036 // Add callee saved registers to move list. 1037 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 1038 for (unsigned I = 0, E = CSI.size(); I != E; ++I) { 1039 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx()); 1040 unsigned Reg = CSI[I].getReg(); 1041 if (Reg == PPC::LR || Reg == PPC::LR8) continue; 1042 MachineLocation CSDst(MachineLocation::VirtualFP, Offset); 1043 MachineLocation CSSrc(Reg); 1044 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc)); 1045 } 1046 1047 MachineLocation LRDst(MachineLocation::VirtualFP, LROffset); 1048 MachineLocation LRSrc(IsPPC64 ? PPC::LR8 : PPC::LR); 1049 Moves.push_back(MachineMove(FrameLabelId, LRDst, LRSrc)); 1050 1051 // Mark effective beginning of when frame pointer is ready. 1052 unsigned ReadyLabelId = MMI->NextLabelID(); 1053 BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(ReadyLabelId); 1054 1055 MachineLocation FPDst(HasFP ? (IsPPC64 ? PPC::X31 : PPC::R31) : 1056 (IsPPC64 ? PPC::X1 : PPC::R1)); 1057 MachineLocation FPSrc(MachineLocation::VirtualFP); 1058 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc)); 1059 } 1060 1061 // If there is a frame pointer, copy R1 into R31 1062 if (HasFP) { 1063 if (!IsPPC64) { 1064 BuildMI(MBB, MBBI, TII.get(PPC::OR), PPC::R31).addReg(PPC::R1) 1065 .addReg(PPC::R1); 1066 } else { 1067 BuildMI(MBB, MBBI, TII.get(PPC::OR8), PPC::X31).addReg(PPC::X1) 1068 .addReg(PPC::X1); 1069 } 1070 } 1071 } 1072 1073 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF, 1074 MachineBasicBlock &MBB) const { 1075 MachineBasicBlock::iterator MBBI = prior(MBB.end()); 1076 assert(MBBI->getOpcode() == PPC::BLR && 1077 "Can only insert epilog into returning blocks"); 1078 1079 // Get alignment info so we know how to restore r1 1080 const MachineFrameInfo *MFI = MF.getFrameInfo(); 1081 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 1082 unsigned MaxAlign = MFI->getMaxAlignment(); 1083 1084 // Get the number of bytes allocated from the FrameInfo. 1085 unsigned FrameSize = MFI->getStackSize(); 1086 1087 // Get processor type. 1088 bool IsPPC64 = Subtarget.isPPC64(); 1089 // Get operating system 1090 bool IsMachoABI = Subtarget.isMachoABI(); 1091 // Check if the link register (LR) has been used. 1092 bool UsesLR = MFI->hasCalls() || usesLR(MF); 1093 // Do we have a frame pointer for this function? 1094 bool HasFP = hasFP(MF) && FrameSize; 1095 1096 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI); 1097 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI); 1098 1099 if (FrameSize) { 1100 // The loaded (or persistent) stack pointer value is offset by the 'stwu' 1101 // on entry to the function. Add this offset back now. 1102 if (!Subtarget.isPPC64()) { 1103 if (isInt16(FrameSize) && TargetAlign >= MaxAlign && 1104 !MFI->hasVarSizedObjects()) { 1105 BuildMI(MBB, MBBI, TII.get(PPC::ADDI), PPC::R1) 1106 .addReg(PPC::R1).addImm(FrameSize); 1107 } else { 1108 BuildMI(MBB, MBBI, TII.get(PPC::LWZ),PPC::R1).addImm(0).addReg(PPC::R1); 1109 } 1110 } else { 1111 if (isInt16(FrameSize) && TargetAlign >= MaxAlign && 1112 !MFI->hasVarSizedObjects()) { 1113 BuildMI(MBB, MBBI, TII.get(PPC::ADDI8), PPC::X1) 1114 .addReg(PPC::X1).addImm(FrameSize); 1115 } else { 1116 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X1).addImm(0).addReg(PPC::X1); 1117 } 1118 } 1119 } 1120 1121 if (IsPPC64) { 1122 if (UsesLR) 1123 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X0) 1124 .addImm(LROffset/4).addReg(PPC::X1); 1125 1126 if (HasFP) 1127 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X31) 1128 .addImm(FPOffset/4).addReg(PPC::X1); 1129 1130 if (UsesLR) 1131 BuildMI(MBB, MBBI, TII.get(PPC::MTLR8)).addReg(PPC::X0); 1132 } else { 1133 if (UsesLR) 1134 BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R0) 1135 .addImm(LROffset).addReg(PPC::R1); 1136 1137 if (HasFP) 1138 BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R31) 1139 .addImm(FPOffset).addReg(PPC::R1); 1140 1141 if (UsesLR) 1142 BuildMI(MBB, MBBI, TII.get(PPC::MTLR)).addReg(PPC::R0); 1143 } 1144 } 1145 1146 unsigned PPCRegisterInfo::getRARegister() const { 1147 return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8; 1148 } 1149 1150 unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const { 1151 if (!Subtarget.isPPC64()) 1152 return hasFP(MF) ? PPC::R31 : PPC::R1; 1153 else 1154 return hasFP(MF) ? PPC::X31 : PPC::X1; 1155 } 1156 1157 void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) 1158 const { 1159 // Initial state of the frame pointer is R1. 1160 MachineLocation Dst(MachineLocation::VirtualFP); 1161 MachineLocation Src(PPC::R1, 0); 1162 Moves.push_back(MachineMove(0, Dst, Src)); 1163 } 1164 1165 unsigned PPCRegisterInfo::getEHExceptionRegister() const { 1166 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3; 1167 } 1168 1169 unsigned PPCRegisterInfo::getEHHandlerRegister() const { 1170 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4; 1171 } 1172 1173 #include "PPCGenRegisterInfo.inc" 1174 1175