1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file was developed by the LLVM research group and is distributed under 6 // the University of Illinois Open Source License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the MRegisterInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #define DEBUG_TYPE "reginfo" 15 #include "PPC.h" 16 #include "PPCInstrBuilder.h" 17 #include "PPCMachineFunctionInfo.h" 18 #include "PPCRegisterInfo.h" 19 #include "PPCFrameInfo.h" 20 #include "PPCSubtarget.h" 21 #include "llvm/Constants.h" 22 #include "llvm/Type.h" 23 #include "llvm/CodeGen/ValueTypes.h" 24 #include "llvm/CodeGen/MachineInstrBuilder.h" 25 #include "llvm/CodeGen/MachineModuleInfo.h" 26 #include "llvm/CodeGen/MachineFunction.h" 27 #include "llvm/CodeGen/MachineFrameInfo.h" 28 #include "llvm/CodeGen/MachineLocation.h" 29 #include "llvm/CodeGen/SelectionDAGNodes.h" 30 #include "llvm/Target/TargetFrameInfo.h" 31 #include "llvm/Target/TargetInstrInfo.h" 32 #include "llvm/Target/TargetMachine.h" 33 #include "llvm/Target/TargetOptions.h" 34 #include "llvm/Support/CommandLine.h" 35 #include "llvm/Support/Debug.h" 36 #include "llvm/Support/MathExtras.h" 37 #include "llvm/ADT/BitVector.h" 38 #include "llvm/ADT/STLExtras.h" 39 #include <cstdlib> 40 using namespace llvm; 41 42 /// getRegisterNumbering - Given the enum value for some register, e.g. 43 /// PPC::F14, return the number that it corresponds to (e.g. 14). 44 unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) { 45 using namespace PPC; 46 switch (RegEnum) { 47 case R0 : case X0 : case F0 : case V0 : case CR0: return 0; 48 case R1 : case X1 : case F1 : case V1 : case CR1: return 1; 49 case R2 : case X2 : case F2 : case V2 : case CR2: return 2; 50 case R3 : case X3 : case F3 : case V3 : case CR3: return 3; 51 case R4 : case X4 : case F4 : case V4 : case CR4: return 4; 52 case R5 : case X5 : case F5 : case V5 : case CR5: return 5; 53 case R6 : case X6 : case F6 : case V6 : case CR6: return 6; 54 case R7 : case X7 : case F7 : case V7 : case CR7: return 7; 55 case R8 : case X8 : case F8 : case V8 : return 8; 56 case R9 : case X9 : case F9 : case V9 : return 9; 57 case R10: case X10: case F10: case V10: return 10; 58 case R11: case X11: case F11: case V11: return 11; 59 case R12: case X12: case F12: case V12: return 12; 60 case R13: case X13: case F13: case V13: return 13; 61 case R14: case X14: case F14: case V14: return 14; 62 case R15: case X15: case F15: case V15: return 15; 63 case R16: case X16: case F16: case V16: return 16; 64 case R17: case X17: case F17: case V17: return 17; 65 case R18: case X18: case F18: case V18: return 18; 66 case R19: case X19: case F19: case V19: return 19; 67 case R20: case X20: case F20: case V20: return 20; 68 case R21: case X21: case F21: case V21: return 21; 69 case R22: case X22: case F22: case V22: return 22; 70 case R23: case X23: case F23: case V23: return 23; 71 case R24: case X24: case F24: case V24: return 24; 72 case R25: case X25: case F25: case V25: return 25; 73 case R26: case X26: case F26: case V26: return 26; 74 case R27: case X27: case F27: case V27: return 27; 75 case R28: case X28: case F28: case V28: return 28; 76 case R29: case X29: case F29: case V29: return 29; 77 case R30: case X30: case F30: case V30: return 30; 78 case R31: case X31: case F31: case V31: return 31; 79 default: 80 cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n"; 81 abort(); 82 } 83 } 84 85 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST, 86 const TargetInstrInfo &tii) 87 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP), 88 Subtarget(ST), TII(tii) { 89 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 90 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 91 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 92 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 93 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 94 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 95 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 96 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 97 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; 98 } 99 100 void 101 PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 102 MachineBasicBlock::iterator MI, 103 unsigned SrcReg, int FrameIdx, 104 const TargetRegisterClass *RC) const { 105 if (RC == PPC::GPRCRegisterClass) { 106 if (SrcReg != PPC::LR) { 107 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW)) 108 .addReg(SrcReg, false, false, true), FrameIdx); 109 } else { 110 // FIXME: this spills LR immediately to memory in one step. To do this, 111 // we use R11, which we know cannot be used in the prolog/epilog. This is 112 // a hack. 113 BuildMI(MBB, MI, TII.get(PPC::MFLR), PPC::R11); 114 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW)) 115 .addReg(PPC::R11, false, false, true), FrameIdx); 116 } 117 } else if (RC == PPC::G8RCRegisterClass) { 118 if (SrcReg != PPC::LR8) { 119 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STD)) 120 .addReg(SrcReg, false, false, true), FrameIdx); 121 } else { 122 // FIXME: this spills LR immediately to memory in one step. To do this, 123 // we use R11, which we know cannot be used in the prolog/epilog. This is 124 // a hack. 125 BuildMI(MBB, MI, TII.get(PPC::MFLR8), PPC::X11); 126 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STD)) 127 .addReg(PPC::X11, false, false, true), FrameIdx); 128 } 129 } else if (RC == PPC::F8RCRegisterClass) { 130 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STFD)) 131 .addReg(SrcReg, false, false, true), FrameIdx); 132 } else if (RC == PPC::F4RCRegisterClass) { 133 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STFS)) 134 .addReg(SrcReg, false, false, true), FrameIdx); 135 } else if (RC == PPC::CRRCRegisterClass) { 136 // FIXME: We use R0 here, because it isn't available for RA. 137 // We need to store the CR in the low 4-bits of the saved value. First, 138 // issue a MFCR to save all of the CRBits. 139 BuildMI(MBB, MI, TII.get(PPC::MFCR), PPC::R0); 140 141 // If the saved register wasn't CR0, shift the bits left so that they are in 142 // CR0's slot. 143 if (SrcReg != PPC::CR0) { 144 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4; 145 // rlwinm r0, r0, ShiftBits, 0, 31. 146 BuildMI(MBB, MI, TII.get(PPC::RLWINM), PPC::R0) 147 .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31); 148 } 149 150 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW)) 151 .addReg(PPC::R0, false, false, true), FrameIdx); 152 } else if (RC == PPC::VRRCRegisterClass) { 153 // We don't have indexed addressing for vector loads. Emit: 154 // R11 = ADDI FI# 155 // Dest = LVX R0, R11 156 // 157 // FIXME: We use R0 here, because it isn't available for RA. 158 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::ADDI), PPC::R0), 159 FrameIdx, 0, 0); 160 BuildMI(MBB, MI, TII.get(PPC::STVX)) 161 .addReg(SrcReg, false, false, true).addReg(PPC::R0).addReg(PPC::R0); 162 } else { 163 assert(0 && "Unknown regclass!"); 164 abort(); 165 } 166 } 167 168 void 169 PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 170 MachineBasicBlock::iterator MI, 171 unsigned DestReg, int FrameIdx, 172 const TargetRegisterClass *RC) const { 173 if (RC == PPC::GPRCRegisterClass) { 174 if (DestReg != PPC::LR) { 175 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LWZ), DestReg), FrameIdx); 176 } else { 177 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LWZ), PPC::R11),FrameIdx); 178 BuildMI(MBB, MI, TII.get(PPC::MTLR)).addReg(PPC::R11); 179 } 180 } else if (RC == PPC::G8RCRegisterClass) { 181 if (DestReg != PPC::LR8) { 182 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LD), DestReg), FrameIdx); 183 } else { 184 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LD), PPC::R11), FrameIdx); 185 BuildMI(MBB, MI, TII.get(PPC::MTLR8)).addReg(PPC::R11); 186 } 187 } else if (RC == PPC::F8RCRegisterClass) { 188 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LFD), DestReg), FrameIdx); 189 } else if (RC == PPC::F4RCRegisterClass) { 190 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LFS), DestReg), FrameIdx); 191 } else if (RC == PPC::CRRCRegisterClass) { 192 // FIXME: We use R0 here, because it isn't available for RA. 193 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LWZ), PPC::R0), FrameIdx); 194 195 // If the reloaded register isn't CR0, shift the bits right so that they are 196 // in the right CR's slot. 197 if (DestReg != PPC::CR0) { 198 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4; 199 // rlwinm r11, r11, 32-ShiftBits, 0, 31. 200 BuildMI(MBB, MI, TII.get(PPC::RLWINM), PPC::R0) 201 .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31); 202 } 203 204 BuildMI(MBB, MI, TII.get(PPC::MTCRF), DestReg).addReg(PPC::R0); 205 } else if (RC == PPC::VRRCRegisterClass) { 206 // We don't have indexed addressing for vector loads. Emit: 207 // R11 = ADDI FI# 208 // Dest = LVX R0, R11 209 // 210 // FIXME: We use R0 here, because it isn't available for RA. 211 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::ADDI), PPC::R0), 212 FrameIdx, 0, 0); 213 BuildMI(MBB, MI, TII.get(PPC::LVX),DestReg).addReg(PPC::R0).addReg(PPC::R0); 214 } else { 215 assert(0 && "Unknown regclass!"); 216 abort(); 217 } 218 } 219 220 void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, 221 MachineBasicBlock::iterator MI, 222 unsigned DestReg, unsigned SrcReg, 223 const TargetRegisterClass *RC) const { 224 if (RC == PPC::GPRCRegisterClass) { 225 BuildMI(MBB, MI, TII.get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg); 226 } else if (RC == PPC::G8RCRegisterClass) { 227 BuildMI(MBB, MI, TII.get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg); 228 } else if (RC == PPC::F4RCRegisterClass) { 229 BuildMI(MBB, MI, TII.get(PPC::FMRS), DestReg).addReg(SrcReg); 230 } else if (RC == PPC::F8RCRegisterClass) { 231 BuildMI(MBB, MI, TII.get(PPC::FMRD), DestReg).addReg(SrcReg); 232 } else if (RC == PPC::CRRCRegisterClass) { 233 BuildMI(MBB, MI, TII.get(PPC::MCRF), DestReg).addReg(SrcReg); 234 } else if (RC == PPC::VRRCRegisterClass) { 235 BuildMI(MBB, MI, TII.get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg); 236 } else { 237 cerr << "Attempt to copy register that is not GPR or FPR"; 238 abort(); 239 } 240 } 241 242 const unsigned* PPCRegisterInfo::getCalleeSavedRegs() const { 243 // 32-bit Darwin calling convention. 244 static const unsigned Darwin32_CalleeSavedRegs[] = { 245 PPC::R13, PPC::R14, PPC::R15, 246 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 247 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 248 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 249 PPC::R28, PPC::R29, PPC::R30, PPC::R31, 250 251 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 252 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 253 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 254 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 255 PPC::F30, PPC::F31, 256 257 PPC::CR2, PPC::CR3, PPC::CR4, 258 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 259 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 260 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 261 262 PPC::LR, 0 263 }; 264 265 static const unsigned ELF32_CalleeSavedRegs[] = { 266 PPC::R13, PPC::R14, PPC::R15, 267 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 268 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 269 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 270 PPC::R28, PPC::R29, PPC::R30, PPC::R31, 271 272 PPC::F11, PPC::F12, PPC::F13, 273 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 274 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 275 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 276 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 277 PPC::F30, PPC::F31, 278 279 PPC::CR2, PPC::CR3, PPC::CR4, 280 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 281 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 282 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 283 284 PPC::LR, 0 285 }; 286 // 64-bit Darwin calling convention. 287 static const unsigned Darwin64_CalleeSavedRegs[] = { 288 PPC::X14, PPC::X15, 289 PPC::X16, PPC::X17, PPC::X18, PPC::X19, 290 PPC::X20, PPC::X21, PPC::X22, PPC::X23, 291 PPC::X24, PPC::X25, PPC::X26, PPC::X27, 292 PPC::X28, PPC::X29, PPC::X30, PPC::X31, 293 294 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 295 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 296 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 297 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 298 PPC::F30, PPC::F31, 299 300 PPC::CR2, PPC::CR3, PPC::CR4, 301 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 302 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 303 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 304 305 PPC::LR8, 0 306 }; 307 308 static const unsigned ELF64_CalleeSavedRegs[] = { 309 PPC::X14, PPC::X15, 310 PPC::X16, PPC::X17, PPC::X18, PPC::X19, 311 PPC::X20, PPC::X21, PPC::X22, PPC::X23, 312 PPC::X24, PPC::X25, PPC::X26, PPC::X27, 313 PPC::X28, PPC::X29, PPC::X30, PPC::X31, 314 315 PPC::F11, PPC::F12, PPC::F13, 316 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 317 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 318 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 319 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 320 PPC::F30, PPC::F31, 321 322 PPC::CR2, PPC::CR3, PPC::CR4, 323 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 324 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 325 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 326 327 PPC::LR8, 0 328 }; 329 330 if (Subtarget.isMachoABI()) 331 return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegs : 332 Darwin32_CalleeSavedRegs; 333 334 // ELF. 335 return Subtarget.isPPC64() ? ELF64_CalleeSavedRegs : ELF32_CalleeSavedRegs; 336 } 337 338 const TargetRegisterClass* const* 339 PPCRegisterInfo::getCalleeSavedRegClasses() const { 340 // 32-bit Darwin calling convention. 341 static const TargetRegisterClass * const Darwin32_CalleeSavedRegClasses[] = { 342 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 343 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 344 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 345 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 346 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 347 348 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 349 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 350 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 351 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 352 &PPC::F8RCRegClass,&PPC::F8RCRegClass, 353 354 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, 355 356 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 357 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 358 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 359 360 &PPC::GPRCRegClass, 0 361 }; 362 363 static const TargetRegisterClass * const ELF32_CalleeSavedRegClasses[] = { 364 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 365 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 366 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 367 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 368 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 369 370 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 371 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 372 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 373 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 374 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 375 &PPC::F8RCRegClass,&PPC::F8RCRegClass, 376 377 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, 378 379 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 380 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 381 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 382 383 &PPC::GPRCRegClass, 0 384 }; 385 386 // 64-bit Darwin calling convention. 387 static const TargetRegisterClass * const Darwin64_CalleeSavedRegClasses[] = { 388 &PPC::G8RCRegClass,&PPC::G8RCRegClass, 389 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 390 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 391 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 392 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 393 394 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 395 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 396 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 397 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 398 &PPC::F8RCRegClass,&PPC::F8RCRegClass, 399 400 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, 401 402 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 403 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 404 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 405 406 &PPC::G8RCRegClass, 0 407 }; 408 409 static const TargetRegisterClass * const ELF64_CalleeSavedRegClasses[] = { 410 &PPC::G8RCRegClass,&PPC::G8RCRegClass, 411 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 412 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 413 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 414 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 415 416 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 417 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 418 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 419 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 420 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 421 &PPC::F8RCRegClass,&PPC::F8RCRegClass, 422 423 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, 424 425 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 426 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 427 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 428 429 &PPC::G8RCRegClass, 0 430 }; 431 432 if (Subtarget.isMachoABI()) 433 return Subtarget.isPPC64() ? Darwin64_CalleeSavedRegClasses : 434 Darwin32_CalleeSavedRegClasses; 435 436 // ELF. 437 return Subtarget.isPPC64() ? ELF64_CalleeSavedRegClasses : 438 ELF32_CalleeSavedRegClasses; 439 } 440 441 // needsFP - Return true if the specified function should have a dedicated frame 442 // pointer register. This is true if the function has variable sized allocas or 443 // if frame pointer elimination is disabled. 444 // 445 static bool needsFP(const MachineFunction &MF) { 446 const MachineFrameInfo *MFI = MF.getFrameInfo(); 447 return NoFramePointerElim || MFI->hasVarSizedObjects(); 448 } 449 450 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 451 BitVector Reserved(getNumRegs()); 452 Reserved.set(PPC::R0); 453 Reserved.set(PPC::R1); 454 Reserved.set(PPC::LR); 455 // In Linux, r2 is reserved for the OS. 456 if (!Subtarget.isDarwin()) 457 Reserved.set(PPC::R2); 458 // On PPC64, r13 is the thread pointer. Never allocate this register. 459 // Note that this is overconservative, as it also prevents allocation of 460 // R31 when the FP is not needed. 461 if (Subtarget.isPPC64()) { 462 Reserved.set(PPC::R13); 463 Reserved.set(PPC::R31); 464 } 465 if (needsFP(MF)) 466 Reserved.set(PPC::R31); 467 return Reserved; 468 } 469 470 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into 471 /// copy instructions, turning them into load/store instructions. 472 MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI, 473 unsigned OpNum, 474 int FrameIndex) const { 475 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because 476 // it takes more than one instruction to store it. 477 unsigned Opc = MI->getOpcode(); 478 479 MachineInstr *NewMI = NULL; 480 if ((Opc == PPC::OR && 481 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { 482 if (OpNum == 0) { // move -> store 483 unsigned InReg = MI->getOperand(1).getReg(); 484 NewMI = addFrameReference(BuildMI(TII.get(PPC::STW)).addReg(InReg), 485 FrameIndex); 486 } else { // move -> load 487 unsigned OutReg = MI->getOperand(0).getReg(); 488 NewMI = addFrameReference(BuildMI(TII.get(PPC::LWZ), OutReg), 489 FrameIndex); 490 } 491 } else if ((Opc == PPC::OR8 && 492 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { 493 if (OpNum == 0) { // move -> store 494 unsigned InReg = MI->getOperand(1).getReg(); 495 NewMI = addFrameReference(BuildMI(TII.get(PPC::STD)).addReg(InReg), 496 FrameIndex); 497 } else { // move -> load 498 unsigned OutReg = MI->getOperand(0).getReg(); 499 NewMI = addFrameReference(BuildMI(TII.get(PPC::LD), OutReg), FrameIndex); 500 } 501 } else if (Opc == PPC::FMRD) { 502 if (OpNum == 0) { // move -> store 503 unsigned InReg = MI->getOperand(1).getReg(); 504 NewMI = addFrameReference(BuildMI(TII.get(PPC::STFD)).addReg(InReg), 505 FrameIndex); 506 } else { // move -> load 507 unsigned OutReg = MI->getOperand(0).getReg(); 508 NewMI = addFrameReference(BuildMI(TII.get(PPC::LFD), OutReg), FrameIndex); 509 } 510 } else if (Opc == PPC::FMRS) { 511 if (OpNum == 0) { // move -> store 512 unsigned InReg = MI->getOperand(1).getReg(); 513 NewMI = addFrameReference(BuildMI(TII.get(PPC::STFS)).addReg(InReg), 514 FrameIndex); 515 } else { // move -> load 516 unsigned OutReg = MI->getOperand(0).getReg(); 517 NewMI = addFrameReference(BuildMI(TII.get(PPC::LFS), OutReg), FrameIndex); 518 } 519 } 520 521 if (NewMI) 522 NewMI->copyKillDeadInfo(MI); 523 return NewMI; 524 } 525 526 //===----------------------------------------------------------------------===// 527 // Stack Frame Processing methods 528 //===----------------------------------------------------------------------===// 529 530 // hasFP - Return true if the specified function actually has a dedicated frame 531 // pointer register. This is true if the function needs a frame pointer and has 532 // a non-zero stack size. 533 bool PPCRegisterInfo::hasFP(const MachineFunction &MF) const { 534 const MachineFrameInfo *MFI = MF.getFrameInfo(); 535 return MFI->getStackSize() && needsFP(MF); 536 } 537 538 /// usesLR - Returns if the link registers (LR) has been used in the function. 539 /// 540 bool PPCRegisterInfo::usesLR(MachineFunction &MF) const { 541 const bool *PhysRegsUsed = MF.getUsedPhysregs(); 542 return PhysRegsUsed[getRARegister()]; 543 } 544 545 void PPCRegisterInfo:: 546 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 547 MachineBasicBlock::iterator I) const { 548 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions. 549 MBB.erase(I); 550 } 551 552 /// LowerDynamicAlloc - Generate the code for allocating an object in the 553 /// current frame. The sequence of code with be in the general form 554 /// 555 /// addi R0, SP, #frameSize ; get the address of the previous frame 556 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size 557 /// addi Rnew, SP, #maxCalFrameSize ; get the top of the allocation 558 /// 559 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const { 560 // Get the instruction. 561 MachineInstr &MI = *II; 562 // Get the instruction's basic block. 563 MachineBasicBlock &MBB = *MI.getParent(); 564 // Get the basic block's function. 565 MachineFunction &MF = *MBB.getParent(); 566 // Get the frame info. 567 MachineFrameInfo *MFI = MF.getFrameInfo(); 568 // Determine whether 64-bit pointers are used. 569 bool LP64 = Subtarget.isPPC64(); 570 571 // Get the maximum call stack size. 572 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 573 // Get the total frame size. 574 unsigned FrameSize = MFI->getStackSize(); 575 576 // Get stack alignments. 577 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 578 unsigned MaxAlign = MFI->getMaxAlignment(); 579 assert(MaxAlign <= TargetAlign && 580 "Dynamic alloca with large aligns not supported"); 581 582 // Determine the previous frame's address. If FrameSize can't be 583 // represented as 16 bits or we need special alignment, then we load the 584 // previous frame's address from 0(SP). Why not do an addis of the hi? 585 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. 586 // Constructing the constant and adding would take 3 instructions. 587 // Fortunately, a frame greater than 32K is rare. 588 if (MaxAlign < TargetAlign && isInt16(FrameSize)) { 589 BuildMI(MBB, II, TII.get(PPC::ADDI), PPC::R0) 590 .addReg(PPC::R31) 591 .addImm(FrameSize); 592 } else if (LP64) { 593 BuildMI(MBB, II, TII.get(PPC::LD), PPC::X0) 594 .addImm(0) 595 .addReg(PPC::X1); 596 } else { 597 BuildMI(MBB, II, TII.get(PPC::LWZ), PPC::R0) 598 .addImm(0) 599 .addReg(PPC::R1); 600 } 601 602 // Grow the stack and update the stack pointer link, then 603 // determine the address of new allocated space. 604 if (LP64) { 605 BuildMI(MBB, II, TII.get(PPC::STDUX)) 606 .addReg(PPC::X0) 607 .addReg(PPC::X1) 608 .addReg(MI.getOperand(1).getReg()); 609 BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 610 .addReg(PPC::X1) 611 .addImm(maxCallFrameSize); 612 } else { 613 BuildMI(MBB, II, TII.get(PPC::STWUX)) 614 .addReg(PPC::R0) 615 .addReg(PPC::R1) 616 .addReg(MI.getOperand(1).getReg()); 617 BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 618 .addReg(PPC::R1) 619 .addImm(maxCallFrameSize); 620 } 621 622 // Discard the DYNALLOC instruction. 623 MBB.erase(II); 624 } 625 626 void 627 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { 628 // Get the instruction. 629 MachineInstr &MI = *II; 630 // Get the instruction's basic block. 631 MachineBasicBlock &MBB = *MI.getParent(); 632 // Get the basic block's function. 633 MachineFunction &MF = *MBB.getParent(); 634 // Get the frame info. 635 MachineFrameInfo *MFI = MF.getFrameInfo(); 636 637 // Find out which operand is the frame index. 638 unsigned i = 0; 639 while (!MI.getOperand(i).isFrameIndex()) { 640 ++i; 641 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 642 } 643 // Take into account whether it's an add or mem instruction 644 unsigned OffIdx = (i == 2) ? 1 : 2; 645 if (MI.getOpcode() == TargetInstrInfo::INLINEASM) 646 OffIdx = i-1; 647 648 // Get the frame index. 649 int FrameIndex = MI.getOperand(i).getFrameIndex(); 650 651 // Get the frame pointer save index. Users of this index are primarily 652 // DYNALLOC instructions. 653 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 654 int FPSI = FI->getFramePointerSaveIndex(); 655 // Get the instruction opcode. 656 unsigned OpC = MI.getOpcode(); 657 658 // Special case for dynamic alloca. 659 if (FPSI && FrameIndex == FPSI && 660 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { 661 lowerDynamicAlloc(II); 662 return; 663 } 664 665 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 666 MI.getOperand(i).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1, false); 667 668 // Figure out if the offset in the instruction is shifted right two bits. This 669 // is true for instructions like "STD", which the machine implicitly adds two 670 // low zeros to. 671 bool isIXAddr = false; 672 switch (OpC) { 673 case PPC::LWA: 674 case PPC::LD: 675 case PPC::STD: 676 case PPC::STD_32: 677 isIXAddr = true; 678 break; 679 } 680 681 // Now add the frame object offset to the offset from r1. 682 int Offset = MFI->getObjectOffset(FrameIndex); 683 684 if (!isIXAddr) 685 Offset += MI.getOperand(OffIdx).getImmedValue(); 686 else 687 Offset += MI.getOperand(OffIdx).getImmedValue() << 2; 688 689 // If we're not using a Frame Pointer that has been set to the value of the 690 // SP before having the stack size subtracted from it, then add the stack size 691 // to Offset to get the correct offset. 692 Offset += MFI->getStackSize(); 693 694 if (!isInt16(Offset)) { 695 // Insert a set of r0 with the full offset value before the ld, st, or add 696 BuildMI(MBB, II, TII.get(PPC::LIS), PPC::R0).addImm(Offset >> 16); 697 BuildMI(MBB, II, TII.get(PPC::ORI), PPC::R0).addReg(PPC::R0).addImm(Offset); 698 699 // convert into indexed form of the instruction 700 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 701 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 702 assert(ImmToIdxMap.count(OpC) && 703 "No indexed form of load or store available!"); 704 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; 705 MI.setInstrDescriptor(TII.get(NewOpcode)); 706 MI.getOperand(1).ChangeToRegister(MI.getOperand(i).getReg(), false); 707 MI.getOperand(2).ChangeToRegister(PPC::R0, false); 708 } else { 709 if (isIXAddr) { 710 assert((Offset & 3) == 0 && "Invalid frame offset!"); 711 Offset >>= 2; // The actual encoded value has the low two bits zero. 712 } 713 MI.getOperand(OffIdx).ChangeToImmediate(Offset); 714 } 715 } 716 717 /// VRRegNo - Map from a numbered VR register to its enum value. 718 /// 719 static const unsigned short VRRegNo[] = { 720 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 , 721 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, 722 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, 723 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31 724 }; 725 726 /// RemoveVRSaveCode - We have found that this function does not need any code 727 /// to manipulate the VRSAVE register, even though it uses vector registers. 728 /// This can happen when the only registers used are known to be live in or out 729 /// of the function. Remove all of the VRSAVE related code from the function. 730 static void RemoveVRSaveCode(MachineInstr *MI) { 731 MachineBasicBlock *Entry = MI->getParent(); 732 MachineFunction *MF = Entry->getParent(); 733 734 // We know that the MTVRSAVE instruction immediately follows MI. Remove it. 735 MachineBasicBlock::iterator MBBI = MI; 736 ++MBBI; 737 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE); 738 MBBI->eraseFromParent(); 739 740 bool RemovedAllMTVRSAVEs = true; 741 // See if we can find and remove the MTVRSAVE instruction from all of the 742 // epilog blocks. 743 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); 744 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) { 745 // If last instruction is a return instruction, add an epilogue 746 if (!I->empty() && TII.isReturn(I->back().getOpcode())) { 747 bool FoundIt = false; 748 for (MBBI = I->end(); MBBI != I->begin(); ) { 749 --MBBI; 750 if (MBBI->getOpcode() == PPC::MTVRSAVE) { 751 MBBI->eraseFromParent(); // remove it. 752 FoundIt = true; 753 break; 754 } 755 } 756 RemovedAllMTVRSAVEs &= FoundIt; 757 } 758 } 759 760 // If we found and removed all MTVRSAVE instructions, remove the read of 761 // VRSAVE as well. 762 if (RemovedAllMTVRSAVEs) { 763 MBBI = MI; 764 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?"); 765 --MBBI; 766 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?"); 767 MBBI->eraseFromParent(); 768 } 769 770 // Finally, nuke the UPDATE_VRSAVE. 771 MI->eraseFromParent(); 772 } 773 774 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the 775 // instruction selector. Based on the vector registers that have been used, 776 // transform this into the appropriate ORI instruction. 777 static void HandleVRSaveUpdate(MachineInstr *MI, const bool *UsedRegs, 778 const TargetInstrInfo &TII) { 779 unsigned UsedRegMask = 0; 780 for (unsigned i = 0; i != 32; ++i) 781 if (UsedRegs[VRRegNo[i]]) 782 UsedRegMask |= 1 << (31-i); 783 784 // Live in and live out values already must be in the mask, so don't bother 785 // marking them. 786 MachineFunction *MF = MI->getParent()->getParent(); 787 for (MachineFunction::livein_iterator I = 788 MF->livein_begin(), E = MF->livein_end(); I != E; ++I) { 789 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first); 790 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg. 791 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 792 } 793 for (MachineFunction::liveout_iterator I = 794 MF->liveout_begin(), E = MF->liveout_end(); I != E; ++I) { 795 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I); 796 if (VRRegNo[RegNo] == *I) // If this really is a vector reg. 797 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 798 } 799 800 unsigned SrcReg = MI->getOperand(1).getReg(); 801 unsigned DstReg = MI->getOperand(0).getReg(); 802 // If no registers are used, turn this into a copy. 803 if (UsedRegMask == 0) { 804 // Remove all VRSAVE code. 805 RemoveVRSaveCode(MI); 806 return; 807 } else if ((UsedRegMask & 0xFFFF) == UsedRegMask) { 808 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg) 809 .addReg(SrcReg).addImm(UsedRegMask); 810 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { 811 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) 812 .addReg(SrcReg).addImm(UsedRegMask >> 16); 813 } else { 814 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) 815 .addReg(SrcReg).addImm(UsedRegMask >> 16); 816 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg) 817 .addReg(DstReg).addImm(UsedRegMask & 0xFFFF); 818 } 819 820 // Remove the old UPDATE_VRSAVE instruction. 821 MI->eraseFromParent(); 822 } 823 824 /// determineFrameLayout - Determine the size of the frame and maximum call 825 /// frame size. 826 void PPCRegisterInfo::determineFrameLayout(MachineFunction &MF) const { 827 MachineFrameInfo *MFI = MF.getFrameInfo(); 828 829 // Get the number of bytes to allocate from the FrameInfo 830 unsigned FrameSize = MFI->getStackSize(); 831 832 // Get the alignments provided by the target, and the maximum alignment 833 // (if any) of the fixed frame objects. 834 unsigned MaxAlign = MFI->getMaxAlignment(); 835 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 836 unsigned AlignMask = TargetAlign - 1; // 837 838 // If we are a leaf function, and use up to 224 bytes of stack space, 839 // don't have a frame pointer, calls, or dynamic alloca then we do not need 840 // to adjust the stack pointer (we fit in the Red Zone). 841 if (FrameSize <= 224 && // Fits in red zone. 842 !MFI->hasVarSizedObjects() && // No dynamic alloca. 843 !MFI->hasCalls() && // No calls. 844 MaxAlign <= TargetAlign) { // No special alignment. 845 // No need for frame 846 MFI->setStackSize(0); 847 return; 848 } 849 850 // Get the maximum call frame size of all the calls. 851 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 852 853 // Maximum call frame needs to be at least big enough for linkage and 8 args. 854 unsigned minCallFrameSize = 855 PPCFrameInfo::getMinCallFrameSize(Subtarget.isPPC64(), 856 Subtarget.isMachoABI()); 857 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize); 858 859 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so 860 // that allocations will be aligned. 861 if (MFI->hasVarSizedObjects()) 862 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask; 863 864 // Update maximum call frame size. 865 MFI->setMaxCallFrameSize(maxCallFrameSize); 866 867 // Include call frame size in total. 868 FrameSize += maxCallFrameSize; 869 870 // Make sure the frame is aligned. 871 FrameSize = (FrameSize + AlignMask) & ~AlignMask; 872 873 // Update frame info. 874 MFI->setStackSize(FrameSize); 875 } 876 877 void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const { 878 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB 879 MachineBasicBlock::iterator MBBI = MBB.begin(); 880 MachineFrameInfo *MFI = MF.getFrameInfo(); 881 MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); 882 883 // Prepare for frame info. 884 unsigned FrameLabelId = 0; 885 886 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it, 887 // process it. 888 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { 889 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) { 890 HandleVRSaveUpdate(MBBI, MF.getUsedPhysregs(), TII); 891 break; 892 } 893 } 894 895 // Move MBBI back to the beginning of the function. 896 MBBI = MBB.begin(); 897 898 // Work out frame sizes. 899 determineFrameLayout(MF); 900 unsigned FrameSize = MFI->getStackSize(); 901 902 // Skip if a leaf routine. 903 if (!FrameSize) return; 904 905 int NegFrameSize = -FrameSize; 906 907 // Get processor type. 908 bool IsPPC64 = Subtarget.isPPC64(); 909 // Get operating system 910 bool IsMachoABI = Subtarget.isMachoABI(); 911 // Check if the link register (LR) has been used. 912 bool UsesLR = MFI->hasCalls() || usesLR(MF); 913 // Do we have a frame pointer for this function? 914 bool HasFP = hasFP(MF); 915 916 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI); 917 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI); 918 919 if (IsPPC64) { 920 if (UsesLR) 921 BuildMI(MBB, MBBI, TII.get(PPC::MFLR8), PPC::X0); 922 923 if (HasFP) 924 BuildMI(MBB, MBBI, TII.get(PPC::STD)) 925 .addReg(PPC::X31).addImm(FPOffset/4).addReg(PPC::X1); 926 927 if (UsesLR) 928 BuildMI(MBB, MBBI, TII.get(PPC::STD)) 929 .addReg(PPC::X0).addImm(LROffset/4).addReg(PPC::X1); 930 } else { 931 if (UsesLR) 932 BuildMI(MBB, MBBI, TII.get(PPC::MFLR), PPC::R0); 933 934 if (HasFP) 935 BuildMI(MBB, MBBI, TII.get(PPC::STW)) 936 .addReg(PPC::R31).addImm(FPOffset).addReg(PPC::R1); 937 938 if (UsesLR) 939 BuildMI(MBB, MBBI, TII.get(PPC::STW)) 940 .addReg(PPC::R0).addImm(LROffset).addReg(PPC::R1); 941 } 942 943 // Get stack alignments. 944 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 945 unsigned MaxAlign = MFI->getMaxAlignment(); 946 947 if (MMI && MMI->needsFrameInfo()) { 948 // Mark effective beginning of when frame pointer becomes valid. 949 FrameLabelId = MMI->NextLabelID(); 950 BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(FrameLabelId); 951 } 952 953 // Adjust stack pointer: r1 += NegFrameSize. 954 // If there is a preferred stack alignment, align R1 now 955 if (!IsPPC64) { 956 // PPC32. 957 if (MaxAlign > TargetAlign) { 958 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!"); 959 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!"); 960 BuildMI(MBB, MBBI, TII.get(PPC::RLWINM), PPC::R0) 961 .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31); 962 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC) ,PPC::R0).addReg(PPC::R0) 963 .addImm(NegFrameSize); 964 BuildMI(MBB, MBBI, TII.get(PPC::STWUX)) 965 .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0); 966 } else if (isInt16(NegFrameSize)) { 967 BuildMI(MBB, MBBI, TII.get(PPC::STWU), 968 PPC::R1).addReg(PPC::R1).addImm(NegFrameSize).addReg(PPC::R1); 969 } else { 970 BuildMI(MBB, MBBI, TII.get(PPC::LIS), PPC::R0).addImm(NegFrameSize >> 16); 971 BuildMI(MBB, MBBI, TII.get(PPC::ORI), PPC::R0).addReg(PPC::R0) 972 .addImm(NegFrameSize & 0xFFFF); 973 BuildMI(MBB, MBBI, TII.get(PPC::STWUX)).addReg(PPC::R1).addReg(PPC::R1) 974 .addReg(PPC::R0); 975 } 976 } else { // PPC64. 977 if (MaxAlign > TargetAlign) { 978 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!"); 979 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!"); 980 BuildMI(MBB, MBBI, TII.get(PPC::RLDICL), PPC::X0) 981 .addReg(PPC::X1).addImm(0).addImm(64-Log2_32(MaxAlign)); 982 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC8), PPC::X0).addReg(PPC::X0) 983 .addImm(NegFrameSize); 984 BuildMI(MBB, MBBI, TII.get(PPC::STDUX)) 985 .addReg(PPC::X1).addReg(PPC::X1).addReg(PPC::X0); 986 } else if (isInt16(NegFrameSize)) { 987 BuildMI(MBB, MBBI, TII.get(PPC::STDU), PPC::X1) 988 .addReg(PPC::X1).addImm(NegFrameSize/4).addReg(PPC::X1); 989 } else { 990 BuildMI(MBB, MBBI, TII.get(PPC::LIS8), PPC::X0).addImm(NegFrameSize >>16); 991 BuildMI(MBB, MBBI, TII.get(PPC::ORI8), PPC::X0).addReg(PPC::X0) 992 .addImm(NegFrameSize & 0xFFFF); 993 BuildMI(MBB, MBBI, TII.get(PPC::STDUX)).addReg(PPC::X1).addReg(PPC::X1) 994 .addReg(PPC::X0); 995 } 996 } 997 998 if (MMI && MMI->needsFrameInfo()) { 999 std::vector<MachineMove> &Moves = MMI->getFrameMoves(); 1000 1001 if (NegFrameSize) { 1002 // Show update of SP. 1003 MachineLocation SPDst(MachineLocation::VirtualFP); 1004 MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize); 1005 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc)); 1006 } else { 1007 MachineLocation SP(IsPPC64 ? PPC::X31 : PPC::R31); 1008 Moves.push_back(MachineMove(FrameLabelId, SP, SP)); 1009 } 1010 1011 if (HasFP) { 1012 MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset); 1013 MachineLocation FPSrc(IsPPC64 ? PPC::X31 : PPC::R31); 1014 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc)); 1015 } 1016 1017 // Add callee saved registers to move list. 1018 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 1019 for (unsigned I = 0, E = CSI.size(); I != E; ++I) { 1020 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx()); 1021 unsigned Reg = CSI[I].getReg(); 1022 if (Reg == PPC::LR || Reg == PPC::LR8) continue; 1023 MachineLocation CSDst(MachineLocation::VirtualFP, Offset); 1024 MachineLocation CSSrc(Reg); 1025 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc)); 1026 } 1027 1028 MachineLocation LRDst(MachineLocation::VirtualFP, LROffset); 1029 MachineLocation LRSrc(IsPPC64 ? PPC::LR8 : PPC::LR); 1030 Moves.push_back(MachineMove(FrameLabelId, LRDst, LRSrc)); 1031 1032 // Mark effective beginning of when frame pointer is ready. 1033 unsigned ReadyLabelId = MMI->NextLabelID(); 1034 BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(ReadyLabelId); 1035 1036 MachineLocation FPDst(HasFP ? (IsPPC64 ? PPC::X31 : PPC::R31) : 1037 (IsPPC64 ? PPC::X1 : PPC::R1)); 1038 MachineLocation FPSrc(MachineLocation::VirtualFP); 1039 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc)); 1040 } 1041 1042 // If there is a frame pointer, copy R1 into R31 1043 if (HasFP) { 1044 if (!IsPPC64) { 1045 BuildMI(MBB, MBBI, TII.get(PPC::OR), PPC::R31).addReg(PPC::R1) 1046 .addReg(PPC::R1); 1047 } else { 1048 BuildMI(MBB, MBBI, TII.get(PPC::OR8), PPC::X31).addReg(PPC::X1) 1049 .addReg(PPC::X1); 1050 } 1051 } 1052 } 1053 1054 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF, 1055 MachineBasicBlock &MBB) const { 1056 MachineBasicBlock::iterator MBBI = prior(MBB.end()); 1057 assert(MBBI->getOpcode() == PPC::BLR && 1058 "Can only insert epilog into returning blocks"); 1059 1060 // Get alignment info so we know how to restore r1 1061 const MachineFrameInfo *MFI = MF.getFrameInfo(); 1062 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 1063 unsigned MaxAlign = MFI->getMaxAlignment(); 1064 1065 // Get the number of bytes allocated from the FrameInfo. 1066 unsigned FrameSize = MFI->getStackSize(); 1067 1068 if (!FrameSize) return; 1069 1070 // Get processor type. 1071 bool IsPPC64 = Subtarget.isPPC64(); 1072 // Get operating system 1073 bool IsMachoABI = Subtarget.isMachoABI(); 1074 // Check if the link register (LR) has been used. 1075 bool UsesLR = MFI->hasCalls() || usesLR(MF); 1076 // Do we have a frame pointer for this function? 1077 bool HasFP = hasFP(MF); 1078 1079 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI); 1080 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI); 1081 1082 // The loaded (or persistent) stack pointer value is offset by the 'stwu' 1083 // on entry to the function. Add this offset back now. 1084 if (!Subtarget.isPPC64()) { 1085 if (isInt16(FrameSize) && TargetAlign >= MaxAlign && 1086 !MFI->hasVarSizedObjects()) { 1087 BuildMI(MBB, MBBI, TII.get(PPC::ADDI), PPC::R1) 1088 .addReg(PPC::R1).addImm(FrameSize); 1089 } else { 1090 BuildMI(MBB, MBBI, TII.get(PPC::LWZ),PPC::R1).addImm(0).addReg(PPC::R1); 1091 } 1092 } else { 1093 if (isInt16(FrameSize) && TargetAlign >= MaxAlign && 1094 !MFI->hasVarSizedObjects()) { 1095 BuildMI(MBB, MBBI, TII.get(PPC::ADDI8), PPC::X1) 1096 .addReg(PPC::X1).addImm(FrameSize); 1097 } else { 1098 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X1).addImm(0).addReg(PPC::X1); 1099 } 1100 } 1101 1102 1103 if (IsPPC64) { 1104 if (UsesLR) 1105 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X0) 1106 .addImm(LROffset/4).addReg(PPC::X1); 1107 1108 if (HasFP) 1109 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X31) 1110 .addImm(FPOffset/4).addReg(PPC::X1); 1111 1112 if (UsesLR) 1113 BuildMI(MBB, MBBI, TII.get(PPC::MTLR8)).addReg(PPC::X0); 1114 } else { 1115 if (UsesLR) 1116 BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R0) 1117 .addImm(LROffset).addReg(PPC::R1); 1118 1119 if (HasFP) 1120 BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R31) 1121 .addImm(FPOffset).addReg(PPC::R1); 1122 1123 if (UsesLR) 1124 BuildMI(MBB, MBBI, TII.get(PPC::MTLR)).addReg(PPC::R0); 1125 } 1126 } 1127 1128 unsigned PPCRegisterInfo::getRARegister() const { 1129 return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8; 1130 } 1131 1132 unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const { 1133 if (!Subtarget.isPPC64()) 1134 return hasFP(MF) ? PPC::R31 : PPC::R1; 1135 else 1136 return hasFP(MF) ? PPC::X31 : PPC::X1; 1137 } 1138 1139 void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) 1140 const { 1141 // Initial state of the frame pointer is R1. 1142 MachineLocation Dst(MachineLocation::VirtualFP); 1143 MachineLocation Src(PPC::R1, 0); 1144 Moves.push_back(MachineMove(0, Dst, Src)); 1145 } 1146 1147 unsigned PPCRegisterInfo::getEHExceptionRegister() const { 1148 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3; 1149 } 1150 1151 unsigned PPCRegisterInfo::getEHHandlerRegister() const { 1152 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4; 1153 } 1154 1155 #include "PPCGenRegisterInfo.inc" 1156 1157