1 //===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the TargetRegisterInfo 11 // class. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "PPCRegisterInfo.h" 16 #include "PPC.h" 17 #include "PPCFrameLowering.h" 18 #include "PPCInstrBuilder.h" 19 #include "PPCMachineFunctionInfo.h" 20 #include "PPCSubtarget.h" 21 #include "llvm/ADT/BitVector.h" 22 #include "llvm/ADT/STLExtras.h" 23 #include "llvm/CodeGen/MachineFrameInfo.h" 24 #include "llvm/CodeGen/MachineFunction.h" 25 #include "llvm/CodeGen/MachineInstrBuilder.h" 26 #include "llvm/CodeGen/MachineModuleInfo.h" 27 #include "llvm/CodeGen/MachineRegisterInfo.h" 28 #include "llvm/CodeGen/RegisterScavenging.h" 29 #include "llvm/IR/CallingConv.h" 30 #include "llvm/IR/Constants.h" 31 #include "llvm/IR/Function.h" 32 #include "llvm/IR/Type.h" 33 #include "llvm/Support/CommandLine.h" 34 #include "llvm/Support/Debug.h" 35 #include "llvm/Support/ErrorHandling.h" 36 #include "llvm/Support/MathExtras.h" 37 #include "llvm/Support/raw_ostream.h" 38 #include "llvm/Target/TargetFrameLowering.h" 39 #include "llvm/Target/TargetInstrInfo.h" 40 #include "llvm/Target/TargetMachine.h" 41 #include "llvm/Target/TargetOptions.h" 42 #include <cstdlib> 43 44 using namespace llvm; 45 46 #define DEBUG_TYPE "reginfo" 47 48 #define GET_REGINFO_TARGET_DESC 49 #include "PPCGenRegisterInfo.inc" 50 51 static cl::opt<bool> 52 EnableBasePointer("ppc-use-base-pointer", cl::Hidden, cl::init(true), 53 cl::desc("Enable use of a base pointer for complex stack frames")); 54 55 static cl::opt<bool> 56 AlwaysBasePointer("ppc-always-use-base-pointer", cl::Hidden, cl::init(false), 57 cl::desc("Force the use of a base pointer in every function")); 58 59 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST) 60 : PPCGenRegisterInfo(ST.isPPC64() ? PPC::LR8 : PPC::LR, 61 ST.isPPC64() ? 0 : 1, 62 ST.isPPC64() ? 0 : 1), 63 Subtarget(ST) { 64 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 65 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 66 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 67 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 68 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 69 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 70 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 71 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 72 ImmToIdxMap[PPC::LWA_32] = PPC::LWAX_32; 73 74 // 64-bit 75 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8; 76 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8; 77 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8; 78 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX; 79 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; 80 } 81 82 /// getPointerRegClass - Return the register class to use to hold pointers. 83 /// This is used for addressing modes. 84 const TargetRegisterClass * 85 PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) 86 const { 87 // Note that PPCInstrInfo::FoldImmediate also directly uses this Kind value 88 // when it checks for ZERO folding. 89 if (Kind == 1) { 90 if (Subtarget.isPPC64()) 91 return &PPC::G8RC_NOX0RegClass; 92 return &PPC::GPRC_NOR0RegClass; 93 } 94 95 if (Subtarget.isPPC64()) 96 return &PPC::G8RCRegClass; 97 return &PPC::GPRCRegClass; 98 } 99 100 const MCPhysReg* 101 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 102 if (MF->getFunction()->getCallingConv() == CallingConv::AnyReg) { 103 if (Subtarget.hasVSX()) 104 return CSR_64_AllRegs_VSX_SaveList; 105 if (Subtarget.hasAltivec()) 106 return CSR_64_AllRegs_Altivec_SaveList; 107 return CSR_64_AllRegs_SaveList; 108 } 109 110 if (Subtarget.isDarwinABI()) 111 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ? 112 CSR_Darwin64_Altivec_SaveList : 113 CSR_Darwin64_SaveList) : 114 (Subtarget.hasAltivec() ? 115 CSR_Darwin32_Altivec_SaveList : 116 CSR_Darwin32_SaveList); 117 118 // On PPC64, we might need to save r2 (but only if it is not reserved). 119 bool SaveR2 = MF->getRegInfo().isAllocatable(PPC::X2); 120 121 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ? 122 (SaveR2 ? CSR_SVR464_R2_Altivec_SaveList : 123 CSR_SVR464_Altivec_SaveList) : 124 (SaveR2 ? CSR_SVR464_R2_SaveList : 125 CSR_SVR464_SaveList)) : 126 (Subtarget.hasAltivec() ? 127 CSR_SVR432_Altivec_SaveList : 128 CSR_SVR432_SaveList); 129 } 130 131 const uint32_t* 132 PPCRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const { 133 if (CC == CallingConv::AnyReg) { 134 if (Subtarget.hasVSX()) 135 return CSR_64_AllRegs_VSX_RegMask; 136 if (Subtarget.hasAltivec()) 137 return CSR_64_AllRegs_Altivec_RegMask; 138 return CSR_64_AllRegs_RegMask; 139 } 140 141 if (Subtarget.isDarwinABI()) 142 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ? 143 CSR_Darwin64_Altivec_RegMask : 144 CSR_Darwin64_RegMask) : 145 (Subtarget.hasAltivec() ? 146 CSR_Darwin32_Altivec_RegMask : 147 CSR_Darwin32_RegMask); 148 149 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ? 150 CSR_SVR464_Altivec_RegMask : 151 CSR_SVR464_RegMask) : 152 (Subtarget.hasAltivec() ? 153 CSR_SVR432_Altivec_RegMask : 154 CSR_SVR432_RegMask); 155 } 156 157 const uint32_t* 158 PPCRegisterInfo::getNoPreservedMask() const { 159 return CSR_NoRegs_RegMask; 160 } 161 162 void PPCRegisterInfo::adjustStackMapLiveOutMask(uint32_t *Mask) const { 163 unsigned PseudoRegs[] = { PPC::ZERO, PPC::ZERO8, PPC::RM }; 164 for (unsigned i = 0, ie = array_lengthof(PseudoRegs); i != ie; ++i) { 165 unsigned Reg = PseudoRegs[i]; 166 Mask[Reg / 32] &= ~(1u << (Reg % 32)); 167 } 168 } 169 170 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 171 BitVector Reserved(getNumRegs()); 172 const PPCFrameLowering *PPCFI = 173 static_cast<const PPCFrameLowering *>(Subtarget.getFrameLowering()); 174 175 // The ZERO register is not really a register, but the representation of r0 176 // when used in instructions that treat r0 as the constant 0. 177 Reserved.set(PPC::ZERO); 178 Reserved.set(PPC::ZERO8); 179 180 // The FP register is also not really a register, but is the representation 181 // of the frame pointer register used by ISD::FRAMEADDR. 182 Reserved.set(PPC::FP); 183 Reserved.set(PPC::FP8); 184 185 // The BP register is also not really a register, but is the representation 186 // of the base pointer register used by setjmp. 187 Reserved.set(PPC::BP); 188 Reserved.set(PPC::BP8); 189 190 // The counter registers must be reserved so that counter-based loops can 191 // be correctly formed (and the mtctr instructions are not DCE'd). 192 Reserved.set(PPC::CTR); 193 Reserved.set(PPC::CTR8); 194 195 Reserved.set(PPC::R1); 196 Reserved.set(PPC::LR); 197 Reserved.set(PPC::LR8); 198 Reserved.set(PPC::RM); 199 200 if (!Subtarget.isDarwinABI() || !Subtarget.hasAltivec()) 201 Reserved.set(PPC::VRSAVE); 202 203 // The SVR4 ABI reserves r2 and r13 204 if (Subtarget.isSVR4ABI()) { 205 Reserved.set(PPC::R2); // System-reserved register 206 Reserved.set(PPC::R13); // Small Data Area pointer register 207 } 208 209 // On PPC64, r13 is the thread pointer. Never allocate this register. 210 if (Subtarget.isPPC64()) { 211 Reserved.set(PPC::R13); 212 213 Reserved.set(PPC::X1); 214 Reserved.set(PPC::X13); 215 216 if (PPCFI->needsFP(MF)) 217 Reserved.set(PPC::X31); 218 219 if (hasBasePointer(MF)) 220 Reserved.set(PPC::X30); 221 222 // The 64-bit SVR4 ABI reserves r2 for the TOC pointer. 223 if (Subtarget.isSVR4ABI()) { 224 // We only reserve r2 if we need to use the TOC pointer. If we have no 225 // explicit uses of the TOC pointer (meaning we're a leaf function with 226 // no constant-pool loads, etc.) and we have no potential uses inside an 227 // inline asm block, then we can treat r2 has an ordinary callee-saved 228 // register. 229 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 230 if (FuncInfo->usesTOCBasePtr() || MF.hasInlineAsm()) 231 Reserved.set(PPC::X2); 232 else 233 Reserved.reset(PPC::R2); 234 } 235 } 236 237 if (PPCFI->needsFP(MF)) 238 Reserved.set(PPC::R31); 239 240 if (hasBasePointer(MF)) { 241 if (Subtarget.isSVR4ABI() && !Subtarget.isPPC64() && 242 MF.getTarget().getRelocationModel() == Reloc::PIC_) 243 Reserved.set(PPC::R29); 244 else 245 Reserved.set(PPC::R30); 246 } 247 248 if (Subtarget.isSVR4ABI() && !Subtarget.isPPC64() && 249 MF.getTarget().getRelocationModel() == Reloc::PIC_) 250 Reserved.set(PPC::R30); 251 252 // Reserve Altivec registers when Altivec is unavailable. 253 if (!Subtarget.hasAltivec()) 254 for (TargetRegisterClass::iterator I = PPC::VRRCRegClass.begin(), 255 IE = PPC::VRRCRegClass.end(); I != IE; ++I) 256 Reserved.set(*I); 257 258 return Reserved; 259 } 260 261 unsigned PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 262 MachineFunction &MF) const { 263 const TargetFrameLowering *TFI = Subtarget.getFrameLowering(); 264 const unsigned DefaultSafety = 1; 265 266 switch (RC->getID()) { 267 default: 268 return 0; 269 case PPC::G8RC_NOX0RegClassID: 270 case PPC::GPRC_NOR0RegClassID: 271 case PPC::G8RCRegClassID: 272 case PPC::GPRCRegClassID: { 273 unsigned FP = TFI->hasFP(MF) ? 1 : 0; 274 return 32 - FP - DefaultSafety; 275 } 276 case PPC::F8RCRegClassID: 277 case PPC::F4RCRegClassID: 278 case PPC::VRRCRegClassID: 279 case PPC::VFRCRegClassID: 280 case PPC::VSLRCRegClassID: 281 case PPC::VSHRCRegClassID: 282 return 32 - DefaultSafety; 283 case PPC::VSRCRegClassID: 284 case PPC::VSFRCRegClassID: 285 return 64 - DefaultSafety; 286 case PPC::CRRCRegClassID: 287 return 8 - DefaultSafety; 288 } 289 } 290 291 const TargetRegisterClass *PPCRegisterInfo::getLargestLegalSuperClass( 292 const TargetRegisterClass *RC) const { 293 if (Subtarget.hasVSX()) { 294 // With VSX, we can inflate various sub-register classes to the full VSX 295 // register set. 296 297 if (RC == &PPC::F8RCRegClass) 298 return &PPC::VSFRCRegClass; 299 else if (RC == &PPC::VRRCRegClass) 300 return &PPC::VSRCRegClass; 301 } 302 303 return TargetRegisterInfo::getLargestLegalSuperClass(RC); 304 } 305 306 //===----------------------------------------------------------------------===// 307 // Stack Frame Processing methods 308 //===----------------------------------------------------------------------===// 309 310 /// lowerDynamicAlloc - Generate the code for allocating an object in the 311 /// current frame. The sequence of code with be in the general form 312 /// 313 /// addi R0, SP, \#frameSize ; get the address of the previous frame 314 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size 315 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation 316 /// 317 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const { 318 // Get the instruction. 319 MachineInstr &MI = *II; 320 // Get the instruction's basic block. 321 MachineBasicBlock &MBB = *MI.getParent(); 322 // Get the basic block's function. 323 MachineFunction &MF = *MBB.getParent(); 324 // Get the frame info. 325 MachineFrameInfo *MFI = MF.getFrameInfo(); 326 // Get the instruction info. 327 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 328 // Determine whether 64-bit pointers are used. 329 bool LP64 = Subtarget.isPPC64(); 330 DebugLoc dl = MI.getDebugLoc(); 331 332 // Get the maximum call stack size. 333 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 334 // Get the total frame size. 335 unsigned FrameSize = MFI->getStackSize(); 336 337 // Get stack alignments. 338 unsigned TargetAlign = Subtarget.getFrameLowering()->getStackAlignment(); 339 unsigned MaxAlign = MFI->getMaxAlignment(); 340 assert((maxCallFrameSize & (MaxAlign-1)) == 0 && 341 "Maximum call-frame size not sufficiently aligned"); 342 343 // Determine the previous frame's address. If FrameSize can't be 344 // represented as 16 bits or we need special alignment, then we load the 345 // previous frame's address from 0(SP). Why not do an addis of the hi? 346 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. 347 // Constructing the constant and adding would take 3 instructions. 348 // Fortunately, a frame greater than 32K is rare. 349 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 350 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 351 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 352 353 if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) { 354 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) 355 .addReg(PPC::R31) 356 .addImm(FrameSize); 357 } else if (LP64) { 358 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg) 359 .addImm(0) 360 .addReg(PPC::X1); 361 } else { 362 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) 363 .addImm(0) 364 .addReg(PPC::R1); 365 } 366 367 bool KillNegSizeReg = MI.getOperand(1).isKill(); 368 unsigned NegSizeReg = MI.getOperand(1).getReg(); 369 370 // Grow the stack and update the stack pointer link, then determine the 371 // address of new allocated space. 372 if (LP64) { 373 if (MaxAlign > TargetAlign) { 374 unsigned UnalNegSizeReg = NegSizeReg; 375 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC); 376 377 // Unfortunately, there is no andi, only andi., and we can't insert that 378 // here because we might clobber cr0 while it is live. 379 BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg) 380 .addImm(~(MaxAlign-1)); 381 382 unsigned NegSizeReg1 = NegSizeReg; 383 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC); 384 BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg) 385 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg)) 386 .addReg(NegSizeReg1, RegState::Kill); 387 KillNegSizeReg = true; 388 } 389 390 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1) 391 .addReg(Reg, RegState::Kill) 392 .addReg(PPC::X1) 393 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg)); 394 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 395 .addReg(PPC::X1) 396 .addImm(maxCallFrameSize); 397 } else { 398 if (MaxAlign > TargetAlign) { 399 unsigned UnalNegSizeReg = NegSizeReg; 400 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); 401 402 // Unfortunately, there is no andi, only andi., and we can't insert that 403 // here because we might clobber cr0 while it is live. 404 BuildMI(MBB, II, dl, TII.get(PPC::LI), NegSizeReg) 405 .addImm(~(MaxAlign-1)); 406 407 unsigned NegSizeReg1 = NegSizeReg; 408 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); 409 BuildMI(MBB, II, dl, TII.get(PPC::AND), NegSizeReg) 410 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg)) 411 .addReg(NegSizeReg1, RegState::Kill); 412 KillNegSizeReg = true; 413 } 414 415 BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1) 416 .addReg(Reg, RegState::Kill) 417 .addReg(PPC::R1) 418 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg)); 419 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 420 .addReg(PPC::R1) 421 .addImm(maxCallFrameSize); 422 } 423 424 // Discard the DYNALLOC instruction. 425 MBB.erase(II); 426 } 427 428 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of 429 /// reserving a whole register (R0), we scrounge for one here. This generates 430 /// code like this: 431 /// 432 /// mfcr rA ; Move the conditional register into GPR rA. 433 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot. 434 /// stw rA, FI ; Store rA to the frame. 435 /// 436 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, 437 unsigned FrameIndex) const { 438 // Get the instruction. 439 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset> 440 // Get the instruction's basic block. 441 MachineBasicBlock &MBB = *MI.getParent(); 442 MachineFunction &MF = *MBB.getParent(); 443 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 444 DebugLoc dl = MI.getDebugLoc(); 445 446 bool LP64 = Subtarget.isPPC64(); 447 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 448 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 449 450 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 451 unsigned SrcReg = MI.getOperand(0).getReg(); 452 453 // We need to store the CR in the low 4-bits of the saved value. First, issue 454 // an MFOCRF to save all of the CRBits and, if needed, kill the SrcReg. 455 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg) 456 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 457 458 // If the saved register wasn't CR0, shift the bits left so that they are in 459 // CR0's slot. 460 if (SrcReg != PPC::CR0) { 461 unsigned Reg1 = Reg; 462 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 463 464 // rlwinm rA, rA, ShiftBits, 0, 31. 465 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 466 .addReg(Reg1, RegState::Kill) 467 .addImm(getEncodingValue(SrcReg) * 4) 468 .addImm(0) 469 .addImm(31); 470 } 471 472 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW)) 473 .addReg(Reg, RegState::Kill), 474 FrameIndex); 475 476 // Discard the pseudo instruction. 477 MBB.erase(II); 478 } 479 480 void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II, 481 unsigned FrameIndex) const { 482 // Get the instruction. 483 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset> 484 // Get the instruction's basic block. 485 MachineBasicBlock &MBB = *MI.getParent(); 486 MachineFunction &MF = *MBB.getParent(); 487 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 488 DebugLoc dl = MI.getDebugLoc(); 489 490 bool LP64 = Subtarget.isPPC64(); 491 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 492 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 493 494 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 495 unsigned DestReg = MI.getOperand(0).getReg(); 496 assert(MI.definesRegister(DestReg) && 497 "RESTORE_CR does not define its destination"); 498 499 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), 500 Reg), FrameIndex); 501 502 // If the reloaded register isn't CR0, shift the bits right so that they are 503 // in the right CR's slot. 504 if (DestReg != PPC::CR0) { 505 unsigned Reg1 = Reg; 506 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 507 508 unsigned ShiftBits = getEncodingValue(DestReg)*4; 509 // rlwinm r11, r11, 32-ShiftBits, 0, 31. 510 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 511 .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0) 512 .addImm(31); 513 } 514 515 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), DestReg) 516 .addReg(Reg, RegState::Kill); 517 518 // Discard the pseudo instruction. 519 MBB.erase(II); 520 } 521 522 static unsigned getCRFromCRBit(unsigned SrcReg) { 523 unsigned Reg = 0; 524 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT || 525 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN) 526 Reg = PPC::CR0; 527 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT || 528 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN) 529 Reg = PPC::CR1; 530 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT || 531 SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN) 532 Reg = PPC::CR2; 533 else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT || 534 SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN) 535 Reg = PPC::CR3; 536 else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT || 537 SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN) 538 Reg = PPC::CR4; 539 else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT || 540 SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN) 541 Reg = PPC::CR5; 542 else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT || 543 SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN) 544 Reg = PPC::CR6; 545 else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT || 546 SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN) 547 Reg = PPC::CR7; 548 549 assert(Reg != 0 && "Invalid CR bit register"); 550 return Reg; 551 } 552 553 void PPCRegisterInfo::lowerCRBitSpilling(MachineBasicBlock::iterator II, 554 unsigned FrameIndex) const { 555 // Get the instruction. 556 MachineInstr &MI = *II; // ; SPILL_CRBIT <SrcReg>, <offset> 557 // Get the instruction's basic block. 558 MachineBasicBlock &MBB = *MI.getParent(); 559 MachineFunction &MF = *MBB.getParent(); 560 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 561 DebugLoc dl = MI.getDebugLoc(); 562 563 bool LP64 = Subtarget.isPPC64(); 564 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 565 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 566 567 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 568 unsigned SrcReg = MI.getOperand(0).getReg(); 569 570 BuildMI(MBB, II, dl, TII.get(TargetOpcode::KILL), 571 getCRFromCRBit(SrcReg)) 572 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 573 574 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg) 575 .addReg(getCRFromCRBit(SrcReg)); 576 577 // If the saved register wasn't CR0LT, shift the bits left so that the bit to 578 // store is the first one. Mask all but that bit. 579 unsigned Reg1 = Reg; 580 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 581 582 // rlwinm rA, rA, ShiftBits, 0, 0. 583 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 584 .addReg(Reg1, RegState::Kill) 585 .addImm(getEncodingValue(SrcReg)) 586 .addImm(0).addImm(0); 587 588 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW)) 589 .addReg(Reg, RegState::Kill), 590 FrameIndex); 591 592 // Discard the pseudo instruction. 593 MBB.erase(II); 594 } 595 596 void PPCRegisterInfo::lowerCRBitRestore(MachineBasicBlock::iterator II, 597 unsigned FrameIndex) const { 598 // Get the instruction. 599 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CRBIT <offset> 600 // Get the instruction's basic block. 601 MachineBasicBlock &MBB = *MI.getParent(); 602 MachineFunction &MF = *MBB.getParent(); 603 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 604 DebugLoc dl = MI.getDebugLoc(); 605 606 bool LP64 = Subtarget.isPPC64(); 607 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 608 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 609 610 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 611 unsigned DestReg = MI.getOperand(0).getReg(); 612 assert(MI.definesRegister(DestReg) && 613 "RESTORE_CRBIT does not define its destination"); 614 615 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), 616 Reg), FrameIndex); 617 618 BuildMI(MBB, II, dl, TII.get(TargetOpcode::IMPLICIT_DEF), DestReg); 619 620 unsigned RegO = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 621 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), RegO) 622 .addReg(getCRFromCRBit(DestReg)); 623 624 unsigned ShiftBits = getEncodingValue(DestReg); 625 // rlwimi r11, r10, 32-ShiftBits, ..., ... 626 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWIMI8 : PPC::RLWIMI), RegO) 627 .addReg(RegO, RegState::Kill).addReg(Reg, RegState::Kill) 628 .addImm(ShiftBits ? 32-ShiftBits : 0) 629 .addImm(ShiftBits).addImm(ShiftBits); 630 631 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), 632 getCRFromCRBit(DestReg)) 633 .addReg(RegO, RegState::Kill) 634 // Make sure we have a use dependency all the way through this 635 // sequence of instructions. We can't have the other bits in the CR 636 // modified in between the mfocrf and the mtocrf. 637 .addReg(getCRFromCRBit(DestReg), RegState::Implicit); 638 639 // Discard the pseudo instruction. 640 MBB.erase(II); 641 } 642 643 void PPCRegisterInfo::lowerVRSAVESpilling(MachineBasicBlock::iterator II, 644 unsigned FrameIndex) const { 645 // Get the instruction. 646 MachineInstr &MI = *II; // ; SPILL_VRSAVE <SrcReg>, <offset> 647 // Get the instruction's basic block. 648 MachineBasicBlock &MBB = *MI.getParent(); 649 MachineFunction &MF = *MBB.getParent(); 650 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 651 DebugLoc dl = MI.getDebugLoc(); 652 653 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 654 unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC); 655 unsigned SrcReg = MI.getOperand(0).getReg(); 656 657 BuildMI(MBB, II, dl, TII.get(PPC::MFVRSAVEv), Reg) 658 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 659 660 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::STW)) 661 .addReg(Reg, RegState::Kill), 662 FrameIndex); 663 664 // Discard the pseudo instruction. 665 MBB.erase(II); 666 } 667 668 void PPCRegisterInfo::lowerVRSAVERestore(MachineBasicBlock::iterator II, 669 unsigned FrameIndex) const { 670 // Get the instruction. 671 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_VRSAVE <offset> 672 // Get the instruction's basic block. 673 MachineBasicBlock &MBB = *MI.getParent(); 674 MachineFunction &MF = *MBB.getParent(); 675 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 676 DebugLoc dl = MI.getDebugLoc(); 677 678 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 679 unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC); 680 unsigned DestReg = MI.getOperand(0).getReg(); 681 assert(MI.definesRegister(DestReg) && 682 "RESTORE_VRSAVE does not define its destination"); 683 684 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::LWZ), 685 Reg), FrameIndex); 686 687 BuildMI(MBB, II, dl, TII.get(PPC::MTVRSAVEv), DestReg) 688 .addReg(Reg, RegState::Kill); 689 690 // Discard the pseudo instruction. 691 MBB.erase(II); 692 } 693 694 bool 695 PPCRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF, 696 unsigned Reg, int &FrameIdx) const { 697 698 // For the nonvolatile condition registers (CR2, CR3, CR4) in an SVR4 699 // ABI, return true to prevent allocating an additional frame slot. 700 // For 64-bit, the CR save area is at SP+8; the value of FrameIdx = 0 701 // is arbitrary and will be subsequently ignored. For 32-bit, we have 702 // previously created the stack slot if needed, so return its FrameIdx. 703 if (Subtarget.isSVR4ABI() && PPC::CR2 <= Reg && Reg <= PPC::CR4) { 704 if (Subtarget.isPPC64()) 705 FrameIdx = 0; 706 else { 707 const PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 708 FrameIdx = FI->getCRSpillFrameIndex(); 709 } 710 return true; 711 } 712 return false; 713 } 714 715 // Figure out if the offset in the instruction must be a multiple of 4. 716 // This is true for instructions like "STD". 717 static bool usesIXAddr(const MachineInstr &MI) { 718 unsigned OpC = MI.getOpcode(); 719 720 switch (OpC) { 721 default: 722 return false; 723 case PPC::LWA: 724 case PPC::LWA_32: 725 case PPC::LD: 726 case PPC::STD: 727 return true; 728 } 729 } 730 731 // Return the OffsetOperandNo given the FIOperandNum (and the instruction). 732 static unsigned getOffsetONFromFION(const MachineInstr &MI, 733 unsigned FIOperandNum) { 734 // Take into account whether it's an add or mem instruction 735 unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2; 736 if (MI.isInlineAsm()) 737 OffsetOperandNo = FIOperandNum - 1; 738 else if (MI.getOpcode() == TargetOpcode::STACKMAP || 739 MI.getOpcode() == TargetOpcode::PATCHPOINT) 740 OffsetOperandNo = FIOperandNum + 1; 741 742 return OffsetOperandNo; 743 } 744 745 void 746 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 747 int SPAdj, unsigned FIOperandNum, 748 RegScavenger *RS) const { 749 assert(SPAdj == 0 && "Unexpected"); 750 751 // Get the instruction. 752 MachineInstr &MI = *II; 753 // Get the instruction's basic block. 754 MachineBasicBlock &MBB = *MI.getParent(); 755 // Get the basic block's function. 756 MachineFunction &MF = *MBB.getParent(); 757 // Get the instruction info. 758 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 759 // Get the frame info. 760 MachineFrameInfo *MFI = MF.getFrameInfo(); 761 DebugLoc dl = MI.getDebugLoc(); 762 763 unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum); 764 765 // Get the frame index. 766 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 767 768 // Get the frame pointer save index. Users of this index are primarily 769 // DYNALLOC instructions. 770 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 771 int FPSI = FI->getFramePointerSaveIndex(); 772 // Get the instruction opcode. 773 unsigned OpC = MI.getOpcode(); 774 775 // Special case for dynamic alloca. 776 if (FPSI && FrameIndex == FPSI && 777 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { 778 lowerDynamicAlloc(II); 779 return; 780 } 781 782 // Special case for pseudo-ops SPILL_CR and RESTORE_CR, etc. 783 if (OpC == PPC::SPILL_CR) { 784 lowerCRSpilling(II, FrameIndex); 785 return; 786 } else if (OpC == PPC::RESTORE_CR) { 787 lowerCRRestore(II, FrameIndex); 788 return; 789 } else if (OpC == PPC::SPILL_CRBIT) { 790 lowerCRBitSpilling(II, FrameIndex); 791 return; 792 } else if (OpC == PPC::RESTORE_CRBIT) { 793 lowerCRBitRestore(II, FrameIndex); 794 return; 795 } else if (OpC == PPC::SPILL_VRSAVE) { 796 lowerVRSAVESpilling(II, FrameIndex); 797 return; 798 } else if (OpC == PPC::RESTORE_VRSAVE) { 799 lowerVRSAVERestore(II, FrameIndex); 800 return; 801 } 802 803 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 804 MI.getOperand(FIOperandNum).ChangeToRegister( 805 FrameIndex < 0 ? getBaseRegister(MF) : getFrameRegister(MF), false); 806 807 // Figure out if the offset in the instruction is shifted right two bits. 808 bool isIXAddr = usesIXAddr(MI); 809 810 // If the instruction is not present in ImmToIdxMap, then it has no immediate 811 // form (and must be r+r). 812 bool noImmForm = !MI.isInlineAsm() && OpC != TargetOpcode::STACKMAP && 813 OpC != TargetOpcode::PATCHPOINT && !ImmToIdxMap.count(OpC); 814 815 // Now add the frame object offset to the offset from r1. 816 int Offset = MFI->getObjectOffset(FrameIndex); 817 Offset += MI.getOperand(OffsetOperandNo).getImm(); 818 819 // If we're not using a Frame Pointer that has been set to the value of the 820 // SP before having the stack size subtracted from it, then add the stack size 821 // to Offset to get the correct offset. 822 // Naked functions have stack size 0, although getStackSize may not reflect that 823 // because we didn't call all the pieces that compute it for naked functions. 824 if (!MF.getFunction()->hasFnAttribute(Attribute::Naked)) { 825 if (!(hasBasePointer(MF) && FrameIndex < 0)) 826 Offset += MFI->getStackSize(); 827 } 828 829 // If we can, encode the offset directly into the instruction. If this is a 830 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If 831 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits 832 // clear can be encoded. This is extremely uncommon, because normally you 833 // only "std" to a stack slot that is at least 4-byte aligned, but it can 834 // happen in invalid code. 835 assert(OpC != PPC::DBG_VALUE && 836 "This should be handled in a target-independent way"); 837 if (!noImmForm && ((isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0)) || 838 OpC == TargetOpcode::STACKMAP || 839 OpC == TargetOpcode::PATCHPOINT)) { 840 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 841 return; 842 } 843 844 // The offset doesn't fit into a single register, scavenge one to build the 845 // offset in. 846 847 bool is64Bit = Subtarget.isPPC64(); 848 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 849 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 850 const TargetRegisterClass *RC = is64Bit ? G8RC : GPRC; 851 unsigned SRegHi = MF.getRegInfo().createVirtualRegister(RC), 852 SReg = MF.getRegInfo().createVirtualRegister(RC); 853 854 // Insert a set of rA with the full offset value before the ld, st, or add 855 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SRegHi) 856 .addImm(Offset >> 16); 857 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg) 858 .addReg(SRegHi, RegState::Kill) 859 .addImm(Offset); 860 861 // Convert into indexed form of the instruction: 862 // 863 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 864 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 865 unsigned OperandBase; 866 867 if (noImmForm) 868 OperandBase = 1; 869 else if (OpC != TargetOpcode::INLINEASM) { 870 assert(ImmToIdxMap.count(OpC) && 871 "No indexed form of load or store available!"); 872 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; 873 MI.setDesc(TII.get(NewOpcode)); 874 OperandBase = 1; 875 } else { 876 OperandBase = OffsetOperandNo; 877 } 878 879 unsigned StackReg = MI.getOperand(FIOperandNum).getReg(); 880 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false); 881 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true); 882 } 883 884 unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 885 const TargetFrameLowering *TFI = Subtarget.getFrameLowering(); 886 887 if (!Subtarget.isPPC64()) 888 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1; 889 else 890 return TFI->hasFP(MF) ? PPC::X31 : PPC::X1; 891 } 892 893 unsigned PPCRegisterInfo::getBaseRegister(const MachineFunction &MF) const { 894 if (!hasBasePointer(MF)) 895 return getFrameRegister(MF); 896 897 if (Subtarget.isPPC64()) 898 return PPC::X30; 899 900 if (Subtarget.isSVR4ABI() && 901 MF.getTarget().getRelocationModel() == Reloc::PIC_) 902 return PPC::R29; 903 904 return PPC::R30; 905 } 906 907 bool PPCRegisterInfo::hasBasePointer(const MachineFunction &MF) const { 908 if (!EnableBasePointer) 909 return false; 910 if (AlwaysBasePointer) 911 return true; 912 913 // If we need to realign the stack, then the stack pointer can no longer 914 // serve as an offset into the caller's stack space. As a result, we need a 915 // base pointer. 916 return needsStackRealignment(MF); 917 } 918 919 bool PPCRegisterInfo::canRealignStack(const MachineFunction &MF) const { 920 if (MF.getFunction()->hasFnAttribute("no-realign-stack")) 921 return false; 922 923 return true; 924 } 925 926 bool PPCRegisterInfo::needsStackRealignment(const MachineFunction &MF) const { 927 const MachineFrameInfo *MFI = MF.getFrameInfo(); 928 const Function *F = MF.getFunction(); 929 unsigned StackAlign = Subtarget.getFrameLowering()->getStackAlignment(); 930 bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) || 931 F->hasFnAttribute(Attribute::StackAlignment)); 932 933 return requiresRealignment && canRealignStack(MF); 934 } 935 936 /// Returns true if the instruction's frame index 937 /// reference would be better served by a base register other than FP 938 /// or SP. Used by LocalStackFrameAllocation to determine which frame index 939 /// references it should create new base registers for. 940 bool PPCRegisterInfo:: 941 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { 942 assert(Offset < 0 && "Local offset must be negative"); 943 944 // It's the load/store FI references that cause issues, as it can be difficult 945 // to materialize the offset if it won't fit in the literal field. Estimate 946 // based on the size of the local frame and some conservative assumptions 947 // about the rest of the stack frame (note, this is pre-regalloc, so 948 // we don't know everything for certain yet) whether this offset is likely 949 // to be out of range of the immediate. Return true if so. 950 951 // We only generate virtual base registers for loads and stores that have 952 // an r+i form. Return false for everything else. 953 unsigned OpC = MI->getOpcode(); 954 if (!ImmToIdxMap.count(OpC)) 955 return false; 956 957 // Don't generate a new virtual base register just to add zero to it. 958 if ((OpC == PPC::ADDI || OpC == PPC::ADDI8) && 959 MI->getOperand(2).getImm() == 0) 960 return false; 961 962 MachineBasicBlock &MBB = *MI->getParent(); 963 MachineFunction &MF = *MBB.getParent(); 964 965 const PPCFrameLowering *PPCFI = 966 static_cast<const PPCFrameLowering *>(Subtarget.getFrameLowering()); 967 unsigned StackEst = 968 PPCFI->determineFrameLayout(MF, false, true); 969 970 // If we likely don't need a stack frame, then we probably don't need a 971 // virtual base register either. 972 if (!StackEst) 973 return false; 974 975 // Estimate an offset from the stack pointer. 976 // The incoming offset is relating to the SP at the start of the function, 977 // but when we access the local it'll be relative to the SP after local 978 // allocation, so adjust our SP-relative offset by that allocation size. 979 Offset += StackEst; 980 981 // The frame pointer will point to the end of the stack, so estimate the 982 // offset as the difference between the object offset and the FP location. 983 return !isFrameOffsetLegal(MI, Offset); 984 } 985 986 /// Insert defining instruction(s) for BaseReg to 987 /// be a pointer to FrameIdx at the beginning of the basic block. 988 void PPCRegisterInfo:: 989 materializeFrameBaseRegister(MachineBasicBlock *MBB, 990 unsigned BaseReg, int FrameIdx, 991 int64_t Offset) const { 992 unsigned ADDriOpc = Subtarget.isPPC64() ? PPC::ADDI8 : PPC::ADDI; 993 994 MachineBasicBlock::iterator Ins = MBB->begin(); 995 DebugLoc DL; // Defaults to "unknown" 996 if (Ins != MBB->end()) 997 DL = Ins->getDebugLoc(); 998 999 const MachineFunction &MF = *MBB->getParent(); 1000 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 1001 const MCInstrDesc &MCID = TII.get(ADDriOpc); 1002 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 1003 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); 1004 1005 BuildMI(*MBB, Ins, DL, MCID, BaseReg) 1006 .addFrameIndex(FrameIdx).addImm(Offset); 1007 } 1008 1009 void PPCRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, 1010 int64_t Offset) const { 1011 unsigned FIOperandNum = 0; 1012 while (!MI.getOperand(FIOperandNum).isFI()) { 1013 ++FIOperandNum; 1014 assert(FIOperandNum < MI.getNumOperands() && 1015 "Instr doesn't have FrameIndex operand!"); 1016 } 1017 1018 MI.getOperand(FIOperandNum).ChangeToRegister(BaseReg, false); 1019 unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum); 1020 Offset += MI.getOperand(OffsetOperandNo).getImm(); 1021 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 1022 1023 MachineBasicBlock &MBB = *MI.getParent(); 1024 MachineFunction &MF = *MBB.getParent(); 1025 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 1026 const MCInstrDesc &MCID = MI.getDesc(); 1027 MachineRegisterInfo &MRI = MF.getRegInfo(); 1028 MRI.constrainRegClass(BaseReg, 1029 TII.getRegClass(MCID, FIOperandNum, this, MF)); 1030 } 1031 1032 bool PPCRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, 1033 int64_t Offset) const { 1034 unsigned FIOperandNum = 0; 1035 while (!MI->getOperand(FIOperandNum).isFI()) { 1036 ++FIOperandNum; 1037 assert(FIOperandNum < MI->getNumOperands() && 1038 "Instr doesn't have FrameIndex operand!"); 1039 } 1040 1041 unsigned OffsetOperandNo = getOffsetONFromFION(*MI, FIOperandNum); 1042 Offset += MI->getOperand(OffsetOperandNo).getImm(); 1043 1044 return MI->getOpcode() == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm 1045 MI->getOpcode() == TargetOpcode::STACKMAP || 1046 MI->getOpcode() == TargetOpcode::PATCHPOINT || 1047 (isInt<16>(Offset) && (!usesIXAddr(*MI) || (Offset & 3) == 0)); 1048 } 1049 1050