1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file was developed by the LLVM research group and is distributed under 6 // the University of Illinois Open Source License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the MRegisterInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #define DEBUG_TYPE "reginfo" 15 #include "PPC.h" 16 #include "PPCInstrBuilder.h" 17 #include "PPCMachineFunctionInfo.h" 18 #include "PPCRegisterInfo.h" 19 #include "PPCFrameInfo.h" 20 #include "PPCSubtarget.h" 21 #include "llvm/Constants.h" 22 #include "llvm/Type.h" 23 #include "llvm/CodeGen/ValueTypes.h" 24 #include "llvm/CodeGen/MachineInstrBuilder.h" 25 #include "llvm/CodeGen/MachineModuleInfo.h" 26 #include "llvm/CodeGen/MachineFunction.h" 27 #include "llvm/CodeGen/MachineFrameInfo.h" 28 #include "llvm/CodeGen/MachineLocation.h" 29 #include "llvm/CodeGen/SelectionDAGNodes.h" 30 #include "llvm/Target/TargetFrameInfo.h" 31 #include "llvm/Target/TargetInstrInfo.h" 32 #include "llvm/Target/TargetMachine.h" 33 #include "llvm/Target/TargetOptions.h" 34 #include "llvm/Support/CommandLine.h" 35 #include "llvm/Support/Debug.h" 36 #include "llvm/Support/MathExtras.h" 37 #include "llvm/ADT/BitVector.h" 38 #include "llvm/ADT/STLExtras.h" 39 #include <cstdlib> 40 using namespace llvm; 41 42 /// getRegisterNumbering - Given the enum value for some register, e.g. 43 /// PPC::F14, return the number that it corresponds to (e.g. 14). 44 unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) { 45 using namespace PPC; 46 switch (RegEnum) { 47 case R0 : case X0 : case F0 : case V0 : case CR0: return 0; 48 case R1 : case X1 : case F1 : case V1 : case CR1: return 1; 49 case R2 : case X2 : case F2 : case V2 : case CR2: return 2; 50 case R3 : case X3 : case F3 : case V3 : case CR3: return 3; 51 case R4 : case X4 : case F4 : case V4 : case CR4: return 4; 52 case R5 : case X5 : case F5 : case V5 : case CR5: return 5; 53 case R6 : case X6 : case F6 : case V6 : case CR6: return 6; 54 case R7 : case X7 : case F7 : case V7 : case CR7: return 7; 55 case R8 : case X8 : case F8 : case V8 : return 8; 56 case R9 : case X9 : case F9 : case V9 : return 9; 57 case R10: case X10: case F10: case V10: return 10; 58 case R11: case X11: case F11: case V11: return 11; 59 case R12: case X12: case F12: case V12: return 12; 60 case R13: case X13: case F13: case V13: return 13; 61 case R14: case X14: case F14: case V14: return 14; 62 case R15: case X15: case F15: case V15: return 15; 63 case R16: case X16: case F16: case V16: return 16; 64 case R17: case X17: case F17: case V17: return 17; 65 case R18: case X18: case F18: case V18: return 18; 66 case R19: case X19: case F19: case V19: return 19; 67 case R20: case X20: case F20: case V20: return 20; 68 case R21: case X21: case F21: case V21: return 21; 69 case R22: case X22: case F22: case V22: return 22; 70 case R23: case X23: case F23: case V23: return 23; 71 case R24: case X24: case F24: case V24: return 24; 72 case R25: case X25: case F25: case V25: return 25; 73 case R26: case X26: case F26: case V26: return 26; 74 case R27: case X27: case F27: case V27: return 27; 75 case R28: case X28: case F28: case V28: return 28; 76 case R29: case X29: case F29: case V29: return 29; 77 case R30: case X30: case F30: case V30: return 30; 78 case R31: case X31: case F31: case V31: return 31; 79 default: 80 cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n"; 81 abort(); 82 } 83 } 84 85 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST, 86 const TargetInstrInfo &tii) 87 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP), 88 Subtarget(ST), TII(tii) { 89 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 90 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 91 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 92 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 93 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 94 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 95 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 96 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 97 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; 98 } 99 100 void 101 PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 102 MachineBasicBlock::iterator MI, 103 unsigned SrcReg, int FrameIdx, 104 const TargetRegisterClass *RC) const { 105 if (RC == PPC::GPRCRegisterClass) { 106 if (SrcReg != PPC::LR) { 107 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW)) 108 .addReg(SrcReg, false, false, true), FrameIdx); 109 } else { 110 // FIXME: this spills LR immediately to memory in one step. To do this, 111 // we use R11, which we know cannot be used in the prolog/epilog. This is 112 // a hack. 113 BuildMI(MBB, MI, TII.get(PPC::MFLR), PPC::R11); 114 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW)) 115 .addReg(PPC::R11, false, false, true), FrameIdx); 116 } 117 } else if (RC == PPC::G8RCRegisterClass) { 118 if (SrcReg != PPC::LR8) { 119 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STD)) 120 .addReg(SrcReg, false, false, true), FrameIdx); 121 } else { 122 // FIXME: this spills LR immediately to memory in one step. To do this, 123 // we use R11, which we know cannot be used in the prolog/epilog. This is 124 // a hack. 125 BuildMI(MBB, MI, TII.get(PPC::MFLR8), PPC::X11); 126 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STD)) 127 .addReg(PPC::X11, false, false, true), FrameIdx); 128 } 129 } else if (RC == PPC::F8RCRegisterClass) { 130 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STFD)) 131 .addReg(SrcReg, false, false, true), FrameIdx); 132 } else if (RC == PPC::F4RCRegisterClass) { 133 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STFS)) 134 .addReg(SrcReg, false, false, true), FrameIdx); 135 } else if (RC == PPC::CRRCRegisterClass) { 136 // FIXME: We use R0 here, because it isn't available for RA. 137 // We need to store the CR in the low 4-bits of the saved value. First, 138 // issue a MFCR to save all of the CRBits. 139 BuildMI(MBB, MI, TII.get(PPC::MFCR), PPC::R0); 140 141 // If the saved register wasn't CR0, shift the bits left so that they are in 142 // CR0's slot. 143 if (SrcReg != PPC::CR0) { 144 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4; 145 // rlwinm r0, r0, ShiftBits, 0, 31. 146 BuildMI(MBB, MI, TII.get(PPC::RLWINM), PPC::R0) 147 .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31); 148 } 149 150 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW)) 151 .addReg(PPC::R0, false, false, true), FrameIdx); 152 } else if (RC == PPC::VRRCRegisterClass) { 153 // We don't have indexed addressing for vector loads. Emit: 154 // R11 = ADDI FI# 155 // Dest = LVX R0, R11 156 // 157 // FIXME: We use R0 here, because it isn't available for RA. 158 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::ADDI), PPC::R0), 159 FrameIdx, 0, 0); 160 BuildMI(MBB, MI, TII.get(PPC::STVX)) 161 .addReg(SrcReg, false, false, true).addReg(PPC::R0).addReg(PPC::R0); 162 } else { 163 assert(0 && "Unknown regclass!"); 164 abort(); 165 } 166 } 167 168 void 169 PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 170 MachineBasicBlock::iterator MI, 171 unsigned DestReg, int FrameIdx, 172 const TargetRegisterClass *RC) const { 173 if (RC == PPC::GPRCRegisterClass) { 174 if (DestReg != PPC::LR) { 175 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LWZ), DestReg), FrameIdx); 176 } else { 177 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LWZ), PPC::R11),FrameIdx); 178 BuildMI(MBB, MI, TII.get(PPC::MTLR)).addReg(PPC::R11); 179 } 180 } else if (RC == PPC::G8RCRegisterClass) { 181 if (DestReg != PPC::LR8) { 182 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LD), DestReg), FrameIdx); 183 } else { 184 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LD), PPC::R11), FrameIdx); 185 BuildMI(MBB, MI, TII.get(PPC::MTLR8)).addReg(PPC::R11); 186 } 187 } else if (RC == PPC::F8RCRegisterClass) { 188 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LFD), DestReg), FrameIdx); 189 } else if (RC == PPC::F4RCRegisterClass) { 190 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LFS), DestReg), FrameIdx); 191 } else if (RC == PPC::CRRCRegisterClass) { 192 // FIXME: We use R0 here, because it isn't available for RA. 193 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LWZ), PPC::R0), FrameIdx); 194 195 // If the reloaded register isn't CR0, shift the bits right so that they are 196 // in the right CR's slot. 197 if (DestReg != PPC::CR0) { 198 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4; 199 // rlwinm r11, r11, 32-ShiftBits, 0, 31. 200 BuildMI(MBB, MI, TII.get(PPC::RLWINM), PPC::R0) 201 .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31); 202 } 203 204 BuildMI(MBB, MI, TII.get(PPC::MTCRF), DestReg).addReg(PPC::R0); 205 } else if (RC == PPC::VRRCRegisterClass) { 206 // We don't have indexed addressing for vector loads. Emit: 207 // R11 = ADDI FI# 208 // Dest = LVX R0, R11 209 // 210 // FIXME: We use R0 here, because it isn't available for RA. 211 addFrameReference(BuildMI(MBB, MI, TII.get(PPC::ADDI), PPC::R0), 212 FrameIdx, 0, 0); 213 BuildMI(MBB, MI, TII.get(PPC::LVX),DestReg).addReg(PPC::R0).addReg(PPC::R0); 214 } else { 215 assert(0 && "Unknown regclass!"); 216 abort(); 217 } 218 } 219 220 void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, 221 MachineBasicBlock::iterator MI, 222 unsigned DestReg, unsigned SrcReg, 223 const TargetRegisterClass *RC) const { 224 if (RC == PPC::GPRCRegisterClass) { 225 BuildMI(MBB, MI, TII.get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg); 226 } else if (RC == PPC::G8RCRegisterClass) { 227 BuildMI(MBB, MI, TII.get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg); 228 } else if (RC == PPC::F4RCRegisterClass) { 229 BuildMI(MBB, MI, TII.get(PPC::FMRS), DestReg).addReg(SrcReg); 230 } else if (RC == PPC::F8RCRegisterClass) { 231 BuildMI(MBB, MI, TII.get(PPC::FMRD), DestReg).addReg(SrcReg); 232 } else if (RC == PPC::CRRCRegisterClass) { 233 BuildMI(MBB, MI, TII.get(PPC::MCRF), DestReg).addReg(SrcReg); 234 } else if (RC == PPC::VRRCRegisterClass) { 235 BuildMI(MBB, MI, TII.get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg); 236 } else { 237 cerr << "Attempt to copy register that is not GPR or FPR"; 238 abort(); 239 } 240 } 241 242 void PPCRegisterInfo::reMaterialize(MachineBasicBlock &MBB, 243 MachineBasicBlock::iterator I, 244 unsigned DestReg, 245 const MachineInstr *Orig) const { 246 MachineInstr *MI = Orig->clone(); 247 MI->getOperand(0).setReg(DestReg); 248 MBB.insert(I, MI); 249 } 250 251 const unsigned* PPCRegisterInfo::getCalleeSavedRegs() const { 252 // 32-bit Darwin calling convention. 253 static const unsigned Macho32_CalleeSavedRegs[] = { 254 PPC::R13, PPC::R14, PPC::R15, 255 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 256 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 257 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 258 PPC::R28, PPC::R29, PPC::R30, PPC::R31, 259 260 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 261 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 262 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 263 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 264 PPC::F30, PPC::F31, 265 266 PPC::CR2, PPC::CR3, PPC::CR4, 267 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 268 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 269 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 270 271 PPC::LR, 0 272 }; 273 274 static const unsigned ELF32_CalleeSavedRegs[] = { 275 PPC::R13, PPC::R14, PPC::R15, 276 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 277 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 278 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 279 PPC::R28, PPC::R29, PPC::R30, PPC::R31, 280 281 PPC::F9, 282 PPC::F10, PPC::F11, PPC::F12, PPC::F13, 283 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 284 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 285 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 286 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 287 PPC::F30, PPC::F31, 288 289 PPC::CR2, PPC::CR3, PPC::CR4, 290 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 291 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 292 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 293 294 PPC::LR, 0 295 }; 296 // 64-bit Darwin calling convention. 297 static const unsigned Macho64_CalleeSavedRegs[] = { 298 PPC::X14, PPC::X15, 299 PPC::X16, PPC::X17, PPC::X18, PPC::X19, 300 PPC::X20, PPC::X21, PPC::X22, PPC::X23, 301 PPC::X24, PPC::X25, PPC::X26, PPC::X27, 302 PPC::X28, PPC::X29, PPC::X30, PPC::X31, 303 304 PPC::F14, PPC::F15, PPC::F16, PPC::F17, 305 PPC::F18, PPC::F19, PPC::F20, PPC::F21, 306 PPC::F22, PPC::F23, PPC::F24, PPC::F25, 307 PPC::F26, PPC::F27, PPC::F28, PPC::F29, 308 PPC::F30, PPC::F31, 309 310 PPC::CR2, PPC::CR3, PPC::CR4, 311 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 312 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 313 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 314 315 PPC::LR8, 0 316 }; 317 318 if (Subtarget.isMachoABI()) 319 return Subtarget.isPPC64() ? Macho64_CalleeSavedRegs : 320 Macho32_CalleeSavedRegs; 321 322 // ELF 32. 323 return ELF32_CalleeSavedRegs; 324 } 325 326 const TargetRegisterClass* const* 327 PPCRegisterInfo::getCalleeSavedRegClasses() const { 328 // 32-bit Macho calling convention. 329 static const TargetRegisterClass * const Macho32_CalleeSavedRegClasses[] = { 330 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 331 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 332 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 333 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 334 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 335 336 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 337 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 338 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 339 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 340 &PPC::F8RCRegClass,&PPC::F8RCRegClass, 341 342 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, 343 344 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 345 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 346 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 347 348 &PPC::GPRCRegClass, 0 349 }; 350 351 static const TargetRegisterClass * const ELF32_CalleeSavedRegClasses[] = { 352 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 353 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 354 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 355 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 356 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass, 357 358 &PPC::F8RCRegClass, 359 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 360 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 361 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 362 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 363 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 364 &PPC::F8RCRegClass,&PPC::F8RCRegClass, 365 366 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, 367 368 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 369 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 370 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 371 372 &PPC::GPRCRegClass, 0 373 }; 374 375 // 64-bit Macho calling convention. 376 static const TargetRegisterClass * const Macho64_CalleeSavedRegClasses[] = { 377 &PPC::G8RCRegClass,&PPC::G8RCRegClass, 378 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 379 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 380 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 381 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass, 382 383 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 384 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 385 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 386 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass, 387 &PPC::F8RCRegClass,&PPC::F8RCRegClass, 388 389 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass, 390 391 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 392 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 393 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass, 394 395 &PPC::G8RCRegClass, 0 396 }; 397 398 if (Subtarget.isMachoABI()) 399 return Subtarget.isPPC64() ? Macho64_CalleeSavedRegClasses : 400 Macho32_CalleeSavedRegClasses; 401 402 // ELF 32. 403 return ELF32_CalleeSavedRegClasses; 404 } 405 406 // needsFP - Return true if the specified function should have a dedicated frame 407 // pointer register. This is true if the function has variable sized allocas or 408 // if frame pointer elimination is disabled. 409 // 410 static bool needsFP(const MachineFunction &MF) { 411 const MachineFrameInfo *MFI = MF.getFrameInfo(); 412 return NoFramePointerElim || MFI->hasVarSizedObjects(); 413 } 414 415 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 416 BitVector Reserved(getNumRegs()); 417 Reserved.set(PPC::R0); 418 Reserved.set(PPC::R1); 419 Reserved.set(PPC::LR); 420 // In Linux, r2 is reserved for the OS. 421 if (!Subtarget.isDarwin()) 422 Reserved.set(PPC::R2); 423 // On PPC64, r13 is the thread pointer. Never allocate this register. 424 // Note that this is overconservative, as it also prevents allocation of 425 // R31 when the FP is not needed. 426 if (Subtarget.isPPC64()) { 427 Reserved.set(PPC::R13); 428 Reserved.set(PPC::R31); 429 } 430 if (needsFP(MF)) 431 Reserved.set(PPC::R31); 432 return Reserved; 433 } 434 435 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into 436 /// copy instructions, turning them into load/store instructions. 437 MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI, 438 unsigned OpNum, 439 int FrameIndex) const { 440 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because 441 // it takes more than one instruction to store it. 442 unsigned Opc = MI->getOpcode(); 443 444 MachineInstr *NewMI = NULL; 445 if ((Opc == PPC::OR && 446 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { 447 if (OpNum == 0) { // move -> store 448 unsigned InReg = MI->getOperand(1).getReg(); 449 NewMI = addFrameReference(BuildMI(TII.get(PPC::STW)).addReg(InReg), 450 FrameIndex); 451 } else { // move -> load 452 unsigned OutReg = MI->getOperand(0).getReg(); 453 NewMI = addFrameReference(BuildMI(TII.get(PPC::LWZ), OutReg), 454 FrameIndex); 455 } 456 } else if ((Opc == PPC::OR8 && 457 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { 458 if (OpNum == 0) { // move -> store 459 unsigned InReg = MI->getOperand(1).getReg(); 460 NewMI = addFrameReference(BuildMI(TII.get(PPC::STD)).addReg(InReg), 461 FrameIndex); 462 } else { // move -> load 463 unsigned OutReg = MI->getOperand(0).getReg(); 464 NewMI = addFrameReference(BuildMI(TII.get(PPC::LD), OutReg), FrameIndex); 465 } 466 } else if (Opc == PPC::FMRD) { 467 if (OpNum == 0) { // move -> store 468 unsigned InReg = MI->getOperand(1).getReg(); 469 NewMI = addFrameReference(BuildMI(TII.get(PPC::STFD)).addReg(InReg), 470 FrameIndex); 471 } else { // move -> load 472 unsigned OutReg = MI->getOperand(0).getReg(); 473 NewMI = addFrameReference(BuildMI(TII.get(PPC::LFD), OutReg), FrameIndex); 474 } 475 } else if (Opc == PPC::FMRS) { 476 if (OpNum == 0) { // move -> store 477 unsigned InReg = MI->getOperand(1).getReg(); 478 NewMI = addFrameReference(BuildMI(TII.get(PPC::STFS)).addReg(InReg), 479 FrameIndex); 480 } else { // move -> load 481 unsigned OutReg = MI->getOperand(0).getReg(); 482 NewMI = addFrameReference(BuildMI(TII.get(PPC::LFS), OutReg), FrameIndex); 483 } 484 } 485 486 if (NewMI) 487 NewMI->copyKillDeadInfo(MI); 488 return NewMI; 489 } 490 491 //===----------------------------------------------------------------------===// 492 // Stack Frame Processing methods 493 //===----------------------------------------------------------------------===// 494 495 // hasFP - Return true if the specified function actually has a dedicated frame 496 // pointer register. This is true if the function needs a frame pointer and has 497 // a non-zero stack size. 498 bool PPCRegisterInfo::hasFP(const MachineFunction &MF) const { 499 const MachineFrameInfo *MFI = MF.getFrameInfo(); 500 return MFI->getStackSize() && needsFP(MF); 501 } 502 503 /// usesLR - Returns if the link registers (LR) has been used in the function. 504 /// 505 bool PPCRegisterInfo::usesLR(MachineFunction &MF) const { 506 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 507 return FI->usesLR(); 508 } 509 510 void PPCRegisterInfo:: 511 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 512 MachineBasicBlock::iterator I) const { 513 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions. 514 MBB.erase(I); 515 } 516 517 /// LowerDynamicAlloc - Generate the code for allocating an object in the 518 /// current frame. The sequence of code with be in the general form 519 /// 520 /// addi R0, SP, #frameSize ; get the address of the previous frame 521 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size 522 /// addi Rnew, SP, #maxCalFrameSize ; get the top of the allocation 523 /// 524 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const { 525 // Get the instruction. 526 MachineInstr &MI = *II; 527 // Get the instruction's basic block. 528 MachineBasicBlock &MBB = *MI.getParent(); 529 // Get the basic block's function. 530 MachineFunction &MF = *MBB.getParent(); 531 // Get the frame info. 532 MachineFrameInfo *MFI = MF.getFrameInfo(); 533 // Determine whether 64-bit pointers are used. 534 bool LP64 = Subtarget.isPPC64(); 535 536 // Get the maximum call stack size. 537 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 538 // Get the total frame size. 539 unsigned FrameSize = MFI->getStackSize(); 540 541 // Get stack alignments. 542 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 543 unsigned MaxAlign = MFI->getMaxAlignment(); 544 assert(MaxAlign <= TargetAlign && 545 "Dynamic alloca with large aligns not supported"); 546 547 // Determine the previous frame's address. If FrameSize can't be 548 // represented as 16 bits or we need special alignment, then we load the 549 // previous frame's address from 0(SP). Why not do an addis of the hi? 550 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. 551 // Constructing the constant and adding would take 3 instructions. 552 // Fortunately, a frame greater than 32K is rare. 553 if (MaxAlign < TargetAlign && isInt16(FrameSize)) { 554 BuildMI(MBB, II, TII.get(PPC::ADDI), PPC::R0) 555 .addReg(PPC::R31) 556 .addImm(FrameSize); 557 } else if (LP64) { 558 BuildMI(MBB, II, TII.get(PPC::LD), PPC::X0) 559 .addImm(0) 560 .addReg(PPC::X1); 561 } else { 562 BuildMI(MBB, II, TII.get(PPC::LWZ), PPC::R0) 563 .addImm(0) 564 .addReg(PPC::R1); 565 } 566 567 // Grow the stack and update the stack pointer link, then 568 // determine the address of new allocated space. 569 if (LP64) { 570 BuildMI(MBB, II, TII.get(PPC::STDUX)) 571 .addReg(PPC::X0) 572 .addReg(PPC::X1) 573 .addReg(MI.getOperand(1).getReg()); 574 BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 575 .addReg(PPC::X1) 576 .addImm(maxCallFrameSize); 577 } else { 578 BuildMI(MBB, II, TII.get(PPC::STWUX)) 579 .addReg(PPC::R0) 580 .addReg(PPC::R1) 581 .addReg(MI.getOperand(1).getReg()); 582 BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 583 .addReg(PPC::R1) 584 .addImm(maxCallFrameSize); 585 } 586 587 // Discard the DYNALLOC instruction. 588 MBB.erase(II); 589 } 590 591 void PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 592 int SPAdj, RegScavenger *RS) const { 593 assert(SPAdj == 0 && "Unexpected"); 594 595 // Get the instruction. 596 MachineInstr &MI = *II; 597 // Get the instruction's basic block. 598 MachineBasicBlock &MBB = *MI.getParent(); 599 // Get the basic block's function. 600 MachineFunction &MF = *MBB.getParent(); 601 // Get the frame info. 602 MachineFrameInfo *MFI = MF.getFrameInfo(); 603 604 // Find out which operand is the frame index. 605 unsigned i = 0; 606 while (!MI.getOperand(i).isFrameIndex()) { 607 ++i; 608 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 609 } 610 // Take into account whether it's an add or mem instruction 611 unsigned OffIdx = (i == 2) ? 1 : 2; 612 if (MI.getOpcode() == TargetInstrInfo::INLINEASM) 613 OffIdx = i-1; 614 615 // Get the frame index. 616 int FrameIndex = MI.getOperand(i).getFrameIndex(); 617 618 // Get the frame pointer save index. Users of this index are primarily 619 // DYNALLOC instructions. 620 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 621 int FPSI = FI->getFramePointerSaveIndex(); 622 // Get the instruction opcode. 623 unsigned OpC = MI.getOpcode(); 624 625 // Special case for dynamic alloca. 626 if (FPSI && FrameIndex == FPSI && 627 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { 628 lowerDynamicAlloc(II); 629 return; 630 } 631 632 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 633 MI.getOperand(i).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1, false); 634 635 // Figure out if the offset in the instruction is shifted right two bits. This 636 // is true for instructions like "STD", which the machine implicitly adds two 637 // low zeros to. 638 bool isIXAddr = false; 639 switch (OpC) { 640 case PPC::LWA: 641 case PPC::LD: 642 case PPC::STD: 643 case PPC::STD_32: 644 isIXAddr = true; 645 break; 646 } 647 648 // Now add the frame object offset to the offset from r1. 649 int Offset = MFI->getObjectOffset(FrameIndex); 650 651 if (!isIXAddr) 652 Offset += MI.getOperand(OffIdx).getImmedValue(); 653 else 654 Offset += MI.getOperand(OffIdx).getImmedValue() << 2; 655 656 // If we're not using a Frame Pointer that has been set to the value of the 657 // SP before having the stack size subtracted from it, then add the stack size 658 // to Offset to get the correct offset. 659 Offset += MFI->getStackSize(); 660 661 if (!isInt16(Offset)) { 662 // Insert a set of r0 with the full offset value before the ld, st, or add 663 BuildMI(MBB, II, TII.get(PPC::LIS), PPC::R0).addImm(Offset >> 16); 664 BuildMI(MBB, II, TII.get(PPC::ORI), PPC::R0).addReg(PPC::R0).addImm(Offset); 665 666 // convert into indexed form of the instruction 667 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 668 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 669 assert(ImmToIdxMap.count(OpC) && 670 "No indexed form of load or store available!"); 671 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; 672 MI.setInstrDescriptor(TII.get(NewOpcode)); 673 MI.getOperand(1).ChangeToRegister(MI.getOperand(i).getReg(), false); 674 MI.getOperand(2).ChangeToRegister(PPC::R0, false); 675 } else { 676 if (isIXAddr) { 677 assert((Offset & 3) == 0 && "Invalid frame offset!"); 678 Offset >>= 2; // The actual encoded value has the low two bits zero. 679 } 680 MI.getOperand(OffIdx).ChangeToImmediate(Offset); 681 } 682 } 683 684 /// VRRegNo - Map from a numbered VR register to its enum value. 685 /// 686 static const unsigned short VRRegNo[] = { 687 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 , 688 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, 689 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, 690 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31 691 }; 692 693 /// RemoveVRSaveCode - We have found that this function does not need any code 694 /// to manipulate the VRSAVE register, even though it uses vector registers. 695 /// This can happen when the only registers used are known to be live in or out 696 /// of the function. Remove all of the VRSAVE related code from the function. 697 static void RemoveVRSaveCode(MachineInstr *MI) { 698 MachineBasicBlock *Entry = MI->getParent(); 699 MachineFunction *MF = Entry->getParent(); 700 701 // We know that the MTVRSAVE instruction immediately follows MI. Remove it. 702 MachineBasicBlock::iterator MBBI = MI; 703 ++MBBI; 704 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE); 705 MBBI->eraseFromParent(); 706 707 bool RemovedAllMTVRSAVEs = true; 708 // See if we can find and remove the MTVRSAVE instruction from all of the 709 // epilog blocks. 710 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); 711 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) { 712 // If last instruction is a return instruction, add an epilogue 713 if (!I->empty() && TII.isReturn(I->back().getOpcode())) { 714 bool FoundIt = false; 715 for (MBBI = I->end(); MBBI != I->begin(); ) { 716 --MBBI; 717 if (MBBI->getOpcode() == PPC::MTVRSAVE) { 718 MBBI->eraseFromParent(); // remove it. 719 FoundIt = true; 720 break; 721 } 722 } 723 RemovedAllMTVRSAVEs &= FoundIt; 724 } 725 } 726 727 // If we found and removed all MTVRSAVE instructions, remove the read of 728 // VRSAVE as well. 729 if (RemovedAllMTVRSAVEs) { 730 MBBI = MI; 731 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?"); 732 --MBBI; 733 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?"); 734 MBBI->eraseFromParent(); 735 } 736 737 // Finally, nuke the UPDATE_VRSAVE. 738 MI->eraseFromParent(); 739 } 740 741 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the 742 // instruction selector. Based on the vector registers that have been used, 743 // transform this into the appropriate ORI instruction. 744 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) { 745 MachineFunction *MF = MI->getParent()->getParent(); 746 747 unsigned UsedRegMask = 0; 748 for (unsigned i = 0; i != 32; ++i) 749 if (MF->isPhysRegUsed(VRRegNo[i])) 750 UsedRegMask |= 1 << (31-i); 751 752 // Live in and live out values already must be in the mask, so don't bother 753 // marking them. 754 for (MachineFunction::livein_iterator I = 755 MF->livein_begin(), E = MF->livein_end(); I != E; ++I) { 756 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first); 757 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg. 758 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 759 } 760 for (MachineFunction::liveout_iterator I = 761 MF->liveout_begin(), E = MF->liveout_end(); I != E; ++I) { 762 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I); 763 if (VRRegNo[RegNo] == *I) // If this really is a vector reg. 764 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 765 } 766 767 unsigned SrcReg = MI->getOperand(1).getReg(); 768 unsigned DstReg = MI->getOperand(0).getReg(); 769 // If no registers are used, turn this into a copy. 770 if (UsedRegMask == 0) { 771 // Remove all VRSAVE code. 772 RemoveVRSaveCode(MI); 773 return; 774 } else if ((UsedRegMask & 0xFFFF) == UsedRegMask) { 775 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg) 776 .addReg(SrcReg).addImm(UsedRegMask); 777 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { 778 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) 779 .addReg(SrcReg).addImm(UsedRegMask >> 16); 780 } else { 781 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg) 782 .addReg(SrcReg).addImm(UsedRegMask >> 16); 783 BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg) 784 .addReg(DstReg).addImm(UsedRegMask & 0xFFFF); 785 } 786 787 // Remove the old UPDATE_VRSAVE instruction. 788 MI->eraseFromParent(); 789 } 790 791 /// determineFrameLayout - Determine the size of the frame and maximum call 792 /// frame size. 793 void PPCRegisterInfo::determineFrameLayout(MachineFunction &MF) const { 794 MachineFrameInfo *MFI = MF.getFrameInfo(); 795 796 // Get the number of bytes to allocate from the FrameInfo 797 unsigned FrameSize = MFI->getStackSize(); 798 799 // Get the alignments provided by the target, and the maximum alignment 800 // (if any) of the fixed frame objects. 801 unsigned MaxAlign = MFI->getMaxAlignment(); 802 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 803 unsigned AlignMask = TargetAlign - 1; // 804 805 // If we are a leaf function, and use up to 224 bytes of stack space, 806 // don't have a frame pointer, calls, or dynamic alloca then we do not need 807 // to adjust the stack pointer (we fit in the Red Zone). 808 if (FrameSize <= 224 && // Fits in red zone. 809 !MFI->hasVarSizedObjects() && // No dynamic alloca. 810 !MFI->hasCalls() && // No calls. 811 MaxAlign <= TargetAlign) { // No special alignment. 812 // No need for frame 813 MFI->setStackSize(0); 814 return; 815 } 816 817 // Get the maximum call frame size of all the calls. 818 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 819 820 // Maximum call frame needs to be at least big enough for linkage and 8 args. 821 unsigned minCallFrameSize = 822 PPCFrameInfo::getMinCallFrameSize(Subtarget.isPPC64(), 823 Subtarget.isMachoABI()); 824 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize); 825 826 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so 827 // that allocations will be aligned. 828 if (MFI->hasVarSizedObjects()) 829 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask; 830 831 // Update maximum call frame size. 832 MFI->setMaxCallFrameSize(maxCallFrameSize); 833 834 // Include call frame size in total. 835 FrameSize += maxCallFrameSize; 836 837 // Make sure the frame is aligned. 838 FrameSize = (FrameSize + AlignMask) & ~AlignMask; 839 840 // Update frame info. 841 MFI->setStackSize(FrameSize); 842 } 843 844 void PPCRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 845 RegScavenger *RS) 846 const { 847 // Save and clear the LR state. 848 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 849 unsigned LR = getRARegister(); 850 FI->setUsesLR(MF.isPhysRegUsed(LR)); 851 MF.setPhysRegUnused(LR); 852 853 // Save R31 if necessary 854 int FPSI = FI->getFramePointerSaveIndex(); 855 bool IsPPC64 = Subtarget.isPPC64(); 856 bool IsELF32_ABI = Subtarget.isELF32_ABI(); 857 bool IsMachoABI = Subtarget.isMachoABI(); 858 const MachineFrameInfo *MFI = MF.getFrameInfo(); 859 860 // If the frame pointer save index hasn't been defined yet. 861 if (!FPSI && (NoFramePointerElim || MFI->hasVarSizedObjects()) 862 && IsELF32_ABI) { 863 // Find out what the fix offset of the frame pointer save area. 864 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, 865 IsMachoABI); 866 // Allocate the frame index for frame pointer save area. 867 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset); 868 // Save the result. 869 FI->setFramePointerSaveIndex(FPSI); 870 } 871 872 } 873 874 void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const { 875 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB 876 MachineBasicBlock::iterator MBBI = MBB.begin(); 877 MachineFrameInfo *MFI = MF.getFrameInfo(); 878 MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); 879 880 // Prepare for frame info. 881 unsigned FrameLabelId = 0; 882 883 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it, 884 // process it. 885 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { 886 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) { 887 HandleVRSaveUpdate(MBBI, TII); 888 break; 889 } 890 } 891 892 // Move MBBI back to the beginning of the function. 893 MBBI = MBB.begin(); 894 895 // Work out frame sizes. 896 determineFrameLayout(MF); 897 unsigned FrameSize = MFI->getStackSize(); 898 899 int NegFrameSize = -FrameSize; 900 901 // Get processor type. 902 bool IsPPC64 = Subtarget.isPPC64(); 903 // Get operating system 904 bool IsMachoABI = Subtarget.isMachoABI(); 905 // Check if the link register (LR) has been used. 906 bool UsesLR = MFI->hasCalls() || usesLR(MF); 907 // Do we have a frame pointer for this function? 908 bool HasFP = hasFP(MF) && FrameSize; 909 910 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI); 911 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI); 912 913 if (IsPPC64) { 914 if (UsesLR) 915 BuildMI(MBB, MBBI, TII.get(PPC::MFLR8), PPC::X0); 916 917 if (HasFP) 918 BuildMI(MBB, MBBI, TII.get(PPC::STD)) 919 .addReg(PPC::X31).addImm(FPOffset/4).addReg(PPC::X1); 920 921 if (UsesLR) 922 BuildMI(MBB, MBBI, TII.get(PPC::STD)) 923 .addReg(PPC::X0).addImm(LROffset/4).addReg(PPC::X1); 924 } else { 925 if (UsesLR) 926 BuildMI(MBB, MBBI, TII.get(PPC::MFLR), PPC::R0); 927 928 if (HasFP) 929 BuildMI(MBB, MBBI, TII.get(PPC::STW)) 930 .addReg(PPC::R31).addImm(FPOffset).addReg(PPC::R1); 931 932 if (UsesLR) 933 BuildMI(MBB, MBBI, TII.get(PPC::STW)) 934 .addReg(PPC::R0).addImm(LROffset).addReg(PPC::R1); 935 } 936 937 // Skip if a leaf routine. 938 if (!FrameSize) return; 939 940 // Get stack alignments. 941 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 942 unsigned MaxAlign = MFI->getMaxAlignment(); 943 944 if (MMI && MMI->needsFrameInfo()) { 945 // Mark effective beginning of when frame pointer becomes valid. 946 FrameLabelId = MMI->NextLabelID(); 947 BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(FrameLabelId); 948 } 949 950 // Adjust stack pointer: r1 += NegFrameSize. 951 // If there is a preferred stack alignment, align R1 now 952 if (!IsPPC64) { 953 // PPC32. 954 if (MaxAlign > TargetAlign) { 955 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!"); 956 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!"); 957 BuildMI(MBB, MBBI, TII.get(PPC::RLWINM), PPC::R0) 958 .addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31); 959 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC) ,PPC::R0).addReg(PPC::R0) 960 .addImm(NegFrameSize); 961 BuildMI(MBB, MBBI, TII.get(PPC::STWUX)) 962 .addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0); 963 } else if (isInt16(NegFrameSize)) { 964 BuildMI(MBB, MBBI, TII.get(PPC::STWU), 965 PPC::R1).addReg(PPC::R1).addImm(NegFrameSize).addReg(PPC::R1); 966 } else { 967 BuildMI(MBB, MBBI, TII.get(PPC::LIS), PPC::R0).addImm(NegFrameSize >> 16); 968 BuildMI(MBB, MBBI, TII.get(PPC::ORI), PPC::R0).addReg(PPC::R0) 969 .addImm(NegFrameSize & 0xFFFF); 970 BuildMI(MBB, MBBI, TII.get(PPC::STWUX)).addReg(PPC::R1).addReg(PPC::R1) 971 .addReg(PPC::R0); 972 } 973 } else { // PPC64. 974 if (MaxAlign > TargetAlign) { 975 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!"); 976 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!"); 977 BuildMI(MBB, MBBI, TII.get(PPC::RLDICL), PPC::X0) 978 .addReg(PPC::X1).addImm(0).addImm(64-Log2_32(MaxAlign)); 979 BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC8), PPC::X0).addReg(PPC::X0) 980 .addImm(NegFrameSize); 981 BuildMI(MBB, MBBI, TII.get(PPC::STDUX)) 982 .addReg(PPC::X1).addReg(PPC::X1).addReg(PPC::X0); 983 } else if (isInt16(NegFrameSize)) { 984 BuildMI(MBB, MBBI, TII.get(PPC::STDU), PPC::X1) 985 .addReg(PPC::X1).addImm(NegFrameSize/4).addReg(PPC::X1); 986 } else { 987 BuildMI(MBB, MBBI, TII.get(PPC::LIS8), PPC::X0).addImm(NegFrameSize >>16); 988 BuildMI(MBB, MBBI, TII.get(PPC::ORI8), PPC::X0).addReg(PPC::X0) 989 .addImm(NegFrameSize & 0xFFFF); 990 BuildMI(MBB, MBBI, TII.get(PPC::STDUX)).addReg(PPC::X1).addReg(PPC::X1) 991 .addReg(PPC::X0); 992 } 993 } 994 995 if (MMI && MMI->needsFrameInfo()) { 996 std::vector<MachineMove> &Moves = MMI->getFrameMoves(); 997 998 if (NegFrameSize) { 999 // Show update of SP. 1000 MachineLocation SPDst(MachineLocation::VirtualFP); 1001 MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize); 1002 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc)); 1003 } else { 1004 MachineLocation SP(IsPPC64 ? PPC::X31 : PPC::R31); 1005 Moves.push_back(MachineMove(FrameLabelId, SP, SP)); 1006 } 1007 1008 if (HasFP) { 1009 MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset); 1010 MachineLocation FPSrc(IsPPC64 ? PPC::X31 : PPC::R31); 1011 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc)); 1012 } 1013 1014 // Add callee saved registers to move list. 1015 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 1016 for (unsigned I = 0, E = CSI.size(); I != E; ++I) { 1017 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx()); 1018 unsigned Reg = CSI[I].getReg(); 1019 if (Reg == PPC::LR || Reg == PPC::LR8) continue; 1020 MachineLocation CSDst(MachineLocation::VirtualFP, Offset); 1021 MachineLocation CSSrc(Reg); 1022 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc)); 1023 } 1024 1025 MachineLocation LRDst(MachineLocation::VirtualFP, LROffset); 1026 MachineLocation LRSrc(IsPPC64 ? PPC::LR8 : PPC::LR); 1027 Moves.push_back(MachineMove(FrameLabelId, LRDst, LRSrc)); 1028 1029 // Mark effective beginning of when frame pointer is ready. 1030 unsigned ReadyLabelId = MMI->NextLabelID(); 1031 BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(ReadyLabelId); 1032 1033 MachineLocation FPDst(HasFP ? (IsPPC64 ? PPC::X31 : PPC::R31) : 1034 (IsPPC64 ? PPC::X1 : PPC::R1)); 1035 MachineLocation FPSrc(MachineLocation::VirtualFP); 1036 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc)); 1037 } 1038 1039 // If there is a frame pointer, copy R1 into R31 1040 if (HasFP) { 1041 if (!IsPPC64) { 1042 BuildMI(MBB, MBBI, TII.get(PPC::OR), PPC::R31).addReg(PPC::R1) 1043 .addReg(PPC::R1); 1044 } else { 1045 BuildMI(MBB, MBBI, TII.get(PPC::OR8), PPC::X31).addReg(PPC::X1) 1046 .addReg(PPC::X1); 1047 } 1048 } 1049 } 1050 1051 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF, 1052 MachineBasicBlock &MBB) const { 1053 MachineBasicBlock::iterator MBBI = prior(MBB.end()); 1054 assert(MBBI->getOpcode() == PPC::BLR && 1055 "Can only insert epilog into returning blocks"); 1056 1057 // Get alignment info so we know how to restore r1 1058 const MachineFrameInfo *MFI = MF.getFrameInfo(); 1059 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 1060 unsigned MaxAlign = MFI->getMaxAlignment(); 1061 1062 // Get the number of bytes allocated from the FrameInfo. 1063 unsigned FrameSize = MFI->getStackSize(); 1064 1065 // Get processor type. 1066 bool IsPPC64 = Subtarget.isPPC64(); 1067 // Get operating system 1068 bool IsMachoABI = Subtarget.isMachoABI(); 1069 // Check if the link register (LR) has been used. 1070 bool UsesLR = MFI->hasCalls() || usesLR(MF); 1071 // Do we have a frame pointer for this function? 1072 bool HasFP = hasFP(MF) && FrameSize; 1073 1074 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI); 1075 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI); 1076 1077 if (FrameSize) { 1078 // The loaded (or persistent) stack pointer value is offset by the 'stwu' 1079 // on entry to the function. Add this offset back now. 1080 if (!Subtarget.isPPC64()) { 1081 if (isInt16(FrameSize) && TargetAlign >= MaxAlign && 1082 !MFI->hasVarSizedObjects()) { 1083 BuildMI(MBB, MBBI, TII.get(PPC::ADDI), PPC::R1) 1084 .addReg(PPC::R1).addImm(FrameSize); 1085 } else { 1086 BuildMI(MBB, MBBI, TII.get(PPC::LWZ),PPC::R1).addImm(0).addReg(PPC::R1); 1087 } 1088 } else { 1089 if (isInt16(FrameSize) && TargetAlign >= MaxAlign && 1090 !MFI->hasVarSizedObjects()) { 1091 BuildMI(MBB, MBBI, TII.get(PPC::ADDI8), PPC::X1) 1092 .addReg(PPC::X1).addImm(FrameSize); 1093 } else { 1094 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X1).addImm(0).addReg(PPC::X1); 1095 } 1096 } 1097 } 1098 1099 if (IsPPC64) { 1100 if (UsesLR) 1101 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X0) 1102 .addImm(LROffset/4).addReg(PPC::X1); 1103 1104 if (HasFP) 1105 BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X31) 1106 .addImm(FPOffset/4).addReg(PPC::X1); 1107 1108 if (UsesLR) 1109 BuildMI(MBB, MBBI, TII.get(PPC::MTLR8)).addReg(PPC::X0); 1110 } else { 1111 if (UsesLR) 1112 BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R0) 1113 .addImm(LROffset).addReg(PPC::R1); 1114 1115 if (HasFP) 1116 BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R31) 1117 .addImm(FPOffset).addReg(PPC::R1); 1118 1119 if (UsesLR) 1120 BuildMI(MBB, MBBI, TII.get(PPC::MTLR)).addReg(PPC::R0); 1121 } 1122 } 1123 1124 unsigned PPCRegisterInfo::getRARegister() const { 1125 return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8; 1126 } 1127 1128 unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const { 1129 if (!Subtarget.isPPC64()) 1130 return hasFP(MF) ? PPC::R31 : PPC::R1; 1131 else 1132 return hasFP(MF) ? PPC::X31 : PPC::X1; 1133 } 1134 1135 void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) 1136 const { 1137 // Initial state of the frame pointer is R1. 1138 MachineLocation Dst(MachineLocation::VirtualFP); 1139 MachineLocation Src(PPC::R1, 0); 1140 Moves.push_back(MachineMove(0, Dst, Src)); 1141 } 1142 1143 unsigned PPCRegisterInfo::getEHExceptionRegister() const { 1144 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3; 1145 } 1146 1147 unsigned PPCRegisterInfo::getEHHandlerRegister() const { 1148 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4; 1149 } 1150 1151 #include "PPCGenRegisterInfo.inc" 1152 1153